openkylin
/
linux
mirror of https://gitee.com/openkylin/linux.git
9
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus 

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
  [MIPS] Malta: Enable tickless and highres timers.
  [MIPS] Bigsur: Enable tickless and and highres timers.
  qemu: do not enable IP7 blindly
  [MIPS] Alchemy: Fix Au1x SD controller IRQ
  [MIPS] Don't byteswap writes to display when running bigendian
This commit is contained in:
Linus Torvalds 2007-12-10 19:45:17 -08:00
parent 3790ee4bd8 ba0f00b9fc
commit c34c15b02e
5 changed files with 25 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
arch/mips/configs/bigsur_defconfig
View File

@ -76,9 +76,13 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_FIND_NEXT_BIT=y
CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_TIME=y CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set # CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
CONFIG_CEVT_BCM1480=y
CONFIG_CSRC_BCM1480=y
CONFIG_DMA_COHERENT=y CONFIG_DMA_COHERENT=y
CONFIG_CPU_BIG_ENDIAN=y CONFIG_CPU_BIG_ENDIAN=y
# CONFIG_CPU_LITTLE_ENDIAN is not set # CONFIG_CPU_LITTLE_ENDIAN is not set
@ -91,6 +95,11 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
# #
# CPU selection # CPU selection
# #
CONFIG_TICK_ONESHOT=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
# CONFIG_CPU_LOONGSON2 is not set
# CONFIG_CPU_MIPS32_R1 is not set # CONFIG_CPU_MIPS32_R1 is not set
# CONFIG_CPU_MIPS32_R2 is not set # CONFIG_CPU_MIPS32_R2 is not set
# CONFIG_CPU_MIPS64_R1 is not set # CONFIG_CPU_MIPS64_R1 is not set

8
arch/mips/configs/malta_defconfig
View File

@ -49,10 +49,13 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_FIND_NEXT_BIT=y
CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_TIME=y CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set # CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
CONFIG_ARCH_MAY_HAVE_PC_FDC=y CONFIG_ARCH_MAY_HAVE_PC_FDC=y
CONFIG_CEVT_R4K=y
CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NONCOHERENT=y
CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_DMA_NEED_PCI_MAP_STATE=y
CONFIG_EARLY_PRINTK=y CONFIG_EARLY_PRINTK=y
@ -76,6 +79,10 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
# #
# CPU selection # CPU selection
# #
CONFIG_TICK_ONESHOT=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
# CONFIG_CPU_LOONGSON2 is not set # CONFIG_CPU_LOONGSON2 is not set
# CONFIG_CPU_MIPS32_R1 is not set # CONFIG_CPU_MIPS32_R1 is not set
CONFIG_CPU_MIPS32_R2=y CONFIG_CPU_MIPS32_R2=y
@ -253,6 +260,7 @@ CONFIG_HW_HAS_PCI=y
CONFIG_PCI=y CONFIG_PCI=y
# CONFIG_ARCH_SUPPORTS_MSI is not set # CONFIG_ARCH_SUPPORTS_MSI is not set
CONFIG_MMU=y CONFIG_MMU=y
CONFIG_I8253=y
# #
# PCCARD (PCMCIA/CardBus) support # PCCARD (PCMCIA/CardBus) support

4
arch/mips/mips-boards/generic/display.c
View File

@ -37,9 +37,9 @@ void mips_display_message(const char *str)
for (i = 0; i <= 14; i=i+2) { for (i = 0; i <= 14; i=i+2) {
if (*str) if (*str)
writel(*str++, display + i); __raw_writel(*str++, display + i);
else else
writel(' ', display + i); __raw_writel(' ', display + i);
} }
} }

2
arch/mips/qemu/q-irq.c
View File

@ -33,5 +33,5 @@ void __init arch_init_irq(void)
mips_cpu_irq_init(); mips_cpu_irq_init();
init_i8259_irqs(); init_i8259_irqs();
set_c0_status(0x8400); set_c0_status(0x400);
} }

7
include/asm-mips/mach-au1x00/au1100_mmc.h
View File

@ -41,8 +41,11 @@
#define NUM_AU1100_MMC_CONTROLLERS 2 #define NUM_AU1100_MMC_CONTROLLERS 2
#if defined(CONFIG_SOC_AU1100)
#define AU1100_SD_IRQ 2 #define AU1100_SD_IRQ AU1100_SD_INT
#elif defined(CONFIG_SOC_AU1200)
#define AU1100_SD_IRQ AU1200_SD_INT
#endif
#define SD0_BASE 0xB0600000 #define SD0_BASE 0xB0600000