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staging: et131x: Remove unnecessary PHY register write 

The PHY registers are now being controlled from the connected phydev,
so there shouldn't be any reason for the et131x code to perform any
extra setup. Removing the interrupt setup code, and register defines
that are now unused.

On testing, no changes in behaviour were experienced.

Signed-off-by: Mark Einon <mark.einon@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Mark Einon 2012-10-30 18:38:58 +00:00 committed by Greg Kroah-Hartman
parent 186c426ddf
commit c35eb3ae57
2 changed files with 1 additions and 19 deletions
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16
drivers/staging/et131x/et131x.c
View File

@ -1749,22 +1749,8 @@ static void et1310_phy_power_down(struct et131x_adapter *adapter, bool down)
*/ */
static void et131x_xcvr_init(struct et131x_adapter *adapter) static void et131x_xcvr_init(struct et131x_adapter *adapter)
{ {
u16 imr;
u16 isr;
u16 lcr2; u16 lcr2;
et131x_mii_read(adapter, PHY_INTERRUPT_STATUS, &isr);
et131x_mii_read(adapter, PHY_INTERRUPT_MASK, &imr);
/* Set the link status interrupt only. Bad behavior when link status
* and auto neg are set, we run into a nested interrupt problem
*/
imr |= (ET_PHY_INT_MASK_AUTONEGSTAT |
ET_PHY_INT_MASK_LINKSTAT |
ET_PHY_INT_MASK_ENABLE);
et131x_mii_write(adapter, PHY_INTERRUPT_MASK, imr);
/* Set the LED behavior such that LED 1 indicates speed (off = /* Set the LED behavior such that LED 1 indicates speed (off =
* 10Mbits, blink = 100Mbits, on = 1000Mbits) and LED 2 indicates * 10Mbits, blink = 100Mbits, on = 1000Mbits) and LED 2 indicates
* link and activity (on for link, blink off for activity). * link and activity (on for link, blink off for activity).
@ -1789,7 +1775,7 @@ static void et131x_xcvr_init(struct et131x_adapter *adapter)
} }
/** /**
* et131x_configure_global_regs - configure JAGCore global regs * et131x_configure_global_regs - configure JAGCore global regs
* @adapter: pointer to our adapter structure * @adapter: pointer to our adapter structure
* *
* Used to configure the global registers on the JAGCore * Used to configure the global registers on the JAGCore

4
drivers/staging/et131x/et131x.h
View File

@ -1538,10 +1538,6 @@ struct address_map {
* 0: int_en * 0: int_en
*/ */
#define ET_PHY_INT_MASK_AUTONEGSTAT 0x0100
#define ET_PHY_INT_MASK_LINKSTAT 0x0004
#define ET_PHY_INT_MASK_ENABLE 0x0001
/* MI Register 25: Interrupt Status Reg(0x19) /* MI Register 25: Interrupt Status Reg(0x19)
* 15-10: reserved * 15-10: reserved
* 9: mdio_sync_lost * 9: mdio_sync_lost