mirror of https://gitee.com/openkylin/linux.git
IRQCHIP: irq-mips-gic: Extend GIC accessors for 64-bit CMs
Previously, the GIC accessors were only accessing u32 registers but newer CMs may actually be 64-bit on MIPS64 cores. As a result of which, extended these accessors to support 64-bit reads and writes. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10709/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Markos Chandras
Ralf Baechle
parent
3885c2b463
commit
c3f57f02e3
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@ -42,20 +42,46 @@ static struct irq_chip gic_level_irq_controller, gic_edge_irq_controller;
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static void __gic_irq_dispatch(void);
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static inline unsigned int gic_read(unsigned int reg)
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static inline u32 gic_read32(unsigned int reg)
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{
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return __raw_readl(gic_base + reg);
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}
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static inline void gic_write(unsigned int reg, unsigned int val)
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static inline u64 gic_read64(unsigned int reg)
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{
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__raw_writel(val, gic_base + reg);
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return __raw_readq(gic_base + reg);
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}
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static inline void gic_update_bits(unsigned int reg, unsigned int mask,
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unsigned int val)
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static inline unsigned long gic_read(unsigned int reg)
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{
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unsigned int regval;
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if (!mips_cm_is64)
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return gic_read32(reg);
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else
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return gic_read64(reg);
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}
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static inline void gic_write32(unsigned int reg, u32 val)
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{
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return __raw_writel(val, gic_base + reg);
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}
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static inline void gic_write64(unsigned int reg, u64 val)
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{
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return __raw_writeq(val, gic_base + reg);
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}
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static inline void gic_write(unsigned int reg, unsigned long val)
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{
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if (!mips_cm_is64)
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return gic_write32(reg, (u32)val);
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else
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return gic_write64(reg, (u64)val);
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}
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static inline void gic_update_bits(unsigned int reg, unsigned long mask,
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unsigned long val)
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{
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unsigned long regval;
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regval = gic_read(reg);
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regval &= ~mask;
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@ -66,40 +92,40 @@ static inline void gic_update_bits(unsigned int reg, unsigned int mask,
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static inline void gic_reset_mask(unsigned int intr)
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{
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gic_write(GIC_REG(SHARED, GIC_SH_RMASK) + GIC_INTR_OFS(intr),
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1 << GIC_INTR_BIT(intr));
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1ul << GIC_INTR_BIT(intr));
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}
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static inline void gic_set_mask(unsigned int intr)
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{
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gic_write(GIC_REG(SHARED, GIC_SH_SMASK) + GIC_INTR_OFS(intr),
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1 << GIC_INTR_BIT(intr));
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1ul << GIC_INTR_BIT(intr));
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}
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static inline void gic_set_polarity(unsigned int intr, unsigned int pol)
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{
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gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_POLARITY) +
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GIC_INTR_OFS(intr), 1 << GIC_INTR_BIT(intr),
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pol << GIC_INTR_BIT(intr));
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GIC_INTR_OFS(intr), 1ul << GIC_INTR_BIT(intr),
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(unsigned long)pol << GIC_INTR_BIT(intr));
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}
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static inline void gic_set_trigger(unsigned int intr, unsigned int trig)
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{
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gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_TRIGGER) +
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GIC_INTR_OFS(intr), 1 << GIC_INTR_BIT(intr),
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trig << GIC_INTR_BIT(intr));
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GIC_INTR_OFS(intr), 1ul << GIC_INTR_BIT(intr),
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(unsigned long)trig << GIC_INTR_BIT(intr));
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}
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static inline void gic_set_dual_edge(unsigned int intr, unsigned int dual)
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{
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gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_DUAL) + GIC_INTR_OFS(intr),
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1 << GIC_INTR_BIT(intr),
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dual << GIC_INTR_BIT(intr));
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1ul << GIC_INTR_BIT(intr),
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(unsigned long)dual << GIC_INTR_BIT(intr));
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}
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static inline void gic_map_to_pin(unsigned int intr, unsigned int pin)
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{
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gic_write(GIC_REG(SHARED, GIC_SH_INTR_MAP_TO_PIN_BASE) +
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GIC_SH_MAP_TO_PIN(intr), GIC_MAP_TO_PIN_MSK | pin);
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gic_write32(GIC_REG(SHARED, GIC_SH_INTR_MAP_TO_PIN_BASE) +
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GIC_SH_MAP_TO_PIN(intr), GIC_MAP_TO_PIN_MSK | pin);
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}
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static inline void gic_map_to_vpe(unsigned int intr, unsigned int vpe)
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@ -115,9 +141,9 @@ cycle_t gic_read_count(void)
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unsigned int hi, hi2, lo;
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do {
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hi = gic_read(GIC_REG(SHARED, GIC_SH_COUNTER_63_32));
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lo = gic_read(GIC_REG(SHARED, GIC_SH_COUNTER_31_00));
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hi2 = gic_read(GIC_REG(SHARED, GIC_SH_COUNTER_63_32));
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hi = gic_read32(GIC_REG(SHARED, GIC_SH_COUNTER_63_32));
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lo = gic_read32(GIC_REG(SHARED, GIC_SH_COUNTER_31_00));
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hi2 = gic_read32(GIC_REG(SHARED, GIC_SH_COUNTER_63_32));
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} while (hi2 != hi);
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return (((cycle_t) hi) << 32) + lo;
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@ -136,9 +162,9 @@ unsigned int gic_get_count_width(void)
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void gic_write_compare(cycle_t cnt)
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{
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gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI),
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gic_write32(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI),
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(int)(cnt >> 32));
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gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO),
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gic_write32(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO),
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(int)(cnt & 0xffffffff));
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}
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@ -148,10 +174,10 @@ void gic_write_cpu_compare(cycle_t cnt, int cpu)
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local_irq_save(flags);
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gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), cpu);
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gic_write(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_HI),
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gic_write32(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), cpu);
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gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_HI),
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(int)(cnt >> 32));
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gic_write(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_LO),
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gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_LO),
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(int)(cnt & 0xffffffff));
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local_irq_restore(flags);
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@ -161,8 +187,8 @@ cycle_t gic_read_compare(void)
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{
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unsigned int hi, lo;
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hi = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI));
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lo = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO));
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hi = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI));
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lo = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO));
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return (((cycle_t) hi) << 32) + lo;
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}
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@ -197,7 +223,7 @@ static bool gic_local_irq_is_routable(int intr)
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if (cpu_has_veic)
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return true;
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vpe_ctl = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_CTL));
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vpe_ctl = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_CTL));
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switch (intr) {
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case GIC_LOCAL_INT_TIMER:
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return vpe_ctl & GIC_VPE_CTL_TIMER_RTBL_MSK;
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@ -263,7 +289,7 @@ int gic_get_c0_fdc_int(void)
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static void gic_handle_shared_int(bool chained)
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{
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unsigned int i, intr, virq;
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unsigned int i, intr, virq, gic_reg_step = mips_cm_is64 ? 8 : 4;
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unsigned long *pcpu_mask;
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unsigned long pending_reg, intrmask_reg;
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DECLARE_BITMAP(pending, GIC_MAX_INTRS);
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@ -278,8 +304,8 @@ static void gic_handle_shared_int(bool chained)
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for (i = 0; i < BITS_TO_LONGS(gic_shared_intrs); i++) {
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pending[i] = gic_read(pending_reg);
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intrmask[i] = gic_read(intrmask_reg);
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pending_reg += 0x4;
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intrmask_reg += 0x4;
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pending_reg += gic_reg_step;
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intrmask_reg += gic_reg_step;
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}
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bitmap_and(pending, pending, intrmask, gic_shared_intrs);
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@ -429,8 +455,8 @@ static void gic_handle_local_int(bool chained)
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unsigned long pending, masked;
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unsigned int intr, virq;
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pending = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_PEND));
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masked = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_MASK));
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pending = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_PEND));
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masked = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_MASK));
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bitmap_and(&pending, &pending, &masked, GIC_NUM_LOCAL_INTRS);
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@ -453,14 +479,14 @@ static void gic_mask_local_irq(struct irq_data *d)
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{
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int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
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gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_RMASK), 1 << intr);
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gic_write32(GIC_REG(VPE_LOCAL, GIC_VPE_RMASK), 1 << intr);
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}
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static void gic_unmask_local_irq(struct irq_data *d)
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{
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int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
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gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_SMASK), 1 << intr);
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gic_write32(GIC_REG(VPE_LOCAL, GIC_VPE_SMASK), 1 << intr);
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}
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static struct irq_chip gic_local_irq_controller = {
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@ -478,7 +504,7 @@ static void gic_mask_local_irq_all_vpes(struct irq_data *d)
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spin_lock_irqsave(&gic_lock, flags);
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for (i = 0; i < gic_vpes; i++) {
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gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
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gic_write(GIC_REG(VPE_OTHER, GIC_VPE_RMASK), 1 << intr);
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gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_RMASK), 1 << intr);
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}
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spin_unlock_irqrestore(&gic_lock, flags);
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}
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@ -492,7 +518,7 @@ static void gic_unmask_local_irq_all_vpes(struct irq_data *d)
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spin_lock_irqsave(&gic_lock, flags);
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for (i = 0; i < gic_vpes; i++) {
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gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
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gic_write(GIC_REG(VPE_OTHER, GIC_VPE_SMASK), 1 << intr);
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gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_SMASK), 1 << intr);
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}
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spin_unlock_irqrestore(&gic_lock, flags);
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}
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@ -612,7 +638,7 @@ static void __init gic_basic_init(void)
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for (j = 0; j < GIC_NUM_LOCAL_INTRS; j++) {
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if (!gic_local_irq_is_routable(j))
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continue;
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gic_write(GIC_REG(VPE_OTHER, GIC_VPE_RMASK), 1 << j);
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gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_RMASK), 1 << j);
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}
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}
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}
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@ -657,27 +683,32 @@ static int gic_local_irq_domain_map(struct irq_domain *d, unsigned int virq,
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switch (intr) {
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case GIC_LOCAL_INT_WD:
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gic_write(GIC_REG(VPE_OTHER, GIC_VPE_WD_MAP), val);
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gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_WD_MAP), val);
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break;
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case GIC_LOCAL_INT_COMPARE:
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gic_write(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_MAP), val);
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gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_MAP),
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val);
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break;
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case GIC_LOCAL_INT_TIMER:
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/* CONFIG_MIPS_CMP workaround (see __gic_init) */
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val = GIC_MAP_TO_PIN_MSK | timer_cpu_pin;
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gic_write(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP), val);
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gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP),
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val);
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break;
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case GIC_LOCAL_INT_PERFCTR:
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gic_write(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP), val);
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gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP),
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val);
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break;
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case GIC_LOCAL_INT_SWINT0:
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gic_write(GIC_REG(VPE_OTHER, GIC_VPE_SWINT0_MAP), val);
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gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_SWINT0_MAP),
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val);
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break;
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case GIC_LOCAL_INT_SWINT1:
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gic_write(GIC_REG(VPE_OTHER, GIC_VPE_SWINT1_MAP), val);
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gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_SWINT1_MAP),
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val);
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break;
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case GIC_LOCAL_INT_FDC:
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gic_write(GIC_REG(VPE_OTHER, GIC_VPE_FDC_MAP), val);
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gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_FDC_MAP), val);
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break;
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default:
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pr_err("Invalid local IRQ %d\n", intr);
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@ -782,7 +813,7 @@ static void __init __gic_init(unsigned long gic_base_addr,
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*/
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if (IS_ENABLED(CONFIG_MIPS_CMP) &&
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gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER)) {
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timer_cpu_pin = gic_read(GIC_REG(VPE_LOCAL,
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timer_cpu_pin = gic_read32(GIC_REG(VPE_LOCAL,
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GIC_VPE_TIMER_MAP)) &
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GIC_MAP_MSK;
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irq_set_chained_handler(MIPS_CPU_IRQ_BASE +
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@ -45,8 +45,14 @@
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#define GIC_SH_REVISIONID_OFS 0x0020
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/* Convert an interrupt number to a byte offset/bit for multi-word registers */
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#define GIC_INTR_OFS(intr) (((intr) / 32) * 4)
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#define GIC_INTR_BIT(intr) ((intr) % 32)
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#define GIC_INTR_OFS(intr) ({ \
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unsigned bits = mips_cm_is64 ? 64 : 32; \
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unsigned reg_idx = (intr) / bits; \
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unsigned reg_width = bits / 8; \
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\
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reg_idx * reg_width; \
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})
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#define GIC_INTR_BIT(intr) ((intr) % (mips_cm_is64 ? 64 : 32))
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/* Polarity : Reset Value is always 0 */
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#define GIC_SH_SET_POLARITY_OFS 0x0100
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