mirror of https://gitee.com/openkylin/linux.git
IB/hfi1: Add static PCIe Gen3 CTLE tuning
Enhance the PCIe Gen3 recipe to support static CTLE tuning, and add a switch to choose between static and dynamic approaches. Make discrete chips default to static CTLE tuning. Reviewed-by: Tadeusz Struk <tadeusz.struk@intel.com> Signed-off-by: Dean Luick <dean.luick@intel.com> Signed-off-by: Dennis Dalessandro <dennis.dalessandro@intel.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
This commit is contained in:
Dean Luick
Doug Ledford
parent
8adf71fa14
commit
c3f8de0b33
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@ -679,6 +679,10 @@ static uint pcie_pset = UNSET_PSET;
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module_param(pcie_pset, uint, S_IRUGO);
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MODULE_PARM_DESC(pcie_pset, "PCIe Eq Pset value to use, range is 0-10");
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static uint pcie_ctle = 1; /* discrete on, integrated off */
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module_param(pcie_ctle, uint, S_IRUGO);
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MODULE_PARM_DESC(pcie_ctle, "PCIe static CTLE mode, bit 0 - discrete on/off, bit 1 - integrated on/off");
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/* equalization columns */
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#define PREC 0
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#define ATTN 1
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@ -716,6 +720,36 @@ static const u8 integrated_preliminary_eq[11][3] = {
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{ 0x00, 0x1e, 0x0a }, /* p10 */
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};
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static const u8 discrete_ctle_tunings[11][4] = {
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/* DC LF HF BW */
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{ 0x48, 0x0b, 0x04, 0x04 }, /* p0 */
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{ 0x60, 0x05, 0x0f, 0x0a }, /* p1 */
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{ 0x50, 0x09, 0x06, 0x06 }, /* p2 */
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{ 0x68, 0x05, 0x0f, 0x0a }, /* p3 */
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{ 0x80, 0x05, 0x0f, 0x0a }, /* p4 */
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{ 0x70, 0x05, 0x0f, 0x0a }, /* p5 */
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{ 0x68, 0x05, 0x0f, 0x0a }, /* p6 */
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{ 0x38, 0x0f, 0x00, 0x00 }, /* p7 */
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{ 0x48, 0x09, 0x06, 0x06 }, /* p8 */
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{ 0x60, 0x05, 0x0f, 0x0a }, /* p9 */
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{ 0x38, 0x0f, 0x00, 0x00 }, /* p10 */
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};
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static const u8 integrated_ctle_tunings[11][4] = {
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/* DC LF HF BW */
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{ 0x38, 0x0f, 0x00, 0x00 }, /* p0 */
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{ 0x38, 0x0f, 0x00, 0x00 }, /* p1 */
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{ 0x38, 0x0f, 0x00, 0x00 }, /* p2 */
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{ 0x38, 0x0f, 0x00, 0x00 }, /* p3 */
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{ 0x58, 0x0a, 0x05, 0x05 }, /* p4 */
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{ 0x48, 0x0a, 0x05, 0x05 }, /* p5 */
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{ 0x40, 0x0a, 0x05, 0x05 }, /* p6 */
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{ 0x38, 0x0f, 0x00, 0x00 }, /* p7 */
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{ 0x38, 0x0f, 0x00, 0x00 }, /* p8 */
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{ 0x38, 0x09, 0x06, 0x06 }, /* p9 */
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{ 0x38, 0x0e, 0x01, 0x01 }, /* p10 */
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};
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/* helper to format the value to write to hardware */
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#define eq_value(pre, curr, post) \
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((((u32)(pre)) << \
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@ -951,11 +985,14 @@ int do_pcie_gen3_transition(struct hfi1_devdata *dd)
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u32 status, err;
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int ret;
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int do_retry, retry_count = 0;
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int intnum = 0;
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uint default_pset;
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u16 target_vector, target_speed;
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u16 lnkctl2, vendor;
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u8 div;
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const u8 (*eq)[3];
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const u8 (*ctle_tunings)[4];
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uint static_ctle_mode;
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int return_error = 0;
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/* PCIe Gen3 is for the ASIC only */
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@ -1089,6 +1126,9 @@ int do_pcie_gen3_transition(struct hfi1_devdata *dd)
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div = 3;
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eq = discrete_preliminary_eq;
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default_pset = DEFAULT_DISCRETE_PSET;
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ctle_tunings = discrete_ctle_tunings;
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/* bit 0 - discrete on/off */
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static_ctle_mode = pcie_ctle & 0x1;
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} else {
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/* 400mV, FS=29, LF = 9 */
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fs = 29;
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@ -1096,6 +1136,9 @@ int do_pcie_gen3_transition(struct hfi1_devdata *dd)
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div = 1;
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eq = integrated_preliminary_eq;
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default_pset = DEFAULT_MCP_PSET;
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ctle_tunings = integrated_ctle_tunings;
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/* bit 1 - integrated on/off */
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static_ctle_mode = (pcie_ctle >> 1) & 0x1;
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}
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pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL101,
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(fs <<
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@ -1135,16 +1178,33 @@ int do_pcie_gen3_transition(struct hfi1_devdata *dd)
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* step 5c: Program gasket interrupts
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*/
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/* set the Rx Bit Rate to REFCLK ratio */
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write_gasket_interrupt(dd, 0, 0x0006, 0x0050);
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write_gasket_interrupt(dd, intnum++, 0x0006, 0x0050);
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/* disable pCal for PCIe Gen3 RX equalization */
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write_gasket_interrupt(dd, 1, 0x0026, 0x5b01);
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/* select adaptive or static CTLE */
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write_gasket_interrupt(dd, intnum++, 0x0026,
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0x5b01 | (static_ctle_mode << 3));
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/*
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* Enable iCal for PCIe Gen3 RX equalization, and set which
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* evaluation of RX_EQ_EVAL will launch the iCal procedure.
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*/
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write_gasket_interrupt(dd, 2, 0x0026, 0x5202);
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write_gasket_interrupt(dd, intnum++, 0x0026, 0x5202);
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if (static_ctle_mode) {
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/* apply static CTLE tunings */
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u8 pcie_dc, pcie_lf, pcie_hf, pcie_bw;
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pcie_dc = ctle_tunings[pcie_pset][0];
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pcie_lf = ctle_tunings[pcie_pset][1];
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pcie_hf = ctle_tunings[pcie_pset][2];
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pcie_bw = ctle_tunings[pcie_pset][3];
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write_gasket_interrupt(dd, intnum++, 0x0026, 0x0200 | pcie_dc);
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write_gasket_interrupt(dd, intnum++, 0x0026, 0x0100 | pcie_lf);
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write_gasket_interrupt(dd, intnum++, 0x0026, 0x0000 | pcie_hf);
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write_gasket_interrupt(dd, intnum++, 0x0026, 0x5500 | pcie_bw);
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}
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/* terminate list */
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write_gasket_interrupt(dd, 3, 0x0000, 0x0000);
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write_gasket_interrupt(dd, intnum++, 0x0000, 0x0000);
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/*
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* step 5d: program XMT margin
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