mirror of https://gitee.com/openkylin/linux.git
net/mlx5e: Remove unused max inline related code
Commit58d522912a
("net/mlx5e: Support TX packet copy into WQE") introduced the max inline WQE as an ethtool tunable. One commit later, that functionality was made dependent on BlueFlame. Commit6982ab6097
("net/mlx5e: Xmit, no write combining") removed BlueFlame support, and with it the max inline WQE. This patch cleans up the leftovers from the removed feature. Signed-off-by: Gal Pressman <galp@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
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@ -240,7 +240,6 @@ struct mlx5e_params {
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struct net_dim_cq_moder tx_cq_moderation;
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struct net_dim_cq_moder tx_cq_moderation;
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bool lro_en;
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bool lro_en;
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u32 lro_wqe_sz;
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u32 lro_wqe_sz;
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u16 tx_max_inline;
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u8 tx_min_inline_mode;
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u8 tx_min_inline_mode;
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u8 rss_hfunc;
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u8 rss_hfunc;
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u8 toeplitz_hash_key[40];
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u8 toeplitz_hash_key[40];
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@ -366,7 +365,6 @@ struct mlx5e_txqsq {
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void __iomem *uar_map;
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void __iomem *uar_map;
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struct netdev_queue *txq;
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struct netdev_queue *txq;
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u32 sqn;
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u32 sqn;
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u16 max_inline;
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u8 min_inline_mode;
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u8 min_inline_mode;
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u16 edge;
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u16 edge;
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struct device *pdev;
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struct device *pdev;
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@ -1017,7 +1015,6 @@ int mlx5e_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
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u16 rxq_index, u32 flow_id);
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u16 rxq_index, u32 flow_id);
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#endif
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#endif
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u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev);
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int mlx5e_create_tir(struct mlx5_core_dev *mdev,
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int mlx5e_create_tir(struct mlx5_core_dev *mdev,
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struct mlx5e_tir *tir, u32 *in, int inlen);
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struct mlx5e_tir *tir, u32 *in, int inlen);
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void mlx5e_destroy_tir(struct mlx5_core_dev *mdev,
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void mlx5e_destroy_tir(struct mlx5_core_dev *mdev,
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@ -1118,13 +1118,9 @@ static int mlx5e_get_tunable(struct net_device *dev,
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const struct ethtool_tunable *tuna,
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const struct ethtool_tunable *tuna,
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void *data)
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void *data)
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{
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{
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const struct mlx5e_priv *priv = netdev_priv(dev);
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int err;
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int err = 0;
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switch (tuna->id) {
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switch (tuna->id) {
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case ETHTOOL_TX_COPYBREAK:
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*(u32 *)data = priv->channels.params.tx_max_inline;
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break;
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case ETHTOOL_PFC_PREVENTION_TOUT:
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case ETHTOOL_PFC_PREVENTION_TOUT:
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err = mlx5e_get_pfc_prevention_tout(dev, data);
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err = mlx5e_get_pfc_prevention_tout(dev, data);
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break;
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break;
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@ -1141,35 +1137,11 @@ static int mlx5e_set_tunable(struct net_device *dev,
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const void *data)
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const void *data)
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{
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{
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struct mlx5e_priv *priv = netdev_priv(dev);
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struct mlx5e_priv *priv = netdev_priv(dev);
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struct mlx5_core_dev *mdev = priv->mdev;
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int err;
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struct mlx5e_channels new_channels = {};
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int err = 0;
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u32 val;
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mutex_lock(&priv->state_lock);
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mutex_lock(&priv->state_lock);
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switch (tuna->id) {
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switch (tuna->id) {
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case ETHTOOL_TX_COPYBREAK:
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val = *(u32 *)data;
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if (val > mlx5e_get_max_inline_cap(mdev)) {
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err = -EINVAL;
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break;
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}
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new_channels.params = priv->channels.params;
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new_channels.params.tx_max_inline = val;
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if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
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priv->channels.params = new_channels.params;
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break;
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}
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err = mlx5e_open_channels(priv, &new_channels);
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if (err)
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break;
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mlx5e_switch_priv_channels(priv, &new_channels, NULL);
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break;
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case ETHTOOL_PFC_PREVENTION_TOUT:
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case ETHTOOL_PFC_PREVENTION_TOUT:
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err = mlx5e_set_pfc_prevention_tout(dev, *(u16 *)data);
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err = mlx5e_set_pfc_prevention_tout(dev, *(u16 *)data);
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break;
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break;
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@ -993,7 +993,6 @@ static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
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sq->channel = c;
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sq->channel = c;
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sq->txq_ix = txq_ix;
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sq->txq_ix = txq_ix;
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sq->uar_map = mdev->mlx5e_res.bfreg.map;
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sq->uar_map = mdev->mlx5e_res.bfreg.map;
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sq->max_inline = params->tx_max_inline;
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sq->min_inline_mode = params->tx_min_inline_mode;
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sq->min_inline_mode = params->tx_min_inline_mode;
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if (MLX5_IPSEC_DEV(c->priv->mdev))
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if (MLX5_IPSEC_DEV(c->priv->mdev))
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set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
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set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
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@ -3882,15 +3881,6 @@ static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
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return 0;
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return 0;
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}
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}
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u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
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{
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int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
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return bf_buf_size -
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sizeof(struct mlx5e_tx_wqe) +
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2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
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}
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void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
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void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
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int num_channels)
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int num_channels)
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{
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{
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@ -4052,7 +4042,6 @@ void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
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mlx5e_set_tx_cq_mode_params(params, cq_period_mode);
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mlx5e_set_tx_cq_mode_params(params, cq_period_mode);
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/* TX inline */
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/* TX inline */
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params->tx_max_inline = mlx5e_get_max_inline_cap(mdev);
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params->tx_min_inline_mode = mlx5e_params_calculate_tx_min_inline(mdev);
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params->tx_min_inline_mode = mlx5e_params_calculate_tx_min_inline(mdev);
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/* RSS */
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/* RSS */
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@ -884,7 +884,6 @@ static void mlx5e_build_rep_params(struct mlx5_core_dev *mdev,
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params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
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params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
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mlx5e_set_rx_cq_mode_params(params, cq_period_mode);
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mlx5e_set_rx_cq_mode_params(params, cq_period_mode);
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params->tx_max_inline = mlx5e_get_max_inline_cap(mdev);
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params->num_tc = 1;
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params->num_tc = 1;
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params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
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params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
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