mirror of https://gitee.com/openkylin/linux.git
staging: xgifb: replace DelayUS() with udelay()
Replace DelayUS() with udelay(). Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Aaro Koskinen
Greg Kroah-Hartman
parent
c83c620afa
commit
c45715bb95
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@ -39,11 +39,6 @@ static unsigned short XGINew_DDRDRAM_TYPE20[12][5] = {
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static int XGINew_RAMType;
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static void DelayUS(unsigned long MicroSeconds)
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{
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udelay(MicroSeconds);
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}
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static unsigned char XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension,
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struct vb_device_info *pVBInfo)
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{
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@ -75,7 +70,7 @@ static unsigned char XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceE
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return data;
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} else if (HwDeviceExtension->jChipType == XG21) {
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XGINew_SetRegAND(pVBInfo->P3d4, 0xB4, ~0x02); /* Independent GPIO control */
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DelayUS(800);
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udelay(800);
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XGINew_SetRegOR(pVBInfo->P3d4, 0x4A, 0x80); /* Enable GPIOH read */
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temp = XGINew_GetReg1(pVBInfo->P3d4, 0x48); /* GPIOF 0:DVI 1:DVO */
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/* HOTPLUG_SUPPORT */
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@ -112,14 +107,14 @@ static void XGINew_DDR1x_MRS_340(unsigned long P3c4, struct vb_device_info *pVBI
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XGINew_SetReg1(P3c4, 0x16, 0x80);
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}
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DelayUS(60);
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udelay(60);
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XGINew_SetReg1(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
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XGINew_SetReg1(P3c4, 0x19, 0x01);
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XGINew_SetReg1(P3c4, 0x16, pVBInfo->SR16[0]);
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XGINew_SetReg1(P3c4, 0x16, pVBInfo->SR16[1]);
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mdelay(1);
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XGINew_SetReg1(P3c4, 0x1B, 0x03);
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DelayUS(500);
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udelay(500);
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XGINew_SetReg1(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
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XGINew_SetReg1(P3c4, 0x19, 0x00);
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XGINew_SetReg1(P3c4, 0x16, pVBInfo->SR16[2]);
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@ -164,65 +159,65 @@ static void XGINew_DDRII_Bootup_XG27(
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/* XGINew_SetReg1(P3d4, 0x97, 0x11); *//* CR97 */
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XGINew_SetReg1(P3d4, 0x97, *pVBInfo->pXGINew_CR97); /* CR97 */
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DelayUS(200);
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udelay(200);
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XGINew_SetReg1(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS2 */
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XGINew_SetReg1(P3c4, 0x19, 0x80); /* Set SR19 */
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XGINew_SetReg1(P3c4, 0x16, 0x20); /* Set SR16 */
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DelayUS(15);
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udelay(15);
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XGINew_SetReg1(P3c4, 0x16, 0xA0); /* Set SR16 */
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DelayUS(15);
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udelay(15);
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XGINew_SetReg1(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS3 */
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XGINew_SetReg1(P3c4, 0x19, 0xC0); /* Set SR19 */
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XGINew_SetReg1(P3c4, 0x16, 0x20); /* Set SR16 */
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DelayUS(15);
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udelay(15);
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XGINew_SetReg1(P3c4, 0x16, 0xA0); /* Set SR16 */
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DelayUS(15);
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udelay(15);
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XGINew_SetReg1(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS1 */
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XGINew_SetReg1(P3c4, 0x19, 0x40); /* Set SR19 */
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XGINew_SetReg1(P3c4, 0x16, 0x20); /* Set SR16 */
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DelayUS(30);
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udelay(30);
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XGINew_SetReg1(P3c4, 0x16, 0xA0); /* Set SR16 */
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DelayUS(15);
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udelay(15);
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XGINew_SetReg1(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Enable */
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XGINew_SetReg1(P3c4, 0x19, 0x0A); /* Set SR19 */
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XGINew_SetReg1(P3c4, 0x16, 0x00); /* Set SR16 */
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DelayUS(30);
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udelay(30);
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XGINew_SetReg1(P3c4, 0x16, 0x00); /* Set SR16 */
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XGINew_SetReg1(P3c4, 0x16, 0x80); /* Set SR16 */
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/* DelayUS(15); */
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/* udelay(15); */
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XGINew_SetReg1(P3c4, 0x1B, 0x04); /* Set SR1B */
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DelayUS(60);
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udelay(60);
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XGINew_SetReg1(P3c4, 0x1B, 0x00); /* Set SR1B */
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XGINew_SetReg1(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Reset */
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XGINew_SetReg1(P3c4, 0x19, 0x08); /* Set SR19 */
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XGINew_SetReg1(P3c4, 0x16, 0x00); /* Set SR16 */
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DelayUS(30);
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udelay(30);
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XGINew_SetReg1(P3c4, 0x16, 0x83); /* Set SR16 */
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DelayUS(15);
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udelay(15);
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XGINew_SetReg1(P3c4, 0x18, 0x80); /* Set SR18 */ /* MRS, ODT */
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XGINew_SetReg1(P3c4, 0x19, 0x46); /* Set SR19 */
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XGINew_SetReg1(P3c4, 0x16, 0x20); /* Set SR16 */
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DelayUS(30);
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udelay(30);
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XGINew_SetReg1(P3c4, 0x16, 0xA0); /* Set SR16 */
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DelayUS(15);
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udelay(15);
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XGINew_SetReg1(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS */
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XGINew_SetReg1(P3c4, 0x19, 0x40); /* Set SR19 */
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XGINew_SetReg1(P3c4, 0x16, 0x20); /* Set SR16 */
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DelayUS(30);
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udelay(30);
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XGINew_SetReg1(P3c4, 0x16, 0xA0); /* Set SR16 */
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DelayUS(15);
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udelay(15);
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XGINew_SetReg1(P3c4, 0x1B, 0x04); /* Set SR1B refresh control 000:close; 010:open */
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DelayUS(200);
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udelay(200);
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}
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@ -236,7 +231,7 @@ static void XGINew_DDR2_MRS_XG20(struct xgi_hw_device_info *HwDeviceExtension,
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XGINew_SetReg1(P3d4, 0x97, 0x11); /* CR97 */
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DelayUS(200);
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udelay(200);
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XGINew_SetReg1(P3c4, 0x18, 0x00); /* EMRS2 */
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XGINew_SetReg1(P3c4, 0x19, 0x80);
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XGINew_SetReg1(P3c4, 0x16, 0x05);
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@ -258,11 +253,11 @@ static void XGINew_DDR2_MRS_XG20(struct xgi_hw_device_info *HwDeviceExtension,
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XGINew_SetReg1(P3c4, 0x16, 0x05);
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XGINew_SetReg1(P3c4, 0x16, 0x85);
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DelayUS(15);
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udelay(15);
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XGINew_SetReg1(P3c4, 0x1B, 0x04); /* SR1B */
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DelayUS(30);
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udelay(30);
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XGINew_SetReg1(P3c4, 0x1B, 0x00); /* SR1B */
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DelayUS(100);
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udelay(100);
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/* XGINew_SetReg1(P3c4 ,0x18, 0x52); */ /* MRS2 */
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XGINew_SetReg1(P3c4, 0x18, 0x42); /* MRS1 */
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@ -270,7 +265,7 @@ static void XGINew_DDR2_MRS_XG20(struct xgi_hw_device_info *HwDeviceExtension,
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XGINew_SetReg1(P3c4, 0x16, 0x05);
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XGINew_SetReg1(P3c4, 0x16, 0x85);
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DelayUS(200);
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udelay(200);
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}
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static void XGINew_DDR1x_MRS_XG20(unsigned long P3c4, struct vb_device_info *pVBInfo)
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@ -280,13 +275,13 @@ static void XGINew_DDR1x_MRS_XG20(unsigned long P3c4, struct vb_device_info *pVB
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XGINew_SetReg1(P3c4, 0x19, 0x40);
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XGINew_SetReg1(P3c4, 0x16, 0x00);
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XGINew_SetReg1(P3c4, 0x16, 0x80);
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DelayUS(60);
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udelay(60);
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XGINew_SetReg1(P3c4, 0x18, 0x00);
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XGINew_SetReg1(P3c4, 0x19, 0x40);
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XGINew_SetReg1(P3c4, 0x16, 0x00);
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XGINew_SetReg1(P3c4, 0x16, 0x80);
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DelayUS(60);
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udelay(60);
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XGINew_SetReg1(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
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/* XGINew_SetReg1(P3c4, 0x18, 0x31); */
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XGINew_SetReg1(P3c4, 0x19, 0x01);
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@ -294,7 +289,7 @@ static void XGINew_DDR1x_MRS_XG20(unsigned long P3c4, struct vb_device_info *pVB
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XGINew_SetReg1(P3c4, 0x16, 0x83);
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mdelay(1);
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XGINew_SetReg1(P3c4, 0x1B, 0x03);
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DelayUS(500);
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udelay(500);
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/* XGINew_SetReg1(P3c4, 0x18, 0x31); */
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XGINew_SetReg1(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
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XGINew_SetReg1(P3c4, 0x19, 0x00);
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@ -522,7 +517,7 @@ static void XGINew_SetDRAMSizingType(int index,
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data = DRAMTYPE_TABLE[index][4];
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XGINew_SetRegANDOR(pVBInfo->P3c4, 0x13, 0x80, data);
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DelayUS(15);
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udelay(15);
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/* should delay 50 ns */
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}
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@ -597,7 +592,7 @@ static unsigned short XGINew_SetDRAMSize20Reg(int index,
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/* [2004/03/25] Vicent, Fix DRAM Sizing Error */
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XGINew_SetReg1(pVBInfo->P3c4, 0x14, (XGINew_GetReg1(pVBInfo->P3c4, 0x14) & 0x0F) | (data & 0xF0));
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DelayUS(15);
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udelay(15);
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/* data |= XGINew_ChannelAB << 2; */
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/* data |= (XGINew_DataBusWidth / 64) << 1; */
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@ -622,7 +617,7 @@ static int XGINew_ReadWriteRest(unsigned short StopAddr,
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*((unsigned long *) (pVBInfo->FBAddr + Position)) = Position;
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}
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DelayUS(500); /* [Vicent] 2004/04/16. Fix #1759 Memory Size error in Multi-Adapter. */
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udelay(500); /* [Vicent] 2004/04/16. Fix #1759 Memory Size error in Multi-Adapter. */
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Position = 0;
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@ -672,7 +667,7 @@ static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
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XGINew_DataBusWidth = 32; /* 32 bits */
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XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0xB1); /* 22bit + 2 rank + 32bit */
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XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x52);
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DelayUS(15);
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udelay(15);
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if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
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return;
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@ -680,7 +675,7 @@ static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
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if ((HwDeviceExtension->ulVideoMemorySize - 1) > 0x800000) {
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XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x31); /* 22bit + 1 rank + 32bit */
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XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x42);
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DelayUS(15);
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udelay(15);
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if (XGINew_ReadWriteRest(23, 23, pVBInfo) == 1)
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return;
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@ -691,13 +686,13 @@ static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
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XGINew_DataBusWidth = 16; /* 16 bits */
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XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0xB1); /* 22bit + 2 rank + 16bit */
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XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x41);
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DelayUS(15);
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udelay(15);
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if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
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return;
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else
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XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x31);
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DelayUS(15);
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udelay(15);
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}
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} else { /* Dual_16_8 */
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@ -706,7 +701,7 @@ static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
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XGINew_DataBusWidth = 16; /* 16 bits */
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XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0xB1); /* (0x31:12x8x2) 22bit + 2 rank */
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XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x41); /* 0x41:16Mx16 bit*/
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DelayUS(15);
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udelay(15);
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if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
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return;
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@ -714,7 +709,7 @@ static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
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if ((HwDeviceExtension->ulVideoMemorySize - 1) > 0x400000) {
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XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x31); /* (0x31:12x8x2) 22bit + 1 rank */
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XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x31); /* 0x31:8Mx16 bit*/
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DelayUS(15);
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udelay(15);
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if (XGINew_ReadWriteRest(22, 22, pVBInfo) == 1)
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return;
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@ -725,13 +720,13 @@ static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
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XGINew_DataBusWidth = 8; /* 8 bits */
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XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0xB1); /* (0x31:12x8x2) 22bit + 2 rank */
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XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x30); /* 0x30:8Mx8 bit*/
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DelayUS(15);
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udelay(15);
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if (XGINew_ReadWriteRest(22, 21, pVBInfo) == 1)
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return;
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else
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XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x31); /* (0x31:12x8x2) 22bit + 1 rank */
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DelayUS(15);
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udelay(15);
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}
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}
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break;
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