mirror of https://gitee.com/openkylin/linux.git
mvebu dt64 for 5.15 (part 1)
- DTS updates for Marvell Armada CN913x platforms
+ Add support for Armada CN913x Development Board topology "B"
+ Add support for Armada CN913x Reference Design boards (CRB)
+ Fixes the NAND partitioning scheme in DTS eliminating gap between
consecutive partitions
+ Fix 10Gb ports PHY mode names
- Extend PCIe MEM space on Armada 37xx: useful for some combination
of PCIe cards where the initial 16MB was not enough
-----BEGIN PGP SIGNATURE-----
iF0EABECAB0WIQQYqXDMF3cvSLY+g9cLBhiOFHI71QUCYRvo7gAKCRALBhiOFHI7
1bmWAJ9PI7D21ZLkSrwwuiwh/e1KpTsYcgCeODbCcOQis4VTK2vU6r+plVXLLzc=
=Mae4
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmEdAWMACgkQmmx57+YA
GNleEQ/+LYx9PbjfMFMNAOyEDQa5ypWIuL2DqHbHFZw7UOGBcUeiDlge3kLFvYtB
JeVOS54Lk85JhxgKBLeIRZ8Nhb+JNKPXbSIz4nqEb7CEvimgRMeePxSfSwyVEi3x
6xqrkXjii9clbbf1UGVTR3XPQITl7M9l7F4yj5kGft7Qt5lHbZPdn733EhnP81cG
HgrcpEviD7Y8jg+nySesenunnnWo82ZsJ/0igCYgRL+cMMDPLXWuPS86Ws0xEuyj
TEh6HR1IlzYr1V9EB7Ra0dFIms4/wDSAwzHItFw08QJs0sirqAnO0vOUETaLH6AX
xUJgvUB+hzmJKlXEwimQYTK14o2Dd8BDgko8FHK/fPE61Is551UmTjxLM0m80baL
4te8/f5h3Lo5oWfbcew8CjUJHRbOc+ZIlmQ8QztrSn6oM4JvFOjSn46aBWkagSfC
0FoeSoCmIhZoPnIOmgdlW+g60qdTeXqbqPUKsS4YTj4ZZYTULWO4I3DlLGNI303p
Z/uv0mLaHXy6TeUWs2519pF1QQ7GDKgATDXflpz9rgp2Veochd8dcDKXGGKyaT1J
P6CWvwJDauo4zMi9M+eQsqn6Vz30jiCndJOEQiMgLQNvCJpq9L1SZqCuQ1iVCPKK
gZfCT6kMdJHrMUGzYaHRc/LaaakWv+UYPtU6r333GtYRdKnZz9w=
=VEgZ
-----END PGP SIGNATURE-----
Merge tag 'mvebu-dt64-5.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into arm/dt
mvebu dt64 for 5.15 (part 1)
- DTS updates for Marvell Armada CN913x platforms
+ Add support for Armada CN913x Development Board topology "B"
+ Add support for Armada CN913x Reference Design boards (CRB)
+ Fixes the NAND partitioning scheme in DTS eliminating gap between
consecutive partitions
+ Fix 10Gb ports PHY mode names
- Extend PCIe MEM space on Armada 37xx: useful for some combination
of PCIe cards where the initial 16MB was not enough
* tag 'mvebu-dt64-5.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu:
arm64: dts: marvell: armada-37xx: Extend PCIe MEM space
arch/arm64: dts: change 10gbase-kr to 10gbase-r in Armada
arm64: dts: add support for Marvell cn9130-crb platform
dts: marvell: Enable 10G interfaces on 9130-DB and 9131-DB boards
arm64: dts: cn913x: add device trees for topology B boards
Link: https://lore.kernel.org/r/878s10ypxe.fsf@BL-laptop
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
c4d3928250
|
|
@ -16,5 +16,10 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin-singleshot.dtb
|
|||
dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-puzzle-m801.dtb
|
||||
dtb-$(CONFIG_ARCH_MVEBU) += armada-8080-db.dtb
|
||||
dtb-$(CONFIG_ARCH_MVEBU) += cn9130-db.dtb
|
||||
dtb-$(CONFIG_ARCH_MVEBU) += cn9130-db-B.dtb
|
||||
dtb-$(CONFIG_ARCH_MVEBU) += cn9131-db.dtb
|
||||
dtb-$(CONFIG_ARCH_MVEBU) += cn9131-db-B.dtb
|
||||
dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb
|
||||
dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb
|
||||
dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb
|
||||
dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb
|
||||
|
|
|
|||
|
|
@ -132,6 +132,23 @@ &pcie0 {
|
|||
pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
|
||||
status = "okay";
|
||||
reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
|
||||
/*
|
||||
* U-Boot port for Turris Mox has a bug which always expects that "ranges" DT property
|
||||
* contains exactly 2 ranges with 3 (child) address cells, 2 (parent) address cells and
|
||||
* 2 size cells and also expects that the second range starts at 16 MB offset. If these
|
||||
* conditions are not met then U-Boot crashes during loading kernel DTB file. PCIe address
|
||||
* space is 128 MB long, so the best split between MEM and IO is to use fixed 16 MB window
|
||||
* for IO and the rest 112 MB (64+32+16) for MEM, despite that maximal IO size is just 64 kB.
|
||||
* This bug is not present in U-Boot ports for other Armada 3700 devices and is fixed in
|
||||
* U-Boot version 2021.07. See relevant U-Boot commits (the last one contains fix):
|
||||
* https://source.denx.de/u-boot/u-boot/-/commit/cb2ddb291ee6fcbddd6d8f4ff49089dfe580f5d7
|
||||
* https://source.denx.de/u-boot/u-boot/-/commit/c64ac3b3185aeb3846297ad7391fc6df8ecd73bf
|
||||
* https://source.denx.de/u-boot/u-boot/-/commit/4a82fca8e330157081fc132a591ebd99ba02ee33
|
||||
*/
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x81000000 0 0xe8000000 0 0xe8000000 0 0x01000000 /* Port 0 IO */
|
||||
0x82000000 0 0xe9000000 0 0xe9000000 0 0x07000000>; /* Port 0 MEM */
|
||||
|
||||
/* enabled by U-Boot if PCIe module is present */
|
||||
status = "disabled";
|
||||
|
|
|
|||
|
|
@ -489,8 +489,15 @@ pcie0: pcie@d0070000 {
|
|||
#interrupt-cells = <1>;
|
||||
msi-parent = <&pcie0>;
|
||||
msi-controller;
|
||||
ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000 /* Port 0 MEM */
|
||||
0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>; /* Port 0 IO*/
|
||||
/*
|
||||
* The 128 MiB address range [0xe8000000-0xf0000000] is
|
||||
* dedicated for PCIe and can be assigned to 8 windows
|
||||
* with size a power of two. Use one 64 KiB window for
|
||||
* IO at the end and the remaining seven windows
|
||||
* (totaling 127 MiB) for MEM.
|
||||
*/
|
||||
ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x07f00000 /* Port 0 MEM */
|
||||
0x81000000 0 0xefff0000 0 0xefff0000 0 0x00010000>; /* Port 0 IO */
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc 0>,
|
||||
<0 0 0 2 &pcie_intc 1>,
|
||||
|
|
|
|||
|
|
@ -282,7 +282,7 @@ &cp0_ethernet {
|
|||
&cp0_eth0 {
|
||||
status = "okay";
|
||||
/* Network PHY */
|
||||
phy-mode = "10gbase-kr";
|
||||
phy-mode = "10gbase-r";
|
||||
/* Generic PHY, providing serdes lanes */
|
||||
phys = <&cp0_comphy2 0>;
|
||||
|
||||
|
|
|
|||
|
|
@ -195,7 +195,7 @@ &cp0_ethernet {
|
|||
|
||||
&cp0_eth0 {
|
||||
status = "okay";
|
||||
phy-mode = "10gbase-kr";
|
||||
phy-mode = "10gbase-r";
|
||||
|
||||
fixed-link {
|
||||
speed = <10000>;
|
||||
|
|
@ -348,7 +348,7 @@ &cp1_ethernet {
|
|||
|
||||
&cp1_eth0 {
|
||||
status = "okay";
|
||||
phy-mode = "10gbase-kr";
|
||||
phy-mode = "10gbase-r";
|
||||
|
||||
fixed-link {
|
||||
speed = <10000>;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,38 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2020 Marvell International Ltd.
|
||||
*/
|
||||
|
||||
#include "cn9130-crb.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada CN9130-CRB-A";
|
||||
};
|
||||
|
||||
&cp0_pcie0 {
|
||||
status = "okay";
|
||||
num-lanes = <4>;
|
||||
num-viewport = <8>;
|
||||
/* Generic PHY, providing serdes lanes */
|
||||
phys = <&cp0_comphy0 0
|
||||
&cp0_comphy1 0
|
||||
&cp0_comphy2 0
|
||||
&cp0_comphy3 0>;
|
||||
iommu-map =
|
||||
<0x0 &smmu 0x480 0x20>,
|
||||
<0x100 &smmu 0x4a0 0x20>,
|
||||
<0x200 &smmu 0x4c0 0x20>;
|
||||
iommu-map-mask = <0x031f>;
|
||||
};
|
||||
|
||||
&cp0_usb3_0 {
|
||||
status = "okay";
|
||||
usb-phy = <&cp0_usb3_0_phy0>;
|
||||
phy-names = "usb";
|
||||
};
|
||||
|
||||
&cp0_usb3_1 {
|
||||
status = "okay";
|
||||
usb-phy = <&cp0_usb3_0_phy1>;
|
||||
phy-names = "usb";
|
||||
};
|
||||
|
|
@ -0,0 +1,46 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2020 Marvell International Ltd.
|
||||
*/
|
||||
|
||||
#include "cn9130-crb.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada CN9130-CRB-B";
|
||||
};
|
||||
|
||||
&cp0_pcie0 {
|
||||
status = "okay";
|
||||
num-lanes = <1>;
|
||||
num-viewport = <8>;
|
||||
/* Generic PHY, providing serdes lanes */
|
||||
phys = <&cp0_comphy0 0>;
|
||||
iommu-map =
|
||||
<0x0 &smmu 0x480 0x20>,
|
||||
<0x100 &smmu 0x4a0 0x20>,
|
||||
<0x200 &smmu 0x4c0 0x20>;
|
||||
iommu-map-mask = <0x031f>;
|
||||
};
|
||||
|
||||
&cp0_sata0 {
|
||||
status = "okay";
|
||||
sata-port@0 {
|
||||
status = "okay";
|
||||
/* Generic PHY, providing serdes lanes */
|
||||
phys = <&cp0_comphy2 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_usb3_0 {
|
||||
status = "okay";
|
||||
usb-phy = <&cp0_usb3_0_phy0>;
|
||||
phy-names = "usb";
|
||||
phys = <&cp0_comphy1 0>;
|
||||
};
|
||||
|
||||
&cp0_usb3_1 {
|
||||
status = "okay";
|
||||
usb-phy = <&cp0_usb3_0_phy1>;
|
||||
phy-names = "usb";
|
||||
phys = <&cp0_comphy3 1>;
|
||||
};
|
||||
|
|
@ -0,0 +1,222 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2020 Marvell International Ltd.
|
||||
*/
|
||||
|
||||
#include "cn9130.dtsi" /* include SoC device tree */
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
aliases {
|
||||
i2c0 = &cp0_i2c0;
|
||||
ethernet0 = &cp0_eth0;
|
||||
ethernet1 = &cp0_eth1;
|
||||
ethernet2 = &cp0_eth2;
|
||||
};
|
||||
|
||||
memory@00000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x80000000>;
|
||||
};
|
||||
|
||||
ap0_reg_mmc_vccq: ap0_mmc_vccq@0 {
|
||||
compatible = "regulator-gpio";
|
||||
regulator-name = "ap0_mmc_vccq";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpios = <&expander0 5 GPIO_ACTIVE_HIGH>;
|
||||
states = <1800000 0x1
|
||||
3300000 0x0>;
|
||||
};
|
||||
|
||||
cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "cp0-xhci1-vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&expander0 8 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
cp0_usb3_0_phy0: cp0_usb3_phy0 {
|
||||
compatible = "usb-nop-xceiv";
|
||||
};
|
||||
|
||||
cp0_usb3_0_phy1: cp0_usb3_phy1 {
|
||||
compatible = "usb-nop-xceiv";
|
||||
vcc-supply = <&cp0_reg_usb3_vbus1>;
|
||||
};
|
||||
|
||||
cp0_reg_sd_vccq: cp0_sd_vccq@0 {
|
||||
compatible = "regulator-gpio";
|
||||
regulator-name = "cp0_sd_vccq";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpios = <&cp0_gpio2 18 GPIO_ACTIVE_HIGH>;
|
||||
states = <1800000 0x1
|
||||
3300000 0x0>;
|
||||
};
|
||||
|
||||
cp0_reg_sd_vcc: cp0_sd_vcc@0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "cp0_sd_vcc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* on-board eMMC U6 */
|
||||
&ap_sdhci0 {
|
||||
pinctrl-names = "default";
|
||||
bus-width = <8>;
|
||||
status = "okay";
|
||||
mmc-ddr-1_8v;
|
||||
vqmmc-supply = <&ap0_reg_mmc_vccq>;
|
||||
};
|
||||
|
||||
&cp0_syscon0 {
|
||||
cp0_pinctrl: pinctrl {
|
||||
compatible = "marvell,cp115-standalone-pinctrl";
|
||||
|
||||
cp0_i2c0_pins: cp0-i2c-pins-0 {
|
||||
marvell,pins = "mpp37", "mpp38";
|
||||
marvell,function = "i2c0";
|
||||
};
|
||||
cp0_i2c1_pins: cp0-i2c-pins-1 {
|
||||
marvell,pins = "mpp35", "mpp36";
|
||||
marvell,function = "i2c1";
|
||||
};
|
||||
cp0_sdhci_cd_pins_crb: cp0-sdhci-cd-pins-crb {
|
||||
marvell,pins = "mpp55";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
cp0_sdhci_pins: cp0-sdhi-pins-0 {
|
||||
marvell,pins = "mpp56", "mpp57", "mpp58",
|
||||
"mpp59", "mpp60", "mpp61";
|
||||
marvell,function = "sdio";
|
||||
};
|
||||
cp0_spi0_pins: cp0-spi-pins-0 {
|
||||
marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
|
||||
marvell,function = "spi1";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_i2c0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp0_i2c0_pins>;
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
expander0: mcp23x17@20 {
|
||||
compatible = "microchip,mcp23017";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x20>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_i2c1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp0_i2c1_pins>;
|
||||
clock-frequency = <100000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
||||
&cp0_sdhci0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp0_sdhci_pins
|
||||
&cp0_sdhci_cd_pins_crb>;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&cp0_gpio2 23 GPIO_ACTIVE_HIGH>;
|
||||
vqmmc-supply = <&cp0_reg_sd_vccq>;
|
||||
vmmc-supply = <&cp0_reg_sd_vcc>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_spi1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp0_spi0_pins>;
|
||||
reg = <0x700680 0x50>, /* control */
|
||||
<0x2000000 0x1000000>; /* CS0 */
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0x0>;
|
||||
/* On-board MUX does not allow higher frequencies */
|
||||
spi-max-frequency = <40000000>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "U-Boot";
|
||||
reg = <0x0 0x200000>;
|
||||
};
|
||||
|
||||
partition@400000 {
|
||||
label = "Filesystem";
|
||||
reg = <0x200000 0xe00000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_mdio {
|
||||
status = "okay";
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_xmdio {
|
||||
status = "okay";
|
||||
nbaset_phy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_ethernet {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_eth0 {
|
||||
/* This port is connected to 88E6393X switch */
|
||||
status = "okay";
|
||||
phy-mode = "10gbase-r";
|
||||
managed = "in-band-status";
|
||||
phys = <&cp0_comphy4 0>;
|
||||
};
|
||||
|
||||
&cp0_eth1 {
|
||||
status = "okay";
|
||||
phy = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
|
||||
&cp0_eth2 {
|
||||
/* This port uses "2500base-t" phy-mode */
|
||||
status = "disabled";
|
||||
phy = <&nbaset_phy0>;
|
||||
phys = <&cp0_comphy5 2>;
|
||||
};
|
||||
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (C) 2020 Marvell International Ltd.
|
||||
*
|
||||
* Device tree for the CN9130-DB board (setup "B").
|
||||
*/
|
||||
|
||||
#include "cn9130-db.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada CN9130-DB setup B";
|
||||
};
|
||||
|
||||
/* Setup B has NAND flash as a boot device, while regular setup uses SPI flash.
|
||||
* Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
|
||||
* simultaneously. When NAND controller is enabled, SPI1 should be disabled.
|
||||
*/
|
||||
|
||||
&cp0_nand_controller {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
@ -5,409 +5,18 @@
|
|||
* Device tree for the CN9130-DB board.
|
||||
*/
|
||||
|
||||
#include "cn9130.dtsi"
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include "cn9130-db.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada CN9130-DB";
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
model = "Marvell Armada CN9130-DB setup A";
|
||||
};
|
||||
|
||||
aliases {
|
||||
gpio1 = &cp0_gpio1;
|
||||
gpio2 = &cp0_gpio2;
|
||||
i2c0 = &cp0_i2c0;
|
||||
ethernet0 = &cp0_eth0;
|
||||
ethernet1 = &cp0_eth1;
|
||||
ethernet2 = &cp0_eth2;
|
||||
spi1 = &cp0_spi0;
|
||||
spi2 = &cp0_spi1;
|
||||
};
|
||||
|
||||
memory@00000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x80000000>;
|
||||
};
|
||||
|
||||
ap0_reg_sd_vccq: ap0_sd_vccq@0 {
|
||||
compatible = "regulator-gpio";
|
||||
regulator-name = "ap0_sd_vccq";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpios = <&expander0 8 GPIO_ACTIVE_HIGH>;
|
||||
states = <1800000 0x1 3300000 0x0>;
|
||||
};
|
||||
|
||||
cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "cp0-xhci0-vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
cp0_usb3_0_phy0: cp0_usb3_phy@0 {
|
||||
compatible = "usb-nop-xceiv";
|
||||
vcc-supply = <&cp0_reg_usb3_vbus0>;
|
||||
};
|
||||
|
||||
cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "cp0-xhci1-vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
cp0_usb3_0_phy1: cp0_usb3_phy@1 {
|
||||
compatible = "usb-nop-xceiv";
|
||||
vcc-supply = <&cp0_reg_usb3_vbus1>;
|
||||
};
|
||||
|
||||
cp0_reg_sd_vccq: cp0_sd_vccq@0 {
|
||||
compatible = "regulator-gpio";
|
||||
regulator-name = "cp0_sd_vccq";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpios = <&expander0 15 GPIO_ACTIVE_HIGH>;
|
||||
states = <1800000 0x1
|
||||
3300000 0x0>;
|
||||
};
|
||||
|
||||
cp0_reg_sd_vcc: cp0_sd_vcc@0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "cp0_sd_vcc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
cp0_sfp_eth0: sfp-eth@0 {
|
||||
compatible = "sff,sfp";
|
||||
i2c-bus = <&cp0_sfpp0_i2c>;
|
||||
los-gpio = <&cp0_module_expander1 11 GPIO_ACTIVE_HIGH>;
|
||||
mod-def0-gpio = <&cp0_module_expander1 10 GPIO_ACTIVE_LOW>;
|
||||
tx-disable-gpio = <&cp0_module_expander1 9 GPIO_ACTIVE_HIGH>;
|
||||
tx-fault-gpio = <&cp0_module_expander1 8 GPIO_ACTIVE_HIGH>;
|
||||
/*
|
||||
* SFP cages are unconnected on early PCBs because of an the I2C
|
||||
* lanes not being connected. Prevent the port for being
|
||||
* unusable by disabling the SFP node.
|
||||
/* Setup A has SPI1 flash as a boot device, while setup B uses NAND flash.
|
||||
* Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
|
||||
* simultaneously. When SPI controller is enabled, NAND should be disabled.
|
||||
*/
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* on-board eMMC - U9 */
|
||||
&ap_sdhci0 {
|
||||
pinctrl-names = "default";
|
||||
bus-width = <8>;
|
||||
mmc-ddr-1_8v;
|
||||
mmc-hs400-1_8v;
|
||||
vqmmc-supply = <&ap0_reg_sd_vccq>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_crypto {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cp0_ethernet {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* SLM-1521-V2, CON9 */
|
||||
&cp0_eth0 {
|
||||
status = "disabled";
|
||||
phy-mode = "10gbase-kr";
|
||||
/* Generic PHY, providing serdes lanes */
|
||||
phys = <&cp0_comphy4 0>;
|
||||
managed = "in-band-status";
|
||||
sfp = <&cp0_sfp_eth0>;
|
||||
};
|
||||
|
||||
/* CON56 */
|
||||
&cp0_eth1 {
|
||||
status = "okay";
|
||||
phy = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
|
||||
/* CON57 */
|
||||
&cp0_eth2 {
|
||||
status = "okay";
|
||||
phy = <&phy1>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
|
||||
&cp0_gpio1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_gpio2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_i2c0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp0_i2c0_pins>;
|
||||
clock-frequency = <100000>;
|
||||
|
||||
/* U36 */
|
||||
expander0: pca953x@21 {
|
||||
compatible = "nxp,pca9555";
|
||||
pinctrl-names = "default";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x21>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* U42 */
|
||||
eeprom0: eeprom@50 {
|
||||
compatible = "atmel,24c64";
|
||||
reg = <0x50>;
|
||||
pagesize = <0x20>;
|
||||
};
|
||||
|
||||
/* U38 */
|
||||
eeprom1: eeprom@57 {
|
||||
compatible = "atmel,24c64";
|
||||
reg = <0x57>;
|
||||
pagesize = <0x20>;
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_i2c1 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
|
||||
/* SLM-1521-V2 - U3 */
|
||||
i2c-mux@72 { /* verify address - depends on dpr */
|
||||
compatible = "nxp,pca9544";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x72>;
|
||||
cp0_sfpp0_i2c: i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
i2c@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
/* U12 */
|
||||
cp0_module_expander1: pca9555@21 {
|
||||
compatible = "nxp,pca9555";
|
||||
pinctrl-names = "default";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x21>;
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_mdio {
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
/* U54 */
|
||||
&cp0_nand_controller {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&nand_pins &nand_rb>;
|
||||
|
||||
nand@0 {
|
||||
reg = <0>;
|
||||
label = "main-storage";
|
||||
nand-rb = <0>;
|
||||
nand-ecc-mode = "hw";
|
||||
nand-on-flash-bbt;
|
||||
nand-ecc-strength = <8>;
|
||||
nand-ecc-step-size = <512>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "U-Boot";
|
||||
reg = <0 0x200000>;
|
||||
};
|
||||
partition@200000 {
|
||||
label = "Linux";
|
||||
reg = <0x200000 0xe00000>;
|
||||
};
|
||||
partition@1000000 {
|
||||
label = "Filesystem";
|
||||
reg = <0x1000000 0x3f000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* SLM-1521-V2, CON6 */
|
||||
&cp0_pcie0 {
|
||||
status = "okay";
|
||||
num-lanes = <4>;
|
||||
num-viewport = <8>;
|
||||
/* Generic PHY, providing serdes lanes */
|
||||
phys = <&cp0_comphy0 0
|
||||
&cp0_comphy1 0
|
||||
&cp0_comphy2 0
|
||||
&cp0_comphy3 0>;
|
||||
};
|
||||
|
||||
&cp0_sata0 {
|
||||
status = "okay";
|
||||
|
||||
/* SLM-1521-V2, CON2 */
|
||||
sata-port@1 {
|
||||
status = "okay";
|
||||
/* Generic PHY, providing serdes lanes */
|
||||
phys = <&cp0_comphy5 1>;
|
||||
};
|
||||
};
|
||||
|
||||
/* CON 28 */
|
||||
&cp0_sdhci0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp0_sdhci_pins
|
||||
&cp0_sdhci_cd_pins>;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>;
|
||||
no-1-8-v;
|
||||
vqmmc-supply = <&cp0_reg_sd_vccq>;
|
||||
vmmc-supply = <&cp0_reg_sd_vcc>;
|
||||
};
|
||||
|
||||
/* U55 */
|
||||
&cp0_spi1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp0_spi0_pins>;
|
||||
reg = <0x700680 0x50>;
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0x0>;
|
||||
/* On-board MUX does not allow higher frequencies */
|
||||
spi-max-frequency = <40000000>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "U-Boot-0";
|
||||
reg = <0x0 0x200000>;
|
||||
};
|
||||
|
||||
partition@400000 {
|
||||
label = "Filesystem-0";
|
||||
reg = <0x200000 0xe00000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_syscon0 {
|
||||
cp0_pinctrl: pinctrl {
|
||||
compatible = "marvell,cp115-standalone-pinctrl";
|
||||
|
||||
cp0_i2c0_pins: cp0-i2c-pins-0 {
|
||||
marvell,pins = "mpp37", "mpp38";
|
||||
marvell,function = "i2c0";
|
||||
};
|
||||
cp0_i2c1_pins: cp0-i2c-pins-1 {
|
||||
marvell,pins = "mpp35", "mpp36";
|
||||
marvell,function = "i2c1";
|
||||
};
|
||||
cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
|
||||
marvell,pins = "mpp0", "mpp1", "mpp2",
|
||||
"mpp3", "mpp4", "mpp5",
|
||||
"mpp6", "mpp7", "mpp8",
|
||||
"mpp9", "mpp10", "mpp11";
|
||||
marvell,function = "ge0";
|
||||
};
|
||||
cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
|
||||
marvell,pins = "mpp44", "mpp45", "mpp46",
|
||||
"mpp47", "mpp48", "mpp49",
|
||||
"mpp50", "mpp51", "mpp52",
|
||||
"mpp53", "mpp54", "mpp55";
|
||||
marvell,function = "ge1";
|
||||
};
|
||||
cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 {
|
||||
marvell,pins = "mpp43";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
cp0_sdhci_pins: cp0-sdhi-pins-0 {
|
||||
marvell,pins = "mpp56", "mpp57", "mpp58",
|
||||
"mpp59", "mpp60", "mpp61";
|
||||
marvell,function = "sdio";
|
||||
};
|
||||
cp0_spi0_pins: cp0-spi-pins-0 {
|
||||
marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
|
||||
marvell,function = "spi1";
|
||||
};
|
||||
nand_pins: nand-pins {
|
||||
marvell,pins = "mpp15", "mpp16", "mpp17", "mpp18",
|
||||
"mpp19", "mpp20", "mpp21", "mpp22",
|
||||
"mpp23", "mpp24", "mpp25", "mpp26",
|
||||
"mpp27";
|
||||
marvell,function = "dev";
|
||||
};
|
||||
nand_rb: nand-rb {
|
||||
marvell,pins = "mpp13";
|
||||
marvell,function = "nf";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_utmi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_usb3_0 {
|
||||
status = "okay";
|
||||
usb-phy = <&cp0_usb3_0_phy0>;
|
||||
phys = <&cp0_utmi0>;
|
||||
phy-names = "utmi";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&cp0_usb3_1 {
|
||||
status = "okay";
|
||||
usb-phy = <&cp0_usb3_0_phy1>;
|
||||
phys = <&cp0_utmi1>;
|
||||
phy-names = "utmi";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,410 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (C) 2019 Marvell International Ltd.
|
||||
*
|
||||
* Device tree for the CN9130-DB board.
|
||||
*/
|
||||
|
||||
#include "cn9130.dtsi"
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
aliases {
|
||||
gpio1 = &cp0_gpio1;
|
||||
gpio2 = &cp0_gpio2;
|
||||
i2c0 = &cp0_i2c0;
|
||||
ethernet0 = &cp0_eth0;
|
||||
ethernet1 = &cp0_eth1;
|
||||
ethernet2 = &cp0_eth2;
|
||||
spi1 = &cp0_spi0;
|
||||
spi2 = &cp0_spi1;
|
||||
};
|
||||
|
||||
memory@00000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x80000000>;
|
||||
};
|
||||
|
||||
ap0_reg_sd_vccq: ap0_sd_vccq@0 {
|
||||
compatible = "regulator-gpio";
|
||||
regulator-name = "ap0_sd_vccq";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpios = <&expander0 8 GPIO_ACTIVE_HIGH>;
|
||||
states = <1800000 0x1 3300000 0x0>;
|
||||
};
|
||||
|
||||
cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "cp0-xhci0-vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
cp0_usb3_0_phy0: cp0_usb3_phy@0 {
|
||||
compatible = "usb-nop-xceiv";
|
||||
vcc-supply = <&cp0_reg_usb3_vbus0>;
|
||||
};
|
||||
|
||||
cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "cp0-xhci1-vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
cp0_usb3_0_phy1: cp0_usb3_phy@1 {
|
||||
compatible = "usb-nop-xceiv";
|
||||
vcc-supply = <&cp0_reg_usb3_vbus1>;
|
||||
};
|
||||
|
||||
cp0_reg_sd_vccq: cp0_sd_vccq@0 {
|
||||
compatible = "regulator-gpio";
|
||||
regulator-name = "cp0_sd_vccq";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpios = <&expander0 15 GPIO_ACTIVE_HIGH>;
|
||||
states = <1800000 0x1
|
||||
3300000 0x0>;
|
||||
};
|
||||
|
||||
cp0_reg_sd_vcc: cp0_sd_vcc@0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "cp0_sd_vcc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
cp0_sfp_eth0: sfp-eth@0 {
|
||||
compatible = "sff,sfp";
|
||||
i2c-bus = <&cp0_sfpp0_i2c>;
|
||||
los-gpio = <&cp0_module_expander1 11 GPIO_ACTIVE_HIGH>;
|
||||
mod-def0-gpio = <&cp0_module_expander1 10 GPIO_ACTIVE_LOW>;
|
||||
tx-disable-gpio = <&cp0_module_expander1 9 GPIO_ACTIVE_HIGH>;
|
||||
tx-fault-gpio = <&cp0_module_expander1 8 GPIO_ACTIVE_HIGH>;
|
||||
/*
|
||||
* SFP cages are unconnected on early PCBs because of an the I2C
|
||||
* lanes not being connected. Prevent the port for being
|
||||
* unusable by disabling the SFP node.
|
||||
*/
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* on-board eMMC - U9 */
|
||||
&ap_sdhci0 {
|
||||
pinctrl-names = "default";
|
||||
bus-width = <8>;
|
||||
vqmmc-supply = <&ap0_reg_sd_vccq>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_crypto {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cp0_ethernet {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* SLM-1521-V2, CON9 */
|
||||
&cp0_eth0 {
|
||||
status = "okay";
|
||||
phy-mode = "10gbase-r";
|
||||
/* Generic PHY, providing serdes lanes */
|
||||
phys = <&cp0_comphy4 0>;
|
||||
managed = "in-band-status";
|
||||
sfp = <&cp0_sfp_eth0>;
|
||||
};
|
||||
|
||||
/* CON56 */
|
||||
&cp0_eth1 {
|
||||
status = "okay";
|
||||
phy = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
|
||||
/* CON57 */
|
||||
&cp0_eth2 {
|
||||
status = "okay";
|
||||
phy = <&phy1>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
|
||||
&cp0_gpio1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_gpio2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_i2c0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp0_i2c0_pins>;
|
||||
clock-frequency = <100000>;
|
||||
|
||||
/* U36 */
|
||||
expander0: pca953x@21 {
|
||||
compatible = "nxp,pca9555";
|
||||
pinctrl-names = "default";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x21>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* U42 */
|
||||
eeprom0: eeprom@50 {
|
||||
compatible = "atmel,24c64";
|
||||
reg = <0x50>;
|
||||
pagesize = <0x20>;
|
||||
};
|
||||
|
||||
/* U38 */
|
||||
eeprom1: eeprom@57 {
|
||||
compatible = "atmel,24c64";
|
||||
reg = <0x57>;
|
||||
pagesize = <0x20>;
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_i2c1 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
|
||||
/* SLM-1521-V2 - U3 */
|
||||
i2c-mux@72 { /* verify address - depends on dpr */
|
||||
compatible = "nxp,pca9544";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x72>;
|
||||
cp0_sfpp0_i2c: i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
i2c@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
/* U12 */
|
||||
cp0_module_expander1: pca9555@21 {
|
||||
compatible = "nxp,pca9555";
|
||||
pinctrl-names = "default";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x21>;
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_mdio {
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
/* U54 */
|
||||
&cp0_nand_controller {
|
||||
status = "disabled";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&nand_pins &nand_rb>;
|
||||
|
||||
nand@0 {
|
||||
reg = <0>;
|
||||
label = "main-storage";
|
||||
nand-rb = <0>;
|
||||
nand-ecc-mode = "hw";
|
||||
nand-on-flash-bbt;
|
||||
nand-ecc-strength = <8>;
|
||||
nand-ecc-step-size = <512>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "U-Boot";
|
||||
reg = <0 0x200000>;
|
||||
};
|
||||
partition@200000 {
|
||||
label = "Linux";
|
||||
reg = <0x200000 0xe00000>;
|
||||
};
|
||||
partition@1000000 {
|
||||
label = "Filesystem";
|
||||
reg = <0x1000000 0x3f000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* SLM-1521-V2, CON6 */
|
||||
&cp0_pcie0 {
|
||||
status = "okay";
|
||||
num-lanes = <4>;
|
||||
num-viewport = <8>;
|
||||
/* Generic PHY, providing serdes lanes */
|
||||
phys = <&cp0_comphy0 0
|
||||
&cp0_comphy1 0
|
||||
&cp0_comphy2 0
|
||||
&cp0_comphy3 0>;
|
||||
};
|
||||
|
||||
&cp0_sata0 {
|
||||
status = "okay";
|
||||
|
||||
/* SLM-1521-V2, CON2 */
|
||||
sata-port@1 {
|
||||
status = "okay";
|
||||
/* Generic PHY, providing serdes lanes */
|
||||
phys = <&cp0_comphy5 1>;
|
||||
};
|
||||
};
|
||||
|
||||
/* CON 28 */
|
||||
&cp0_sdhci0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp0_sdhci_pins
|
||||
&cp0_sdhci_cd_pins>;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>;
|
||||
no-1-8-v;
|
||||
vqmmc-supply = <&cp0_reg_sd_vccq>;
|
||||
vmmc-supply = <&cp0_reg_sd_vcc>;
|
||||
};
|
||||
|
||||
/* U55 */
|
||||
&cp0_spi1 {
|
||||
status = "disabled";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp0_spi0_pins>;
|
||||
reg = <0x700680 0x50>;
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0x0>;
|
||||
/* On-board MUX does not allow higher frequencies */
|
||||
spi-max-frequency = <40000000>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "U-Boot-0";
|
||||
reg = <0x0 0x200000>;
|
||||
};
|
||||
|
||||
partition@400000 {
|
||||
label = "Filesystem-0";
|
||||
reg = <0x200000 0xe00000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_syscon0 {
|
||||
cp0_pinctrl: pinctrl {
|
||||
compatible = "marvell,cp115-standalone-pinctrl";
|
||||
|
||||
cp0_i2c0_pins: cp0-i2c-pins-0 {
|
||||
marvell,pins = "mpp37", "mpp38";
|
||||
marvell,function = "i2c0";
|
||||
};
|
||||
cp0_i2c1_pins: cp0-i2c-pins-1 {
|
||||
marvell,pins = "mpp35", "mpp36";
|
||||
marvell,function = "i2c1";
|
||||
};
|
||||
cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
|
||||
marvell,pins = "mpp0", "mpp1", "mpp2",
|
||||
"mpp3", "mpp4", "mpp5",
|
||||
"mpp6", "mpp7", "mpp8",
|
||||
"mpp9", "mpp10", "mpp11";
|
||||
marvell,function = "ge0";
|
||||
};
|
||||
cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
|
||||
marvell,pins = "mpp44", "mpp45", "mpp46",
|
||||
"mpp47", "mpp48", "mpp49",
|
||||
"mpp50", "mpp51", "mpp52",
|
||||
"mpp53", "mpp54", "mpp55";
|
||||
marvell,function = "ge1";
|
||||
};
|
||||
cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 {
|
||||
marvell,pins = "mpp43";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
cp0_sdhci_pins: cp0-sdhi-pins-0 {
|
||||
marvell,pins = "mpp56", "mpp57", "mpp58",
|
||||
"mpp59", "mpp60", "mpp61";
|
||||
marvell,function = "sdio";
|
||||
};
|
||||
cp0_spi0_pins: cp0-spi-pins-0 {
|
||||
marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
|
||||
marvell,function = "spi1";
|
||||
};
|
||||
nand_pins: nand-pins {
|
||||
marvell,pins = "mpp15", "mpp16", "mpp17", "mpp18",
|
||||
"mpp19", "mpp20", "mpp21", "mpp22",
|
||||
"mpp23", "mpp24", "mpp25", "mpp26",
|
||||
"mpp27";
|
||||
marvell,function = "dev";
|
||||
};
|
||||
nand_rb: nand-rb {
|
||||
marvell,pins = "mpp13";
|
||||
marvell,function = "nf";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_utmi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_usb3_0 {
|
||||
status = "okay";
|
||||
usb-phy = <&cp0_usb3_0_phy0>;
|
||||
phys = <&cp0_utmi0>;
|
||||
phy-names = "utmi";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&cp0_usb3_1 {
|
||||
status = "okay";
|
||||
usb-phy = <&cp0_usb3_0_phy1>;
|
||||
phys = <&cp0_utmi1>;
|
||||
phy-names = "utmi";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (C) 2020 Marvell International Ltd.
|
||||
*
|
||||
* Device tree for the CN9131-DB board (setup "B").
|
||||
*/
|
||||
|
||||
#include "cn9131-db.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada CN9131-DB setup B";
|
||||
};
|
||||
|
||||
/* Setup B has NAND flash as a boot device, while regular setup uses SPI flash.
|
||||
* Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
|
||||
* simultaneously. When NAND controller is enabled, SPI1 should be disabled.
|
||||
*/
|
||||
|
||||
&cp0_nand_controller {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
@ -5,203 +5,18 @@
|
|||
* Device tree for the CN9131-DB board.
|
||||
*/
|
||||
|
||||
#include "cn9130-db.dts"
|
||||
#include "cn9131-db.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada CN9131-DB";
|
||||
compatible = "marvell,cn9131", "marvell,cn9130",
|
||||
"marvell,armada-ap807-quad", "marvell,armada-ap807";
|
||||
|
||||
aliases {
|
||||
gpio3 = &cp1_gpio1;
|
||||
gpio4 = &cp1_gpio2;
|
||||
ethernet3 = &cp1_eth0;
|
||||
ethernet4 = &cp1_eth1;
|
||||
model = "Marvell Armada CN9131-DB setup A";
|
||||
};
|
||||
|
||||
cp1_reg_usb3_vbus0: cp1_usb3_vbus@0 {
|
||||
compatible = "regulator-fixed";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp1_xhci0_vbus_pins>;
|
||||
regulator-name = "cp1-xhci0-vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&cp1_gpio1 3 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
cp1_usb3_0_phy0: cp1_usb3_phy0 {
|
||||
compatible = "usb-nop-xceiv";
|
||||
vcc-supply = <&cp1_reg_usb3_vbus0>;
|
||||
};
|
||||
|
||||
cp1_sfp_eth1: sfp-eth1 {
|
||||
compatible = "sff,sfp";
|
||||
i2c-bus = <&cp1_i2c0>;
|
||||
los-gpio = <&cp1_gpio1 11 GPIO_ACTIVE_HIGH>;
|
||||
mod-def0-gpio = <&cp1_gpio1 10 GPIO_ACTIVE_LOW>;
|
||||
tx-disable-gpio = <&cp1_gpio1 9 GPIO_ACTIVE_HIGH>;
|
||||
tx-fault-gpio = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp1_sfp_pins>;
|
||||
/*
|
||||
* SFP cages are unconnected on early PCBs because of an the I2C
|
||||
* lanes not being connected. Prevent the port for being
|
||||
* unusable by disabling the SFP node.
|
||||
*/
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* Instantiate the first slave CP115
|
||||
/* Setup A has SPI1 flash as a boot device, while setup B uses NAND flash.
|
||||
* Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
|
||||
* simultaneously. When SPI controller is enabled, NAND should be disabled.
|
||||
*/
|
||||
|
||||
#define CP11X_NAME cp1
|
||||
#define CP11X_BASE f4000000
|
||||
#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
|
||||
#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
|
||||
#define CP11X_PCIE0_BASE f4600000
|
||||
#define CP11X_PCIE1_BASE f4620000
|
||||
#define CP11X_PCIE2_BASE f4640000
|
||||
|
||||
#include "armada-cp115.dtsi"
|
||||
|
||||
#undef CP11X_NAME
|
||||
#undef CP11X_BASE
|
||||
#undef CP11X_PCIEx_MEM_BASE
|
||||
#undef CP11X_PCIEx_MEM_SIZE
|
||||
#undef CP11X_PCIE0_BASE
|
||||
#undef CP11X_PCIE1_BASE
|
||||
#undef CP11X_PCIE2_BASE
|
||||
|
||||
&cp1_crypto {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cp1_ethernet {
|
||||
&cp0_spi1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* CON50 */
|
||||
&cp1_eth0 {
|
||||
status = "disabled";
|
||||
phy-mode = "10gbase-kr";
|
||||
/* Generic PHY, providing serdes lanes */
|
||||
phys = <&cp1_comphy4 0>;
|
||||
managed = "in-band-status";
|
||||
sfp = <&cp1_sfp_eth1>;
|
||||
};
|
||||
|
||||
&cp1_gpio1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp1_gpio2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp1_i2c0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp1_i2c0_pins>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
/* CON40 */
|
||||
&cp1_pcie0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp1_pcie_reset_pins>;
|
||||
num-lanes = <2>;
|
||||
num-viewport = <8>;
|
||||
marvell,reset-gpio = <&cp1_gpio1 0 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
/* Generic PHY, providing serdes lanes */
|
||||
phys = <&cp1_comphy0 0
|
||||
&cp1_comphy1 0>;
|
||||
};
|
||||
|
||||
&cp1_sata0 {
|
||||
status = "okay";
|
||||
|
||||
/* CON32 */
|
||||
sata-port@1 {
|
||||
/* Generic PHY, providing serdes lanes */
|
||||
phys = <&cp1_comphy5 1>;
|
||||
};
|
||||
};
|
||||
|
||||
/* U24 */
|
||||
&cp1_spi1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp1_spi0_pins>;
|
||||
reg = <0x700680 0x50>;
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0x0>;
|
||||
/* On-board MUX does not allow higher frequencies */
|
||||
spi-max-frequency = <40000000>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "U-Boot-1";
|
||||
reg = <0x0 0x200000>;
|
||||
};
|
||||
|
||||
partition@400000 {
|
||||
label = "Filesystem-1";
|
||||
reg = <0x200000 0xe00000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&cp1_syscon0 {
|
||||
cp1_pinctrl: pinctrl {
|
||||
compatible = "marvell,cp115-standalone-pinctrl";
|
||||
|
||||
cp1_i2c0_pins: cp1-i2c-pins-0 {
|
||||
marvell,pins = "mpp37", "mpp38";
|
||||
marvell,function = "i2c0";
|
||||
};
|
||||
cp1_spi0_pins: cp1-spi-pins-0 {
|
||||
marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
|
||||
marvell,function = "spi1";
|
||||
};
|
||||
cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
|
||||
marvell,pins = "mpp3";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
cp1_sfp_pins: sfp-pins {
|
||||
marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
cp1_pcie_reset_pins: cp1-pcie-reset-pins {
|
||||
marvell,pins = "mpp0";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* CON58 */
|
||||
&cp1_utmi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp1_usb3_1 {
|
||||
status = "okay";
|
||||
usb-phy = <&cp1_usb3_0_phy0>;
|
||||
/* Generic PHY, providing serdes lanes */
|
||||
phys = <&cp1_comphy3 1>, <&cp1_utmi1>;
|
||||
phy-names = "usb", "utmi";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,206 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (C) 2020 Marvell International Ltd.
|
||||
*
|
||||
* Device tree for the CN9131-DB board.
|
||||
*/
|
||||
|
||||
#include "cn9130-db.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "marvell,cn9131", "marvell,cn9130",
|
||||
"marvell,armada-ap807-quad", "marvell,armada-ap807";
|
||||
|
||||
aliases {
|
||||
gpio3 = &cp1_gpio1;
|
||||
gpio4 = &cp1_gpio2;
|
||||
ethernet3 = &cp1_eth0;
|
||||
ethernet4 = &cp1_eth1;
|
||||
};
|
||||
|
||||
cp1_reg_usb3_vbus0: cp1_usb3_vbus@0 {
|
||||
compatible = "regulator-fixed";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp1_xhci0_vbus_pins>;
|
||||
regulator-name = "cp1-xhci0-vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&cp1_gpio1 3 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
cp1_usb3_0_phy0: cp1_usb3_phy0 {
|
||||
compatible = "usb-nop-xceiv";
|
||||
vcc-supply = <&cp1_reg_usb3_vbus0>;
|
||||
};
|
||||
|
||||
cp1_sfp_eth1: sfp-eth1 {
|
||||
compatible = "sff,sfp";
|
||||
i2c-bus = <&cp1_i2c0>;
|
||||
los-gpio = <&cp1_gpio1 11 GPIO_ACTIVE_HIGH>;
|
||||
mod-def0-gpio = <&cp1_gpio1 10 GPIO_ACTIVE_LOW>;
|
||||
tx-disable-gpio = <&cp1_gpio1 9 GPIO_ACTIVE_HIGH>;
|
||||
tx-fault-gpio = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp1_sfp_pins>;
|
||||
/*
|
||||
* SFP cages are unconnected on early PCBs because of an the I2C
|
||||
* lanes not being connected. Prevent the port for being
|
||||
* unusable by disabling the SFP node.
|
||||
*/
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* Instantiate the first slave CP115
|
||||
*/
|
||||
|
||||
#define CP11X_NAME cp1
|
||||
#define CP11X_BASE f4000000
|
||||
#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
|
||||
#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
|
||||
#define CP11X_PCIE0_BASE f4600000
|
||||
#define CP11X_PCIE1_BASE f4620000
|
||||
#define CP11X_PCIE2_BASE f4640000
|
||||
|
||||
#include "armada-cp115.dtsi"
|
||||
|
||||
#undef CP11X_NAME
|
||||
#undef CP11X_BASE
|
||||
#undef CP11X_PCIEx_MEM_BASE
|
||||
#undef CP11X_PCIEx_MEM_SIZE
|
||||
#undef CP11X_PCIE0_BASE
|
||||
#undef CP11X_PCIE1_BASE
|
||||
#undef CP11X_PCIE2_BASE
|
||||
|
||||
&cp1_crypto {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cp1_ethernet {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* CON50 */
|
||||
&cp1_eth0 {
|
||||
status = "okay";
|
||||
phy-mode = "10gbase-r";
|
||||
/* Generic PHY, providing serdes lanes */
|
||||
phys = <&cp1_comphy4 0>;
|
||||
managed = "in-band-status";
|
||||
sfp = <&cp1_sfp_eth1>;
|
||||
};
|
||||
|
||||
&cp1_gpio1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp1_gpio2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp1_i2c0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp1_i2c0_pins>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
/* CON40 */
|
||||
&cp1_pcie0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp1_pcie_reset_pins>;
|
||||
num-lanes = <2>;
|
||||
num-viewport = <8>;
|
||||
marvell,reset-gpio = <&cp1_gpio1 0 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
/* Generic PHY, providing serdes lanes */
|
||||
phys = <&cp1_comphy0 0
|
||||
&cp1_comphy1 0>;
|
||||
};
|
||||
|
||||
&cp1_sata0 {
|
||||
status = "okay";
|
||||
|
||||
/* CON32 */
|
||||
sata-port@1 {
|
||||
/* Generic PHY, providing serdes lanes */
|
||||
phys = <&cp1_comphy5 1>;
|
||||
};
|
||||
};
|
||||
|
||||
/* U24 */
|
||||
&cp1_spi1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp1_spi0_pins>;
|
||||
reg = <0x700680 0x50>;
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0x0>;
|
||||
/* On-board MUX does not allow higher frequencies */
|
||||
spi-max-frequency = <40000000>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "U-Boot-1";
|
||||
reg = <0x0 0x200000>;
|
||||
};
|
||||
|
||||
partition@400000 {
|
||||
label = "Filesystem-1";
|
||||
reg = <0x200000 0xe00000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&cp1_syscon0 {
|
||||
cp1_pinctrl: pinctrl {
|
||||
compatible = "marvell,cp115-standalone-pinctrl";
|
||||
|
||||
cp1_i2c0_pins: cp1-i2c-pins-0 {
|
||||
marvell,pins = "mpp37", "mpp38";
|
||||
marvell,function = "i2c0";
|
||||
};
|
||||
cp1_spi0_pins: cp1-spi-pins-0 {
|
||||
marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
|
||||
marvell,function = "spi1";
|
||||
};
|
||||
cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
|
||||
marvell,pins = "mpp3";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
cp1_sfp_pins: sfp-pins {
|
||||
marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
cp1_pcie_reset_pins: cp1-pcie-reset-pins {
|
||||
marvell,pins = "mpp0";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* CON58 */
|
||||
&cp1_utmi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp1_usb3_1 {
|
||||
status = "okay";
|
||||
usb-phy = <&cp1_usb3_0_phy0>;
|
||||
/* Generic PHY, providing serdes lanes */
|
||||
phys = <&cp1_comphy3 1>, <&cp1_utmi1>;
|
||||
phy-names = "usb", "utmi";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (C) 2019 Marvell International Ltd.
|
||||
*
|
||||
* Device tree for the CN9132-DB board.
|
||||
*/
|
||||
|
||||
#include "cn9132-db.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada CN9132-DB setup B";
|
||||
};
|
||||
|
||||
/* Setup B has NAND flash as a boot device, while regular setup uses SPI flash.
|
||||
* Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
|
||||
* simultaneously. When NAND controller is enabled, SPI1 should be disabled.
|
||||
*/
|
||||
|
||||
&cp0_nand_controller {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
@ -5,224 +5,18 @@
|
|||
* Device tree for the CN9132-DB board.
|
||||
*/
|
||||
|
||||
#include "cn9131-db.dts"
|
||||
#include "cn9132-db.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada CN9132-DB";
|
||||
compatible = "marvell,cn9132", "marvell,cn9131", "marvell,cn9130",
|
||||
"marvell,armada-ap807-quad", "marvell,armada-ap807";
|
||||
|
||||
aliases {
|
||||
gpio5 = &cp2_gpio1;
|
||||
gpio6 = &cp2_gpio2;
|
||||
ethernet5 = &cp2_eth0;
|
||||
model = "Marvell Armada CN9132-DB setup A";
|
||||
};
|
||||
|
||||
cp2_reg_usb3_vbus0: cp2_usb3_vbus@0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "cp2-xhci0-vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
cp2_usb3_0_phy0: cp2_usb3_phy0 {
|
||||
compatible = "usb-nop-xceiv";
|
||||
vcc-supply = <&cp2_reg_usb3_vbus0>;
|
||||
};
|
||||
|
||||
cp2_reg_usb3_vbus1: cp2_usb3_vbus@1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "cp2-xhci1-vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
cp2_usb3_0_phy1: cp2_usb3_phy1 {
|
||||
compatible = "usb-nop-xceiv";
|
||||
vcc-supply = <&cp2_reg_usb3_vbus1>;
|
||||
};
|
||||
|
||||
cp2_reg_sd_vccq: cp2_sd_vccq@0 {
|
||||
compatible = "regulator-gpio";
|
||||
regulator-name = "cp2_sd_vcc";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpios = <&cp2_gpio2 17 GPIO_ACTIVE_HIGH>;
|
||||
states = <1800000 0x1 3300000 0x0>;
|
||||
};
|
||||
|
||||
cp2_sfp_eth0: sfp-eth0 {
|
||||
compatible = "sff,sfp";
|
||||
i2c-bus = <&cp2_sfpp0_i2c>;
|
||||
los-gpio = <&cp2_module_expander1 11 GPIO_ACTIVE_HIGH>;
|
||||
mod-def0-gpio = <&cp2_module_expander1 10 GPIO_ACTIVE_LOW>;
|
||||
tx-disable-gpio = <&cp2_module_expander1 9 GPIO_ACTIVE_HIGH>;
|
||||
tx-fault-gpio = <&cp2_module_expander1 8 GPIO_ACTIVE_HIGH>;
|
||||
/*
|
||||
* SFP cages are unconnected on early PCBs because of an the I2C
|
||||
* lanes not being connected. Prevent the port for being
|
||||
* unusable by disabling the SFP node.
|
||||
*/
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* Instantiate the second slave CP115
|
||||
/* Setup A has SPI1 flash as a boot device, while setup B uses NAND flash.
|
||||
* Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
|
||||
* simultaneously. When SPI controller is enabled, NAND should be disabled.
|
||||
*/
|
||||
|
||||
#define CP11X_NAME cp2
|
||||
#define CP11X_BASE f6000000
|
||||
#define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000))
|
||||
#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
|
||||
#define CP11X_PCIE0_BASE f6600000
|
||||
#define CP11X_PCIE1_BASE f6620000
|
||||
#define CP11X_PCIE2_BASE f6640000
|
||||
|
||||
#include "armada-cp115.dtsi"
|
||||
|
||||
#undef CP11X_NAME
|
||||
#undef CP11X_BASE
|
||||
#undef CP11X_PCIEx_MEM_BASE
|
||||
#undef CP11X_PCIEx_MEM_SIZE
|
||||
#undef CP11X_PCIE0_BASE
|
||||
#undef CP11X_PCIE1_BASE
|
||||
#undef CP11X_PCIE2_BASE
|
||||
|
||||
&cp2_crypto {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cp2_ethernet {
|
||||
&cp0_spi1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* SLM-1521-V2, CON9 */
|
||||
&cp2_eth0 {
|
||||
status = "disabled";
|
||||
phy-mode = "10gbase-kr";
|
||||
/* Generic PHY, providing serdes lanes */
|
||||
phys = <&cp2_comphy4 0>;
|
||||
managed = "in-band-status";
|
||||
sfp = <&cp2_sfp_eth0>;
|
||||
};
|
||||
|
||||
&cp2_gpio1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp2_gpio2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp2_i2c0 {
|
||||
clock-frequency = <100000>;
|
||||
|
||||
/* SLM-1521-V2 - U3 */
|
||||
i2c-mux@72 {
|
||||
compatible = "nxp,pca9544";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x72>;
|
||||
cp2_sfpp0_i2c: i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
i2c@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
/* U12 */
|
||||
cp2_module_expander1: pca9555@21 {
|
||||
compatible = "nxp,pca9555";
|
||||
pinctrl-names = "default";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x21>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* SLM-1521-V2, CON6 */
|
||||
&cp2_pcie0 {
|
||||
status = "okay";
|
||||
num-lanes = <2>;
|
||||
num-viewport = <8>;
|
||||
/* Generic PHY, providing serdes lanes */
|
||||
phys = <&cp2_comphy0 0
|
||||
&cp2_comphy1 0>;
|
||||
};
|
||||
|
||||
/* SLM-1521-V2, CON8 */
|
||||
&cp2_pcie2 {
|
||||
status = "okay";
|
||||
num-lanes = <1>;
|
||||
num-viewport = <8>;
|
||||
/* Generic PHY, providing serdes lanes */
|
||||
phys = <&cp2_comphy5 2>;
|
||||
};
|
||||
|
||||
&cp2_sata0 {
|
||||
status = "okay";
|
||||
|
||||
/* SLM-1521-V2, CON4 */
|
||||
sata-port@0 {
|
||||
/* Generic PHY, providing serdes lanes */
|
||||
phys = <&cp2_comphy2 0>;
|
||||
};
|
||||
};
|
||||
|
||||
/* CON 2 on SLM-1683 - microSD */
|
||||
&cp2_sdhci0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp2_sdhci_pins>;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&cp2_gpio2 23 GPIO_ACTIVE_LOW>;
|
||||
vqmmc-supply = <&cp2_reg_sd_vccq>;
|
||||
};
|
||||
|
||||
&cp2_syscon0 {
|
||||
cp2_pinctrl: pinctrl {
|
||||
compatible = "marvell,cp115-standalone-pinctrl";
|
||||
|
||||
cp2_i2c0_pins: cp2-i2c-pins-0 {
|
||||
marvell,pins = "mpp37", "mpp38";
|
||||
marvell,function = "i2c0";
|
||||
};
|
||||
cp2_sdhci_pins: cp2-sdhi-pins-0 {
|
||||
marvell,pins = "mpp56", "mpp57", "mpp58",
|
||||
"mpp59", "mpp60", "mpp61";
|
||||
marvell,function = "sdio";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cp2_utmi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp2_usb3_0 {
|
||||
status = "okay";
|
||||
usb-phy = <&cp2_usb3_0_phy0>;
|
||||
phys = <&cp2_utmi0>;
|
||||
phy-names = "usb";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
/* SLM-1521-V2, CON11 */
|
||||
&cp2_usb3_1 {
|
||||
status = "okay";
|
||||
usb-phy = <&cp2_usb3_0_phy1>;
|
||||
/* Generic PHY, providing serdes lanes */
|
||||
phys = <&cp2_comphy3 1>, <&cp2_utmi1>;
|
||||
phy-names = "usb", "utmi";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,227 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (C) 2020 Marvell International Ltd.
|
||||
*
|
||||
* Device tree for the CN9132-DB board.
|
||||
*/
|
||||
|
||||
#include "cn9131-db.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "marvell,cn9132", "marvell,cn9131", "marvell,cn9130",
|
||||
"marvell,armada-ap807-quad", "marvell,armada-ap807";
|
||||
|
||||
aliases {
|
||||
gpio5 = &cp2_gpio1;
|
||||
gpio6 = &cp2_gpio2;
|
||||
ethernet5 = &cp2_eth0;
|
||||
};
|
||||
|
||||
cp2_reg_usb3_vbus0: cp2_usb3_vbus@0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "cp2-xhci0-vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
cp2_usb3_0_phy0: cp2_usb3_phy0 {
|
||||
compatible = "usb-nop-xceiv";
|
||||
vcc-supply = <&cp2_reg_usb3_vbus0>;
|
||||
};
|
||||
|
||||
cp2_reg_usb3_vbus1: cp2_usb3_vbus@1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "cp2-xhci1-vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
cp2_usb3_0_phy1: cp2_usb3_phy1 {
|
||||
compatible = "usb-nop-xceiv";
|
||||
vcc-supply = <&cp2_reg_usb3_vbus1>;
|
||||
};
|
||||
|
||||
cp2_reg_sd_vccq: cp2_sd_vccq@0 {
|
||||
compatible = "regulator-gpio";
|
||||
regulator-name = "cp2_sd_vcc";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpios = <&cp2_gpio2 17 GPIO_ACTIVE_HIGH>;
|
||||
states = <1800000 0x1 3300000 0x0>;
|
||||
};
|
||||
|
||||
cp2_sfp_eth0: sfp-eth0 {
|
||||
compatible = "sff,sfp";
|
||||
i2c-bus = <&cp2_sfpp0_i2c>;
|
||||
los-gpio = <&cp2_module_expander1 11 GPIO_ACTIVE_HIGH>;
|
||||
mod-def0-gpio = <&cp2_module_expander1 10 GPIO_ACTIVE_LOW>;
|
||||
tx-disable-gpio = <&cp2_module_expander1 9 GPIO_ACTIVE_HIGH>;
|
||||
tx-fault-gpio = <&cp2_module_expander1 8 GPIO_ACTIVE_HIGH>;
|
||||
/*
|
||||
* SFP cages are unconnected on early PCBs because of an the I2C
|
||||
* lanes not being connected. Prevent the port for being
|
||||
* unusable by disabling the SFP node.
|
||||
*/
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* Instantiate the second slave CP115
|
||||
*/
|
||||
|
||||
#define CP11X_NAME cp2
|
||||
#define CP11X_BASE f6000000
|
||||
#define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000))
|
||||
#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
|
||||
#define CP11X_PCIE0_BASE f6600000
|
||||
#define CP11X_PCIE1_BASE f6620000
|
||||
#define CP11X_PCIE2_BASE f6640000
|
||||
|
||||
#include "armada-cp115.dtsi"
|
||||
|
||||
#undef CP11X_NAME
|
||||
#undef CP11X_BASE
|
||||
#undef CP11X_PCIEx_MEM_BASE
|
||||
#undef CP11X_PCIEx_MEM_SIZE
|
||||
#undef CP11X_PCIE0_BASE
|
||||
#undef CP11X_PCIE1_BASE
|
||||
#undef CP11X_PCIE2_BASE
|
||||
|
||||
&cp2_crypto {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cp2_ethernet {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* SLM-1521-V2, CON9 */
|
||||
&cp2_eth0 {
|
||||
status = "disabled";
|
||||
phy-mode = "10gbase-r";
|
||||
/* Generic PHY, providing serdes lanes */
|
||||
phys = <&cp2_comphy4 0>;
|
||||
managed = "in-band-status";
|
||||
sfp = <&cp2_sfp_eth0>;
|
||||
};
|
||||
|
||||
&cp2_gpio1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp2_gpio2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp2_i2c0 {
|
||||
clock-frequency = <100000>;
|
||||
|
||||
/* SLM-1521-V2 - U3 */
|
||||
i2c-mux@72 {
|
||||
compatible = "nxp,pca9544";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x72>;
|
||||
cp2_sfpp0_i2c: i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
i2c@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
/* U12 */
|
||||
cp2_module_expander1: pca9555@21 {
|
||||
compatible = "nxp,pca9555";
|
||||
pinctrl-names = "default";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x21>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* SLM-1521-V2, CON6 */
|
||||
&cp2_pcie0 {
|
||||
status = "okay";
|
||||
num-lanes = <2>;
|
||||
num-viewport = <8>;
|
||||
/* Generic PHY, providing serdes lanes */
|
||||
phys = <&cp2_comphy0 0
|
||||
&cp2_comphy1 0>;
|
||||
};
|
||||
|
||||
/* SLM-1521-V2, CON8 */
|
||||
&cp2_pcie2 {
|
||||
status = "okay";
|
||||
num-lanes = <1>;
|
||||
num-viewport = <8>;
|
||||
/* Generic PHY, providing serdes lanes */
|
||||
phys = <&cp2_comphy5 2>;
|
||||
};
|
||||
|
||||
&cp2_sata0 {
|
||||
status = "okay";
|
||||
|
||||
/* SLM-1521-V2, CON4 */
|
||||
sata-port@0 {
|
||||
/* Generic PHY, providing serdes lanes */
|
||||
phys = <&cp2_comphy2 0>;
|
||||
};
|
||||
};
|
||||
|
||||
/* CON 2 on SLM-1683 - microSD */
|
||||
&cp2_sdhci0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp2_sdhci_pins>;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&cp2_gpio2 23 GPIO_ACTIVE_LOW>;
|
||||
vqmmc-supply = <&cp2_reg_sd_vccq>;
|
||||
};
|
||||
|
||||
&cp2_syscon0 {
|
||||
cp2_pinctrl: pinctrl {
|
||||
compatible = "marvell,cp115-standalone-pinctrl";
|
||||
|
||||
cp2_i2c0_pins: cp2-i2c-pins-0 {
|
||||
marvell,pins = "mpp37", "mpp38";
|
||||
marvell,function = "i2c0";
|
||||
};
|
||||
cp2_sdhci_pins: cp2-sdhi-pins-0 {
|
||||
marvell,pins = "mpp56", "mpp57", "mpp58",
|
||||
"mpp59", "mpp60", "mpp61";
|
||||
marvell,function = "sdio";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cp2_utmi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp2_usb3_0 {
|
||||
status = "okay";
|
||||
usb-phy = <&cp2_usb3_0_phy0>;
|
||||
phys = <&cp2_utmi0>;
|
||||
phy-names = "usb";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
/* SLM-1521-V2, CON11 */
|
||||
&cp2_usb3_1 {
|
||||
status = "okay";
|
||||
usb-phy = <&cp2_usb3_0_phy1>;
|
||||
/* Generic PHY, providing serdes lanes */
|
||||
phys = <&cp2_comphy3 1>, <&cp2_utmi1>;
|
||||
phy-names = "usb", "utmi";
|
||||
dr_mode = "host";
|
||||
};
|
||||
Loading…
Reference in New Issue