mirror of https://gitee.com/openkylin/linux.git
microblaze_v8: exception handling
Reviewed-by: Ingo Molnar <mingo@elte.hu> Acked-by: Stephen Neuendorffer <stephen.neuendorffer@xilinx.com> Acked-by: John Linn <john.linn@xilinx.com> Acked-by: John Williams <john.williams@petalogix.com> Signed-off-by: Michal Simek <monstr@monstr.eu>
This commit is contained in:
Michal Simek
parent
945ce1bc54
commit
c4df4bc155
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/*
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* Preliminary support for HW exception handing for Microblaze
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*
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* Copyright (C) 2008 Michal Simek
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* Copyright (C) 2008 PetaLogix
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* Copyright (C) 2005 John Williams <jwilliams@itee.uq.edu.au>
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file COPYING in the main directory of this
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* archive for more details.
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*/
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#ifndef _ASM_MICROBLAZE_EXCEPTIONS_H
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#define _ASM_MICROBLAZE_EXCEPTIONS_H
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#ifdef __KERNEL__
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#ifndef __ASSEMBLY__
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/* Macros to enable and disable HW exceptions in the MSR */
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/* Define MSR enable bit for HW exceptions */
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#define HWEX_MSR_BIT (1 << 8)
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#if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR
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#define __enable_hw_exceptions() \
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__asm__ __volatile__ (" msrset r0, %0; \
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nop;" \
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: \
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: "i" (HWEX_MSR_BIT) \
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: "memory")
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#define __disable_hw_exceptions() \
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__asm__ __volatile__ (" msrclr r0, %0; \
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nop;" \
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: \
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: "i" (HWEX_MSR_BIT) \
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: "memory")
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#else /* !CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR */
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#define __enable_hw_exceptions() \
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__asm__ __volatile__ (" \
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mfs r12, rmsr; \
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nop; \
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ori r12, r12, %0; \
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mts rmsr, r12; \
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nop;" \
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: \
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: "i" (HWEX_MSR_BIT) \
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: "memory", "r12")
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#define __disable_hw_exceptions() \
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__asm__ __volatile__ (" \
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mfs r12, rmsr; \
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nop; \
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andi r12, r12, ~%0; \
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mts rmsr, r12; \
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nop;" \
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: \
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: "i" (HWEX_MSR_BIT) \
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: "memory", "r12")
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#endif /* CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR */
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asmlinkage void full_exception(struct pt_regs *regs, unsigned int type,
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int fsr, int addr);
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#if defined(CONFIG_XMON)
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extern void xmon(struct pt_regs *regs);
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extern int xmon_bpt(struct pt_regs *regs);
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extern int xmon_sstep(struct pt_regs *regs);
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extern int xmon_iabr_match(struct pt_regs *regs);
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extern int xmon_dabr_match(struct pt_regs *regs);
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extern void (*xmon_fault_handler)(struct pt_regs *regs);
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void (*debugger)(struct pt_regs *regs) = xmon;
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int (*debugger_bpt)(struct pt_regs *regs) = xmon_bpt;
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int (*debugger_sstep)(struct pt_regs *regs) = xmon_sstep;
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int (*debugger_iabr_match)(struct pt_regs *regs) = xmon_iabr_match;
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int (*debugger_dabr_match)(struct pt_regs *regs) = xmon_dabr_match;
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void (*debugger_fault_handler)(struct pt_regs *regs);
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#elif defined(CONFIG_KGDB)
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void (*debugger)(struct pt_regs *regs);
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int (*debugger_bpt)(struct pt_regs *regs);
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int (*debugger_sstep)(struct pt_regs *regs);
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int (*debugger_iabr_match)(struct pt_regs *regs);
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int (*debugger_dabr_match)(struct pt_regs *regs);
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void (*debugger_fault_handler)(struct pt_regs *regs);
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#else
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#define debugger(regs) do { } while (0)
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#define debugger_bpt(regs) 0
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#define debugger_sstep(regs) 0
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#define debugger_iabr_match(regs) 0
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#define debugger_dabr_match(regs) 0
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#define debugger_fault_handler ((void (*)(struct pt_regs *))0)
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#endif
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#endif /*__ASSEMBLY__ */
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#endif /* __KERNEL__ */
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#endif /* _ASM_MICROBLAZE_EXCEPTIONS_H */
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@ -0,0 +1,124 @@
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/*
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* HW exception handling
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*
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* Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
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* Copyright (C) 2008 PetaLogix
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file COPYING in the main directory of this
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* archive for more details.
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*/
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/*
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* This file handles the architecture-dependent parts of hardware exceptions
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*/
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#include <linux/kernel.h>
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/kallsyms.h>
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#include <linux/module.h>
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#include <asm/exceptions.h>
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#include <asm/entry.h> /* For KM CPU var */
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#include <asm/uaccess.h>
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#include <asm/errno.h>
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#include <asm/ptrace.h>
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#include <asm/current.h>
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#define MICROBLAZE_ILL_OPCODE_EXCEPTION 0x02
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#define MICROBLAZE_IBUS_EXCEPTION 0x03
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#define MICROBLAZE_DBUS_EXCEPTION 0x04
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#define MICROBLAZE_DIV_ZERO_EXCEPTION 0x05
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#define MICROBLAZE_FPU_EXCEPTION 0x06
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#define MICROBLAZE_PRIVILEG_EXCEPTION 0x07
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static DEFINE_SPINLOCK(die_lock);
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void die(const char *str, struct pt_regs *fp, long err)
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{
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console_verbose();
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spin_lock_irq(&die_lock);
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printk(KERN_WARNING "Oops: %s, sig: %ld\n", str, err);
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show_regs(fp);
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spin_unlock_irq(&die_lock);
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/* do_exit() should take care of panic'ing from an interrupt
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* context so we don't handle it here
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*/
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do_exit(err);
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}
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void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
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{
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siginfo_t info;
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if (kernel_mode(regs)) {
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debugger(regs);
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die("Exception in kernel mode", regs, signr);
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}
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info.si_signo = signr;
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info.si_errno = 0;
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info.si_code = code;
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info.si_addr = (void __user *) addr;
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force_sig_info(signr, &info, current);
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}
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asmlinkage void full_exception(struct pt_regs *regs, unsigned int type,
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int fsr, int addr)
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{
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#if 0
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printk(KERN_WARNING "Exception %02x in %s mode, FSR=%08x PC=%08x ESR=%08x\n",
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type, user_mode(regs) ? "user" : "kernel", fsr,
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(unsigned int) regs->pc, (unsigned int) regs->esr);
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#endif
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switch (type & 0x1F) {
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case MICROBLAZE_ILL_OPCODE_EXCEPTION:
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_exception(SIGILL, regs, ILL_ILLOPC, addr);
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break;
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case MICROBLAZE_IBUS_EXCEPTION:
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if (user_mode(regs)) {
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printk(KERN_WARNING "Instruction bus error exception in user mode.\n");
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_exception(SIGBUS, regs, BUS_ADRERR, addr);
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return;
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}
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printk(KERN_WARNING "Instruction bus error exception in kernel mode.\n");
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die("bus exception", regs, SIGBUS);
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break;
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case MICROBLAZE_DBUS_EXCEPTION:
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if (user_mode(regs)) {
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printk(KERN_WARNING "Data bus error exception in user mode.\n");
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_exception(SIGBUS, regs, BUS_ADRERR, addr);
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return;
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}
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printk(KERN_WARNING "Data bus error exception in kernel mode.\n");
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die("bus exception", regs, SIGBUS);
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break;
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case MICROBLAZE_DIV_ZERO_EXCEPTION:
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printk(KERN_WARNING "Divide by zero exception\n");
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_exception(SIGILL, regs, ILL_ILLOPC, addr);
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break;
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case MICROBLAZE_FPU_EXCEPTION:
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/* IEEE FP exception */
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/* I removed fsr variable and use code var for storing fsr */
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if (fsr & FSR_IO)
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fsr = FPE_FLTINV;
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else if (fsr & FSR_OF)
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fsr = FPE_FLTOVF;
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else if (fsr & FSR_UF)
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fsr = FPE_FLTUND;
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else if (fsr & FSR_DZ)
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fsr = FPE_FLTDIV;
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else if (fsr & FSR_DO)
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fsr = FPE_FLTRES;
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_exception(SIGFPE, regs, fsr, addr);
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break;
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default:
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printk(KERN_WARNING "Unexpected exception %02x "
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"PC=%08x in %s mode\n", type, (unsigned int) addr,
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kernel_mode(regs) ? "kernel" : "user");
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}
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return;
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}
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@ -0,0 +1,458 @@
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/*
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* Exception handling for Microblaze
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*
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* Rewriten interrupt handling
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*
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* Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
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* Copyright (C) 2008-2009 PetaLogix
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*
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* uClinux customisation (C) 2005 John Williams
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*
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* MMU code derived from arch/ppc/kernel/head_4xx.S:
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* Copyright (C) 1995-1996 Gary Thomas <gdt@linuxppc.org>
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* Initial PowerPC version.
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* Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
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* Rewritten for PReP
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* Copyright (C) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
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* Low-level exception handers, MMU support, and rewrite.
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* Copyright (C) 1997 Dan Malek <dmalek@jlc.net>
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* PowerPC 8xx modifications.
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* Copyright (C) 1998-1999 TiVo, Inc.
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* PowerPC 403GCX modifications.
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* Copyright (C) 1999 Grant Erickson <grant@lcse.umn.edu>
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* PowerPC 403GCX/405GP modifications.
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* Copyright 2000 MontaVista Software Inc.
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* PPC405 modifications
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* PowerPC 403GCX/405GP modifications.
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* Author: MontaVista Software, Inc.
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* frank_rowand@mvista.com or source@mvista.com
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* debbie_chu@mvista.com
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*
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* Original code
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* Copyright (C) 2004 Xilinx, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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/*
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* Here are the handlers which don't require enabling translation
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* and calling other kernel code thus we can keep their design very simple
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* and do all processing in real mode. All what they need is a valid current
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* (that is an issue for the CONFIG_REGISTER_TASK_PTR case)
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* This handlers use r3,r4,r5,r6 and optionally r[current] to work therefore
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* these registers are saved/restored
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* The handlers which require translation are in entry.S --KAA
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*
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* Microblaze HW Exception Handler
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* - Non self-modifying exception handler for the following exception conditions
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* - Unalignment
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* - Instruction bus error
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* - Data bus error
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* - Illegal instruction opcode
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* - Divide-by-zero
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*
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* Note we disable interrupts during exception handling, otherwise we will
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* possibly get multiple re-entrancy if interrupt handles themselves cause
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* exceptions. JW
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*/
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#include <asm/exceptions.h>
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#include <asm/unistd.h>
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#include <asm/page.h>
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#include <asm/entry.h>
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#include <asm/current.h>
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#include <linux/linkage.h>
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#include <asm/mmu.h>
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#include <asm/pgtable.h>
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#include <asm/asm-offsets.h>
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/* Helpful Macros */
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#define EX_HANDLER_STACK_SIZ (4*19)
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#define NUM_TO_REG(num) r ## num
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#define LWREG_NOP \
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bri ex_handler_unhandled; \
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nop;
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#define SWREG_NOP \
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bri ex_handler_unhandled; \
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nop;
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/* FIXME this is weird - for noMMU kernel is not possible to use brid
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* instruction which can shorten executed time
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*/
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/* r3 is the source */
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#define R3_TO_LWREG_V(regnum) \
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swi r3, r1, 4 * regnum; \
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bri ex_handler_done;
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/* r3 is the source */
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#define R3_TO_LWREG(regnum) \
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or NUM_TO_REG (regnum), r0, r3; \
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bri ex_handler_done;
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/* r3 is the target */
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#define SWREG_TO_R3_V(regnum) \
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lwi r3, r1, 4 * regnum; \
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bri ex_sw_tail;
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/* r3 is the target */
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#define SWREG_TO_R3(regnum) \
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or r3, r0, NUM_TO_REG (regnum); \
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bri ex_sw_tail;
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.extern other_exception_handler /* Defined in exception.c */
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/*
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* hw_exception_handler - Handler for exceptions
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*
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* Exception handler notes:
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* - Handles all exceptions
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* - Does not handle unaligned exceptions during load into r17, r1, r0.
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* - Does not handle unaligned exceptions during store from r17 (cannot be
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* done) and r1 (slows down common case)
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*
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* Relevant register structures
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*
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* EAR - |----|----|----|----|----|----|----|----|
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* - < ## 32 bit faulting address ## >
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*
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* ESR - |----|----|----|----|----| - | - |-----|-----|
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* - W S REG EXC
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*
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*
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* STACK FRAME STRUCTURE (for NO_MMU)
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* ---------------------------------
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*
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* +-------------+ + 0
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* | MSR |
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* +-------------+ + 4
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* | r1 |
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* | . |
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* | . |
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* | . |
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* | . |
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* | r18 |
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* +-------------+ + 76
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* | . |
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* | . |
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*
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* NO_MMU kernel use the same r0_ram pointed space - look to vmlinux.lds.S
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* which is used for storing register values - old style was, that value were
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* stored in stack but in case of failure you lost information about register.
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* Currently you can see register value in memory in specific place.
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* In compare to with previous solution the speed should be the same.
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*
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* MMU exception handler has different handling compare to no MMU kernel.
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* Exception handler use jump table for directing of what happen. For MMU kernel
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* is this approach better because MMU relate exception are handled by asm code
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* in this file. In compare to with MMU expect of unaligned exception
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* is everything handled by C code.
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*/
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/*
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* every of these handlers is entered having R3/4/5/6/11/current saved on stack
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* and clobbered so care should be taken to restore them if someone is going to
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* return from exception
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*/
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/* wrappers to restore state before coming to entry.S */
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.global _hw_exception_handler
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.section .text
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.align 4
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.ent _hw_exception_handler
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_hw_exception_handler:
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addik r1, r1, -(EX_HANDLER_STACK_SIZ); /* Create stack frame */
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swi r3, r1, PT_R3
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swi r4, r1, PT_R4
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swi r5, r1, PT_R5
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swi r6, r1, PT_R6
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mfs r5, rmsr;
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nop
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swi r5, r1, 0;
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mfs r4, rbtr /* Save BTR before jumping to handler */
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nop
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mfs r3, resr
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nop
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andi r5, r3, 0x1000; /* Check ESR[DS] */
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beqi r5, not_in_delay_slot; /* Branch if ESR[DS] not set */
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mfs r17, rbtr; /* ESR[DS] set - return address in BTR */
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nop
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not_in_delay_slot:
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swi r17, r1, PT_R17
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andi r5, r3, 0x1F; /* Extract ESR[EXC] */
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/* Exceptions enabled here. This will allow nested exceptions */
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mfs r6, rmsr;
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nop
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swi r6, r1, 0; /* RMSR_OFFSET */
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ori r6, r6, 0x100; /* Turn ON the EE bit */
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andi r6, r6, ~2; /* Disable interrupts */
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mts rmsr, r6;
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nop
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xori r6, r5, 1; /* 00001 = Unaligned Exception */
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/* Jump to unalignment exception handler */
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beqi r6, handle_unaligned_ex;
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handle_other_ex: /* Handle Other exceptions here */
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/* Save other volatiles before we make procedure calls below */
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swi r7, r1, PT_R7
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swi r8, r1, PT_R8
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swi r9, r1, PT_R9
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swi r10, r1, PT_R10
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swi r11, r1, PT_R11
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swi r12, r1, PT_R12
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swi r14, r1, PT_R14
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swi r15, r1, PT_R15
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swi r18, r1, PT_R18
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or r5, r1, r0
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andi r6, r3, 0x1F; /* Load ESR[EC] */
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lwi r7, r0, PER_CPU(KM) /* MS: saving current kernel mode to regs */
|
||||
swi r7, r1, PT_MODE
|
||||
mfs r7, rfsr
|
||||
nop
|
||||
addk r8, r17, r0; /* Load exception address */
|
||||
bralid r15, full_exception; /* Branch to the handler */
|
||||
nop;
|
||||
|
||||
/*
|
||||
* Trigger execution of the signal handler by enabling
|
||||
* interrupts and calling an invalid syscall.
|
||||
*/
|
||||
mfs r5, rmsr;
|
||||
nop
|
||||
ori r5, r5, 2;
|
||||
mts rmsr, r5; /* enable interrupt */
|
||||
nop
|
||||
addi r12, r0, __NR_syscalls;
|
||||
brki r14, 0x08;
|
||||
mfs r5, rmsr; /* disable interrupt */
|
||||
nop
|
||||
andi r5, r5, ~2;
|
||||
mts rmsr, r5;
|
||||
nop
|
||||
|
||||
lwi r7, r1, PT_R7
|
||||
lwi r8, r1, PT_R8
|
||||
lwi r9, r1, PT_R9
|
||||
lwi r10, r1, PT_R10
|
||||
lwi r11, r1, PT_R11
|
||||
lwi r12, r1, PT_R12
|
||||
lwi r14, r1, PT_R14
|
||||
lwi r15, r1, PT_R15
|
||||
lwi r18, r1, PT_R18
|
||||
|
||||
bri ex_handler_done; /* Complete exception handling */
|
||||
|
||||
/* 0x01 - Unaligned data access exception
|
||||
* This occurs when a word access is not aligned on a word boundary,
|
||||
* or when a 16-bit access is not aligned on a 16-bit boundary.
|
||||
* This handler perform the access, and returns, except for MMU when
|
||||
* the unaligned address is last on a 4k page or the physical address is
|
||||
* not found in the page table, in which case unaligned_data_trap is called.
|
||||
*/
|
||||
handle_unaligned_ex:
|
||||
/* Working registers already saved: R3, R4, R5, R6
|
||||
* R3 = ESR
|
||||
* R4 = BTR
|
||||
*/
|
||||
mfs r4, rear;
|
||||
nop
|
||||
|
||||
andi r6, r3, 0x3E0; /* Mask and extract the register operand */
|
||||
srl r6, r6; /* r6 >> 5 */
|
||||
srl r6, r6;
|
||||
srl r6, r6;
|
||||
srl r6, r6;
|
||||
srl r6, r6;
|
||||
/* Store the register operand in a temporary location */
|
||||
sbi r6, r0, TOPHYS(ex_reg_op);
|
||||
|
||||
andi r6, r3, 0x400; /* Extract ESR[S] */
|
||||
bnei r6, ex_sw;
|
||||
ex_lw:
|
||||
andi r6, r3, 0x800; /* Extract ESR[W] */
|
||||
beqi r6, ex_lhw;
|
||||
lbui r5, r4, 0; /* Exception address in r4 */
|
||||
/* Load a word, byte-by-byte from destination address
|
||||
and save it in tmp space */
|
||||
sbi r5, r0, TOPHYS(ex_tmp_data_loc_0);
|
||||
lbui r5, r4, 1;
|
||||
sbi r5, r0, TOPHYS(ex_tmp_data_loc_1);
|
||||
lbui r5, r4, 2;
|
||||
sbi r5, r0, TOPHYS(ex_tmp_data_loc_2);
|
||||
lbui r5, r4, 3;
|
||||
sbi r5, r0, TOPHYS(ex_tmp_data_loc_3);
|
||||
/* Get the destination register value into r3 */
|
||||
lwi r3, r0, TOPHYS(ex_tmp_data_loc_0);
|
||||
bri ex_lw_tail;
|
||||
ex_lhw:
|
||||
lbui r5, r4, 0; /* Exception address in r4 */
|
||||
/* Load a half-word, byte-by-byte from destination
|
||||
address and save it in tmp space */
|
||||
sbi r5, r0, TOPHYS(ex_tmp_data_loc_0);
|
||||
lbui r5, r4, 1;
|
||||
sbi r5, r0, TOPHYS(ex_tmp_data_loc_1);
|
||||
/* Get the destination register value into r3 */
|
||||
lhui r3, r0, TOPHYS(ex_tmp_data_loc_0);
|
||||
ex_lw_tail:
|
||||
/* Get the destination register number into r5 */
|
||||
lbui r5, r0, TOPHYS(ex_reg_op);
|
||||
/* Form load_word jump table offset (lw_table + (8 * regnum)) */
|
||||
la r6, r0, TOPHYS(lw_table);
|
||||
addk r5, r5, r5;
|
||||
addk r5, r5, r5;
|
||||
addk r5, r5, r5;
|
||||
addk r5, r5, r6;
|
||||
bra r5;
|
||||
ex_lw_end: /* Exception handling of load word, ends */
|
||||
ex_sw:
|
||||
/* Get the destination register number into r5 */
|
||||
lbui r5, r0, TOPHYS(ex_reg_op);
|
||||
/* Form store_word jump table offset (sw_table + (8 * regnum)) */
|
||||
la r6, r0, TOPHYS(sw_table);
|
||||
add r5, r5, r5;
|
||||
add r5, r5, r5;
|
||||
add r5, r5, r5;
|
||||
add r5, r5, r6;
|
||||
bra r5;
|
||||
ex_sw_tail:
|
||||
mfs r6, resr;
|
||||
nop
|
||||
andi r6, r6, 0x800; /* Extract ESR[W] */
|
||||
beqi r6, ex_shw;
|
||||
/* Get the word - delay slot */
|
||||
swi r3, r0, TOPHYS(ex_tmp_data_loc_0);
|
||||
/* Store the word, byte-by-byte into destination address */
|
||||
lbui r3, r0, TOPHYS(ex_tmp_data_loc_0);
|
||||
sbi r3, r4, 0;
|
||||
lbui r3, r0, TOPHYS(ex_tmp_data_loc_1);
|
||||
sbi r3, r4, 1;
|
||||
lbui r3, r0, TOPHYS(ex_tmp_data_loc_2);
|
||||
sbi r3, r4, 2;
|
||||
lbui r3, r0, TOPHYS(ex_tmp_data_loc_3);
|
||||
sbi r3, r4, 3;
|
||||
bri ex_handler_done;
|
||||
|
||||
ex_shw:
|
||||
/* Store the lower half-word, byte-by-byte into destination address */
|
||||
swi r3, r0, TOPHYS(ex_tmp_data_loc_0);
|
||||
lbui r3, r0, TOPHYS(ex_tmp_data_loc_2);
|
||||
sbi r3, r4, 0;
|
||||
lbui r3, r0, TOPHYS(ex_tmp_data_loc_3);
|
||||
sbi r3, r4, 1;
|
||||
ex_sw_end: /* Exception handling of store word, ends. */
|
||||
|
||||
ex_handler_done:
|
||||
lwi r5, r1, 0 /* RMSR */
|
||||
mts rmsr, r5
|
||||
nop
|
||||
lwi r3, r1, PT_R3
|
||||
lwi r4, r1, PT_R4
|
||||
lwi r5, r1, PT_R5
|
||||
lwi r6, r1, PT_R6
|
||||
lwi r17, r1, PT_R17
|
||||
|
||||
rted r17, 0
|
||||
addik r1, r1, (EX_HANDLER_STACK_SIZ); /* Restore stack frame */
|
||||
|
||||
.end _hw_exception_handler
|
||||
|
||||
ex_handler_unhandled:
|
||||
/* FIXME add handle function for unhandled exception - dump register */
|
||||
bri 0
|
||||
|
||||
.section .text
|
||||
.align 4
|
||||
lw_table:
|
||||
lw_r0: R3_TO_LWREG (0);
|
||||
lw_r1: LWREG_NOP;
|
||||
lw_r2: R3_TO_LWREG (2);
|
||||
lw_r3: R3_TO_LWREG_V (3);
|
||||
lw_r4: R3_TO_LWREG_V (4);
|
||||
lw_r5: R3_TO_LWREG_V (5);
|
||||
lw_r6: R3_TO_LWREG_V (6);
|
||||
lw_r7: R3_TO_LWREG (7);
|
||||
lw_r8: R3_TO_LWREG (8);
|
||||
lw_r9: R3_TO_LWREG (9);
|
||||
lw_r10: R3_TO_LWREG (10);
|
||||
lw_r11: R3_TO_LWREG (11);
|
||||
lw_r12: R3_TO_LWREG (12);
|
||||
lw_r13: R3_TO_LWREG (13);
|
||||
lw_r14: R3_TO_LWREG (14);
|
||||
lw_r15: R3_TO_LWREG (15);
|
||||
lw_r16: R3_TO_LWREG (16);
|
||||
lw_r17: LWREG_NOP;
|
||||
lw_r18: R3_TO_LWREG (18);
|
||||
lw_r19: R3_TO_LWREG (19);
|
||||
lw_r20: R3_TO_LWREG (20);
|
||||
lw_r21: R3_TO_LWREG (21);
|
||||
lw_r22: R3_TO_LWREG (22);
|
||||
lw_r23: R3_TO_LWREG (23);
|
||||
lw_r24: R3_TO_LWREG (24);
|
||||
lw_r25: R3_TO_LWREG (25);
|
||||
lw_r26: R3_TO_LWREG (26);
|
||||
lw_r27: R3_TO_LWREG (27);
|
||||
lw_r28: R3_TO_LWREG (28);
|
||||
lw_r29: R3_TO_LWREG (29);
|
||||
lw_r30: R3_TO_LWREG (30);
|
||||
lw_r31: R3_TO_LWREG (31);
|
||||
|
||||
sw_table:
|
||||
sw_r0: SWREG_TO_R3 (0);
|
||||
sw_r1: SWREG_NOP;
|
||||
sw_r2: SWREG_TO_R3 (2);
|
||||
sw_r3: SWREG_TO_R3_V (3);
|
||||
sw_r4: SWREG_TO_R3_V (4);
|
||||
sw_r5: SWREG_TO_R3_V (5);
|
||||
sw_r6: SWREG_TO_R3_V (6);
|
||||
sw_r7: SWREG_TO_R3 (7);
|
||||
sw_r8: SWREG_TO_R3 (8);
|
||||
sw_r9: SWREG_TO_R3 (9);
|
||||
sw_r10: SWREG_TO_R3 (10);
|
||||
sw_r11: SWREG_TO_R3 (11);
|
||||
sw_r12: SWREG_TO_R3 (12);
|
||||
sw_r13: SWREG_TO_R3 (13);
|
||||
sw_r14: SWREG_TO_R3 (14);
|
||||
sw_r15: SWREG_TO_R3 (15);
|
||||
sw_r16: SWREG_TO_R3 (16);
|
||||
sw_r17: SWREG_NOP;
|
||||
sw_r18: SWREG_TO_R3 (18);
|
||||
sw_r19: SWREG_TO_R3 (19);
|
||||
sw_r20: SWREG_TO_R3 (20);
|
||||
sw_r21: SWREG_TO_R3 (21);
|
||||
sw_r22: SWREG_TO_R3 (22);
|
||||
sw_r23: SWREG_TO_R3 (23);
|
||||
sw_r24: SWREG_TO_R3 (24);
|
||||
sw_r25: SWREG_TO_R3 (25);
|
||||
sw_r26: SWREG_TO_R3 (26);
|
||||
sw_r27: SWREG_TO_R3 (27);
|
||||
sw_r28: SWREG_TO_R3 (28);
|
||||
sw_r29: SWREG_TO_R3 (29);
|
||||
sw_r30: SWREG_TO_R3 (30);
|
||||
sw_r31: SWREG_TO_R3 (31);
|
||||
|
||||
/* Temporary data structures used in the handler */
|
||||
.section .data
|
||||
.align 4
|
||||
ex_tmp_data_loc_0:
|
||||
.byte 0
|
||||
ex_tmp_data_loc_1:
|
||||
.byte 0
|
||||
ex_tmp_data_loc_2:
|
||||
.byte 0
|
||||
ex_tmp_data_loc_3:
|
||||
.byte 0
|
||||
ex_reg_op:
|
||||
.byte 0
|
||||
Loading…
Reference in New Issue