mirror of https://gitee.com/openkylin/linux.git
Ux500 pinctrl changes:
- Updates to MSP pinctrl entry for ALSA SoC - ABx500 pinctrl tables -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (GNU/Linux) iQIcBAABAgAGBQJRrc0vAAoJEEEQszewGV1zbRIQAKJvj3tfzvlMpGBxL9cLpSPO H+0ZYtRjBFd3mHwAuuz1uzuzbFj2pziOKT2vszDOpN7CkYZRQSoXcBfWM342+QFR j8wcwpJw+5x8G612eg9/KOBNnPkVt+RNNmMORDt2coG0Gs8mUWNNh5Pu83f2rpxb YpQrplA59c0H02Pfos09e7eDahCJ+sazpDfhwXPrXVZHU9DI+JcPiixnSzMijq0U qOlUEjtzcfac2pJCeeI655z/4dqI5nL5QTr8MRkpt2wdLT3kDgbs/H8Aqke11hlI XkJ4Zc2HrtAN0AIoWp+e1nFsqcbXjnolVm14TNNh3bRg/UAEpuD+MwmWv75IeOmF YixkFQ1ru4zGIe0lB8KHjip794xBa9xeJ1+NcW5o8yvIWZZqr7snfn2i7OKsa24i qWRr4PUWD5aeY9CK3hRh9vFiWNeo9FtJjNH5ylwncN63UthXGSbR2AP2qQUERke0 JIRzyhT5qo2n6b1pLXtcaxJAAMSy/kJxu/O90LqVHT9rUiXUIydCLG5XiS2luVFh 7QR3kr0wes3Swe07g6BZ3LtNtRrhVvTB5GxUj2BeEdnUr+84gyuWo6vvV3VFRw0a dSq9HFRyc3H9XV0c7CXjpM4XniJIexctfYbAPWzt7XCfwMbPSFSqfh3LOxWUGsWf icX8Bv7zV0FkwvDqRZKy =ZyLV -----END PGP SIGNATURE----- Merge tag 'ux500-pinctrl-for-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into next/boards From Linus Walleij: Ux500 pinctrl changes: - Updates to MSP pinctrl entry for ALSA SoC - ABx500 pinctrl tables * tag 'ux500-pinctrl-for-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson: ARM: ux500: add ABx500 pinctrl tables ARM: ux500: update MSP1 pinctrl defintions Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
c4e6be1bc8
|
|
@ -9,6 +9,7 @@
|
|||
#include <linux/bug.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
#include <linux/pinctrl/pinconf-generic.h>
|
||||
#include <linux/platform_data/pinctrl-nomadik.h>
|
||||
|
||||
#include <asm/mach-types.h>
|
||||
|
|
@ -34,6 +35,11 @@ BIAS(in_pd, PIN_INPUT_PULLDOWN);
|
|||
BIAS(out_hi, PIN_OUTPUT_HIGH);
|
||||
BIAS(out_lo, PIN_OUTPUT_LOW);
|
||||
BIAS(out_lo_slpm_nowkup, PIN_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE);
|
||||
|
||||
BIAS(abx500_out_lo, PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0));
|
||||
BIAS(abx500_in_pd, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 1));
|
||||
BIAS(abx500_in_nopull, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 0));
|
||||
|
||||
/* These also force them into GPIO mode */
|
||||
BIAS(gpio_in_pu, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED);
|
||||
BIAS(gpio_in_pd, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED);
|
||||
|
|
@ -97,6 +103,252 @@ BIAS(out_wkup_pdis, PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE|
|
|||
#define DB8500_PIN_STATE(pin, conf, dev, state) \
|
||||
PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-db8500", pin, conf)
|
||||
|
||||
#define AB8500_MUX_HOG(group, func) \
|
||||
PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-ab8500.0", group, func)
|
||||
#define AB8500_PIN_HOG(pin, conf) \
|
||||
PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-ab8500.0", pin, abx500_##conf)
|
||||
|
||||
#define AB8500_MUX_STATE(group, func, dev, state) \
|
||||
PIN_MAP_MUX_GROUP(dev, state, "pinctrl-ab8500.0", group, func)
|
||||
#define AB8500_PIN_STATE(pin, conf, dev, state) \
|
||||
PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-ab8500.0", pin, abx500_##conf)
|
||||
|
||||
#define AB8505_MUX_HOG(group, func) \
|
||||
PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-ab8505.0", group, func)
|
||||
#define AB8505_PIN_HOG(pin, conf) \
|
||||
PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-ab8505.0", pin, abx500_##conf)
|
||||
|
||||
#define AB8505_MUX_STATE(group, func, dev, state) \
|
||||
PIN_MAP_MUX_GROUP(dev, state, "pinctrl-ab8505.0", group, func)
|
||||
#define AB8505_PIN_STATE(pin, conf, dev, state) \
|
||||
PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-ab8505.0", pin, abx500_##conf)
|
||||
|
||||
static struct pinctrl_map __initdata ab8500_pinmap[] = {
|
||||
/* Sysclkreq2 */
|
||||
AB8500_MUX_STATE("sysclkreq2_d_1", "sysclkreq", "regulator.35", PINCTRL_STATE_DEFAULT),
|
||||
AB8500_PIN_STATE("GPIO1_T10", in_nopull, "regulator.35", PINCTRL_STATE_DEFAULT),
|
||||
/* sysclkreq2 disable, mux in gpio configured in input pulldown */
|
||||
AB8500_MUX_STATE("gpio1_a_1", "gpio", "regulator.35", PINCTRL_STATE_SLEEP),
|
||||
AB8500_PIN_STATE("GPIO1_T10", in_pd, "regulator.35", PINCTRL_STATE_SLEEP),
|
||||
|
||||
/* pins 2 is muxed in GPIO, configured in INPUT PULL DOWN */
|
||||
AB8500_MUX_HOG("gpio2_a_1", "gpio"),
|
||||
AB8500_PIN_HOG("GPIO2_T9", in_pd),
|
||||
|
||||
/* Sysclkreq4 */
|
||||
AB8500_MUX_STATE("sysclkreq4_d_1", "sysclkreq", "regulator.36", PINCTRL_STATE_DEFAULT),
|
||||
AB8500_PIN_STATE("GPIO3_U9", in_nopull, "regulator.36", PINCTRL_STATE_DEFAULT),
|
||||
/* sysclkreq4 disable, mux in gpio configured in input pulldown */
|
||||
AB8500_MUX_STATE("gpio3_a_1", "gpio", "regulator.36", PINCTRL_STATE_SLEEP),
|
||||
AB8500_PIN_STATE("GPIO3_U9", in_pd, "regulator.36", PINCTRL_STATE_SLEEP),
|
||||
|
||||
/* pins 4 is muxed in GPIO, configured in INPUT PULL DOWN */
|
||||
AB8500_MUX_HOG("gpio4_a_1", "gpio"),
|
||||
AB8500_PIN_HOG("GPIO4_W2", in_pd),
|
||||
|
||||
/*
|
||||
* pins 6,7,8 and 9 are muxed in YCBCR0123
|
||||
* configured in INPUT PULL UP
|
||||
*/
|
||||
AB8500_MUX_HOG("ycbcr0123_d_1", "ycbcr"),
|
||||
AB8500_PIN_HOG("GPIO6_Y18", in_nopull),
|
||||
AB8500_PIN_HOG("GPIO7_AA20", in_nopull),
|
||||
AB8500_PIN_HOG("GPIO8_W18", in_nopull),
|
||||
AB8500_PIN_HOG("GPIO9_AA19", in_nopull),
|
||||
|
||||
/*
|
||||
* pins 10,11,12 and 13 are muxed in GPIO
|
||||
* configured in INPUT PULL DOWN
|
||||
*/
|
||||
AB8500_MUX_HOG("gpio10_d_1", "gpio"),
|
||||
AB8500_PIN_HOG("GPIO10_U17", in_pd),
|
||||
|
||||
AB8500_MUX_HOG("gpio11_d_1", "gpio"),
|
||||
AB8500_PIN_HOG("GPIO11_AA18", in_pd),
|
||||
|
||||
AB8500_MUX_HOG("gpio12_d_1", "gpio"),
|
||||
AB8500_PIN_HOG("GPIO12_U16", in_pd),
|
||||
|
||||
AB8500_MUX_HOG("gpio13_d_1", "gpio"),
|
||||
AB8500_PIN_HOG("GPIO13_W17", in_pd),
|
||||
|
||||
/*
|
||||
* pins 14,15 are muxed in PWM1 and PWM2
|
||||
* configured in INPUT PULL DOWN
|
||||
*/
|
||||
AB8500_MUX_HOG("pwmout1_d_1", "pwmout"),
|
||||
AB8500_PIN_HOG("GPIO14_F14", in_pd),
|
||||
|
||||
AB8500_MUX_HOG("pwmout2_d_1", "pwmout"),
|
||||
AB8500_PIN_HOG("GPIO15_B17", in_pd),
|
||||
|
||||
/*
|
||||
* pins 16 is muxed in GPIO
|
||||
* configured in INPUT PULL DOWN
|
||||
*/
|
||||
AB8500_MUX_HOG("gpio16_a_1", "gpio"),
|
||||
AB8500_PIN_HOG("GPIO14_F14", in_pd),
|
||||
|
||||
/*
|
||||
* pins 17,18,19 and 20 are muxed in AUDIO interface 1
|
||||
* configured in INPUT PULL DOWN
|
||||
*/
|
||||
AB8500_MUX_HOG("adi1_d_1", "adi1"),
|
||||
AB8500_PIN_HOG("GPIO17_P5", in_pd),
|
||||
AB8500_PIN_HOG("GPIO18_R5", in_pd),
|
||||
AB8500_PIN_HOG("GPIO19_U5", in_pd),
|
||||
AB8500_PIN_HOG("GPIO20_T5", in_pd),
|
||||
|
||||
/*
|
||||
* pins 21,22 and 23 are muxed in USB UICC
|
||||
* configured in INPUT PULL DOWN
|
||||
*/
|
||||
AB8500_MUX_HOG("usbuicc_d_1", "usbuicc"),
|
||||
AB8500_PIN_HOG("GPIO21_H19", in_pd),
|
||||
AB8500_PIN_HOG("GPIO22_G20", in_pd),
|
||||
AB8500_PIN_HOG("GPIO23_G19", in_pd),
|
||||
|
||||
/*
|
||||
* pins 24,25 are muxed in GPIO
|
||||
* configured in INPUT PULL DOWN
|
||||
*/
|
||||
AB8500_MUX_HOG("gpio24_a_1", "gpio"),
|
||||
AB8500_PIN_HOG("GPIO24_T14", in_pd),
|
||||
|
||||
AB8500_MUX_HOG("gpio25_a_1", "gpio"),
|
||||
AB8500_PIN_HOG("GPIO25_R16", in_pd),
|
||||
|
||||
/*
|
||||
* pins 26 is muxed in GPIO
|
||||
* configured in OUTPUT LOW
|
||||
*/
|
||||
AB8500_MUX_HOG("gpio26_d_1", "gpio"),
|
||||
AB8500_PIN_HOG("GPIO26_M16", out_lo),
|
||||
|
||||
/*
|
||||
* pins 27,28 are muxed in DMIC12
|
||||
* configured in INPUT PULL DOWN
|
||||
*/
|
||||
AB8500_MUX_HOG("dmic12_d_1", "dmic"),
|
||||
AB8500_PIN_HOG("GPIO27_J6", in_pd),
|
||||
AB8500_PIN_HOG("GPIO28_K6", in_pd),
|
||||
|
||||
/*
|
||||
* pins 29,30 are muxed in DMIC34
|
||||
* configured in INPUT PULL DOWN
|
||||
*/
|
||||
AB8500_MUX_HOG("dmic34_d_1", "dmic"),
|
||||
AB8500_PIN_HOG("GPIO29_G6", in_pd),
|
||||
AB8500_PIN_HOG("GPIO30_H6", in_pd),
|
||||
|
||||
/*
|
||||
* pins 31,32 are muxed in DMIC56
|
||||
* configured in INPUT PULL DOWN
|
||||
*/
|
||||
AB8500_MUX_HOG("dmic56_d_1", "dmic"),
|
||||
AB8500_PIN_HOG("GPIO31_F5", in_pd),
|
||||
AB8500_PIN_HOG("GPIO32_G5", in_pd),
|
||||
|
||||
/*
|
||||
* pins 34 is muxed in EXTCPENA
|
||||
* configured INPUT PULL DOWN
|
||||
*/
|
||||
AB8500_MUX_HOG("extcpena_d_1", "extcpena"),
|
||||
AB8500_PIN_HOG("GPIO34_R17", in_pd),
|
||||
|
||||
/*
|
||||
* pins 35 is muxed in GPIO
|
||||
* configured in OUTPUT LOW
|
||||
*/
|
||||
AB8500_MUX_HOG("gpio35_d_1", "gpio"),
|
||||
AB8500_PIN_HOG("GPIO35_W15", in_pd),
|
||||
|
||||
/*
|
||||
* pins 36,37,38 and 39 are muxed in GPIO
|
||||
* configured in INPUT PULL DOWN
|
||||
*/
|
||||
AB8500_MUX_HOG("gpio36_a_1", "gpio"),
|
||||
AB8500_PIN_HOG("GPIO36_A17", in_pd),
|
||||
|
||||
AB8500_MUX_HOG("gpio37_a_1", "gpio"),
|
||||
AB8500_PIN_HOG("GPIO37_E15", in_pd),
|
||||
|
||||
AB8500_MUX_HOG("gpio38_a_1", "gpio"),
|
||||
AB8500_PIN_HOG("GPIO38_C17", in_pd),
|
||||
|
||||
AB8500_MUX_HOG("gpio39_a_1", "gpio"),
|
||||
AB8500_PIN_HOG("GPIO39_E16", in_pd),
|
||||
|
||||
/*
|
||||
* pins 40 and 41 are muxed in MODCSLSDA
|
||||
* configured INPUT PULL DOWN
|
||||
*/
|
||||
AB8500_MUX_HOG("modsclsda_d_1", "modsclsda"),
|
||||
AB8500_PIN_HOG("GPIO40_T19", in_pd),
|
||||
AB8500_PIN_HOG("GPIO41_U19", in_pd),
|
||||
|
||||
/*
|
||||
* pins 42 is muxed in GPIO
|
||||
* configured INPUT PULL DOWN
|
||||
*/
|
||||
AB8500_MUX_HOG("gpio42_a_1", "gpio"),
|
||||
AB8500_PIN_HOG("GPIO42_U2", in_pd),
|
||||
};
|
||||
|
||||
static struct pinctrl_map __initdata ab8505_pinmap[] = {
|
||||
/* Sysclkreq2 */
|
||||
AB8505_MUX_STATE("sysclkreq2_d_1", "sysclkreq", "regulator.36", PINCTRL_STATE_DEFAULT),
|
||||
AB8505_PIN_STATE("GPIO1_N4", in_nopull, "regulator.36", PINCTRL_STATE_DEFAULT),
|
||||
/* sysclkreq2 disable, mux in gpio configured in input pulldown */
|
||||
AB8505_MUX_STATE("gpio1_a_1", "gpio", "regulator.36", PINCTRL_STATE_SLEEP),
|
||||
AB8505_PIN_STATE("GPIO1_N4", in_pd, "regulator.36", PINCTRL_STATE_SLEEP),
|
||||
|
||||
/* pins 2 is muxed in GPIO, configured in INPUT PULL DOWN */
|
||||
AB8505_MUX_HOG("gpio2_a_1", "gpio"),
|
||||
AB8505_PIN_HOG("GPIO2_R5", in_pd),
|
||||
|
||||
/* Sysclkreq4 */
|
||||
AB8505_MUX_STATE("sysclkreq4_d_1", "sysclkreq", "regulator.37", PINCTRL_STATE_DEFAULT),
|
||||
AB8505_PIN_STATE("GPIO3_P5", in_nopull, "regulator.37", PINCTRL_STATE_DEFAULT),
|
||||
/* sysclkreq4 disable, mux in gpio configured in input pulldown */
|
||||
AB8505_MUX_STATE("gpio3_a_1", "gpio", "regulator.37", PINCTRL_STATE_SLEEP),
|
||||
AB8505_PIN_STATE("GPIO3_P5", in_pd, "regulator.37", PINCTRL_STATE_SLEEP),
|
||||
|
||||
AB8505_MUX_HOG("gpio10_d_1", "gpio"),
|
||||
AB8505_PIN_HOG("GPIO10_B16", in_pd),
|
||||
|
||||
AB8505_MUX_HOG("gpio11_d_1", "gpio"),
|
||||
AB8505_PIN_HOG("GPIO11_B17", in_pd),
|
||||
|
||||
AB8505_MUX_HOG("gpio13_d_1", "gpio"),
|
||||
AB8505_PIN_HOG("GPIO13_D17", in_nopull),
|
||||
|
||||
AB8505_MUX_HOG("pwmout1_d_1", "pwmout"),
|
||||
AB8505_PIN_HOG("GPIO14_C16", in_pd),
|
||||
|
||||
AB8505_MUX_HOG("adi2_d_1", "adi2"),
|
||||
AB8505_PIN_HOG("GPIO17_P2", in_pd),
|
||||
AB8505_PIN_HOG("GPIO18_N3", in_pd),
|
||||
AB8505_PIN_HOG("GPIO19_T1", in_pd),
|
||||
AB8505_PIN_HOG("GPIO20_P3", in_pd),
|
||||
|
||||
AB8505_MUX_HOG("gpio34_a_1", "gpio"),
|
||||
AB8505_PIN_HOG("GPIO34_H14", in_pd),
|
||||
|
||||
AB8505_MUX_HOG("modsclsda_d_1", "modsclsda"),
|
||||
AB8505_PIN_HOG("GPIO40_J15", in_pd),
|
||||
AB8505_PIN_HOG("GPIO41_J14", in_pd),
|
||||
|
||||
AB8505_MUX_HOG("gpio50_d_1", "gpio"),
|
||||
AB8505_PIN_HOG("GPIO50_L4", in_nopull),
|
||||
|
||||
AB8505_MUX_HOG("resethw_d_1", "resethw"),
|
||||
AB8505_PIN_HOG("GPIO52_D16", in_pd),
|
||||
|
||||
AB8505_MUX_HOG("service_d_1", "service"),
|
||||
AB8505_PIN_HOG("GPIO53_D15", in_pd),
|
||||
};
|
||||
|
||||
/* Pin control settings */
|
||||
static struct pinctrl_map __initdata mop500_family_pinmap[] = {
|
||||
/*
|
||||
|
|
@ -174,17 +426,12 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = {
|
|||
DB8500_PIN_SLEEP("GPIO4_AH6", slpm_in_wkup_pdis, "uart1"),
|
||||
DB8500_PIN_SLEEP("GPIO5_AG6", slpm_out_wkup_pdis, "uart1"),
|
||||
/* MSP1 for ALSA codec */
|
||||
DB8500_MUX("msp1txrx_a_1", "msp1", "ux500-msp-i2s.1"),
|
||||
DB8500_MUX("msp1_a_1", "msp1", "ux500-msp-i2s.1"),
|
||||
DB8500_PIN("GPIO33_AF2", out_lo_slpm_nowkup, "ux500-msp-i2s.1"),
|
||||
DB8500_PIN("GPIO34_AE1", in_nopull_slpm_nowkup, "ux500-msp-i2s.1"),
|
||||
DB8500_PIN("GPIO35_AE2", in_nopull_slpm_nowkup, "ux500-msp-i2s.1"),
|
||||
DB8500_PIN("GPIO36_AG2", in_nopull_slpm_nowkup, "ux500-msp-i2s.1"),
|
||||
/* MSP1 sleep state */
|
||||
DB8500_PIN_SLEEP("GPIO33_AF2", slpm_out_lo_wkup, "ux500-msp-i2s.1"),
|
||||
DB8500_PIN_SLEEP("GPIO34_AE1", slpm_in_nopull_wkup, "ux500-msp-i2s.1"),
|
||||
DB8500_PIN_SLEEP("GPIO35_AE2", slpm_in_nopull_wkup, "ux500-msp-i2s.1"),
|
||||
DB8500_PIN_SLEEP("GPIO36_AG2", slpm_in_nopull_wkup, "ux500-msp-i2s.1"),
|
||||
DB8500_MUX_HOG("msp1txrx_a_1", "msp1"),
|
||||
DB8500_MUX_HOG("msp1_a_1", "msp1"),
|
||||
DB8500_PIN_HOG("GPIO33_AF2", out_lo_slpm_nowkup),
|
||||
DB8500_PIN_HOG("GPIO34_AE1", in_nopull_slpm_nowkup),
|
||||
DB8500_PIN_HOG("GPIO35_AE2", in_nopull_slpm_nowkup),
|
||||
DB8500_PIN_HOG("GPIO36_AG2", in_nopull_slpm_nowkup),
|
||||
/* Mux in LCD data lines 8 thru 11 and LCDA CLK for MCDE TVOUT */
|
||||
DB8500_MUX("lcd_d8_d11_a_1", "lcd", "mcde-tvout"),
|
||||
DB8500_MUX("lcdaclk_b_1", "lcda", "mcde-tvout"),
|
||||
|
|
@ -821,6 +1068,12 @@ void __init mop500_pinmaps_init(void)
|
|||
pinctrl_register_mappings(mop500_pinmap,
|
||||
ARRAY_SIZE(mop500_pinmap));
|
||||
mop500_href_family_pinmaps_init();
|
||||
if (machine_is_u8520())
|
||||
pinctrl_register_mappings(ab8505_pinmap,
|
||||
ARRAY_SIZE(ab8505_pinmap));
|
||||
else
|
||||
pinctrl_register_mappings(ab8500_pinmap,
|
||||
ARRAY_SIZE(ab8500_pinmap));
|
||||
}
|
||||
|
||||
void __init snowball_pinmaps_init(void)
|
||||
|
|
@ -831,6 +1084,8 @@ void __init snowball_pinmaps_init(void)
|
|||
ARRAY_SIZE(snowball_pinmap));
|
||||
pinctrl_register_mappings(u8500_pinmap,
|
||||
ARRAY_SIZE(u8500_pinmap));
|
||||
pinctrl_register_mappings(ab8500_pinmap,
|
||||
ARRAY_SIZE(ab8500_pinmap));
|
||||
}
|
||||
|
||||
void __init hrefv60_pinmaps_init(void)
|
||||
|
|
@ -840,4 +1095,6 @@ void __init hrefv60_pinmaps_init(void)
|
|||
pinctrl_register_mappings(hrefv60_pinmap,
|
||||
ARRAY_SIZE(hrefv60_pinmap));
|
||||
mop500_href_family_pinmaps_init();
|
||||
pinctrl_register_mappings(ab8500_pinmap,
|
||||
ARRAY_SIZE(ab8500_pinmap));
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue