mirror of https://gitee.com/openkylin/linux.git
rt2x00: rt2500pci: use the rt2x00mmio_* routines
Use the recently introduced rt2x00mmio_* routines instead of the rt2x00pci_* variants. The patch contains no functional changes. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Acked-by: Helmut Schaa <helmut.schaa@googlemail.com> Acked-by: Gertjan van Wingerde <gwingerde@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Gabor Juhos
John W. Linville
parent
172c5911a0
commit
c517123a0e
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@ -41,7 +41,7 @@
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/*
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* Register access.
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* All access to the CSR registers will go through the methods
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* rt2x00pci_register_read and rt2x00pci_register_write.
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* rt2x00mmio_register_read and rt2x00mmio_register_write.
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* BBP and RF register require indirect register access,
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* and use the CSR registers BBPCSR and RFCSR to achieve this.
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* These indirect registers work with busy bits,
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@ -52,9 +52,9 @@
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* and we will print an error.
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*/
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#define WAIT_FOR_BBP(__dev, __reg) \
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rt2x00pci_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
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rt2x00mmio_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
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#define WAIT_FOR_RF(__dev, __reg) \
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rt2x00pci_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
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rt2x00mmio_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
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static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev,
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const unsigned int word, const u8 value)
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@ -74,7 +74,7 @@ static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev,
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rt2x00_set_field32(®, BBPCSR_BUSY, 1);
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rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 1);
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rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
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rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg);
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}
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mutex_unlock(&rt2x00dev->csr_mutex);
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@ -101,7 +101,7 @@ static void rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev,
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rt2x00_set_field32(®, BBPCSR_BUSY, 1);
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rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 0);
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rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
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rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg);
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WAIT_FOR_BBP(rt2x00dev, ®);
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}
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@ -129,7 +129,7 @@ static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev,
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rt2x00_set_field32(®, RFCSR_IF_SELECT, 0);
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rt2x00_set_field32(®, RFCSR_BUSY, 1);
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rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
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rt2x00mmio_register_write(rt2x00dev, RFCSR, reg);
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rt2x00_rf_write(rt2x00dev, word, value);
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}
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@ -141,7 +141,7 @@ static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
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struct rt2x00_dev *rt2x00dev = eeprom->data;
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u32 reg;
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rt2x00pci_register_read(rt2x00dev, CSR21, ®);
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rt2x00mmio_register_read(rt2x00dev, CSR21, ®);
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eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
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eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
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@ -163,15 +163,15 @@ static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
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rt2x00_set_field32(®, CSR21_EEPROM_CHIP_SELECT,
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!!eeprom->reg_chip_select);
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rt2x00pci_register_write(rt2x00dev, CSR21, reg);
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rt2x00mmio_register_write(rt2x00dev, CSR21, reg);
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}
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#ifdef CONFIG_RT2X00_LIB_DEBUGFS
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static const struct rt2x00debug rt2500pci_rt2x00debug = {
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.owner = THIS_MODULE,
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.csr = {
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.read = rt2x00pci_register_read,
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.write = rt2x00pci_register_write,
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.read = rt2x00mmio_register_read,
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.write = rt2x00mmio_register_write,
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.flags = RT2X00DEBUGFS_OFFSET,
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.word_base = CSR_REG_BASE,
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.word_size = sizeof(u32),
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@ -205,7 +205,7 @@ static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
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{
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u32 reg;
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rt2x00pci_register_read(rt2x00dev, GPIOCSR, ®);
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rt2x00mmio_register_read(rt2x00dev, GPIOCSR, ®);
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return rt2x00_get_field32(reg, GPIOCSR_VAL0);
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}
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@ -218,14 +218,14 @@ static void rt2500pci_brightness_set(struct led_classdev *led_cdev,
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unsigned int enabled = brightness != LED_OFF;
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u32 reg;
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rt2x00pci_register_read(led->rt2x00dev, LEDCSR, ®);
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rt2x00mmio_register_read(led->rt2x00dev, LEDCSR, ®);
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if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
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rt2x00_set_field32(®, LEDCSR_LINK, enabled);
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else if (led->type == LED_TYPE_ACTIVITY)
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rt2x00_set_field32(®, LEDCSR_ACTIVITY, enabled);
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rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
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rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg);
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}
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static int rt2500pci_blink_set(struct led_classdev *led_cdev,
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@ -236,10 +236,10 @@ static int rt2500pci_blink_set(struct led_classdev *led_cdev,
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container_of(led_cdev, struct rt2x00_led, led_dev);
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u32 reg;
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rt2x00pci_register_read(led->rt2x00dev, LEDCSR, ®);
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rt2x00mmio_register_read(led->rt2x00dev, LEDCSR, ®);
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rt2x00_set_field32(®, LEDCSR_ON_PERIOD, *delay_on);
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rt2x00_set_field32(®, LEDCSR_OFF_PERIOD, *delay_off);
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rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
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rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg);
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return 0;
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}
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@ -270,7 +270,7 @@ static void rt2500pci_config_filter(struct rt2x00_dev *rt2x00dev,
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* and broadcast frames will always be accepted since
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* there is no filter for it at this time.
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*/
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rt2x00pci_register_read(rt2x00dev, RXCSR0, ®);
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rt2x00mmio_register_read(rt2x00dev, RXCSR0, ®);
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rt2x00_set_field32(®, RXCSR0_DROP_CRC,
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!(filter_flags & FIF_FCSFAIL));
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rt2x00_set_field32(®, RXCSR0_DROP_PHYSICAL,
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@ -286,7 +286,7 @@ static void rt2500pci_config_filter(struct rt2x00_dev *rt2x00dev,
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rt2x00_set_field32(®, RXCSR0_DROP_MCAST,
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!(filter_flags & FIF_ALLMULTI));
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rt2x00_set_field32(®, RXCSR0_DROP_BCAST, 0);
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rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
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rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
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}
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static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
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@ -303,25 +303,25 @@ static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
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* Enable beacon config
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*/
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bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
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rt2x00pci_register_read(rt2x00dev, BCNCSR1, ®);
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rt2x00mmio_register_read(rt2x00dev, BCNCSR1, ®);
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rt2x00_set_field32(®, BCNCSR1_PRELOAD, bcn_preload);
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rt2x00_set_field32(®, BCNCSR1_BEACON_CWMIN, queue->cw_min);
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rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
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rt2x00mmio_register_write(rt2x00dev, BCNCSR1, reg);
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/*
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* Enable synchronisation.
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*/
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rt2x00pci_register_read(rt2x00dev, CSR14, ®);
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rt2x00mmio_register_read(rt2x00dev, CSR14, ®);
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rt2x00_set_field32(®, CSR14_TSF_SYNC, conf->sync);
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rt2x00pci_register_write(rt2x00dev, CSR14, reg);
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rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
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}
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if (flags & CONFIG_UPDATE_MAC)
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rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
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rt2x00mmio_register_multiwrite(rt2x00dev, CSR3,
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conf->mac, sizeof(conf->mac));
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if (flags & CONFIG_UPDATE_BSSID)
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rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
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rt2x00mmio_register_multiwrite(rt2x00dev, CSR5,
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conf->bssid, sizeof(conf->bssid));
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}
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@ -338,68 +338,68 @@ static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev,
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if (changed & BSS_CHANGED_ERP_PREAMBLE) {
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preamble_mask = erp->short_preamble << 3;
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rt2x00pci_register_read(rt2x00dev, TXCSR1, ®);
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rt2x00mmio_register_read(rt2x00dev, TXCSR1, ®);
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rt2x00_set_field32(®, TXCSR1_ACK_TIMEOUT, 0x162);
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rt2x00_set_field32(®, TXCSR1_ACK_CONSUME_TIME, 0xa2);
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rt2x00_set_field32(®, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
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rt2x00_set_field32(®, TXCSR1_AUTORESPONDER, 1);
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rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
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rt2x00mmio_register_write(rt2x00dev, TXCSR1, reg);
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rt2x00pci_register_read(rt2x00dev, ARCSR2, ®);
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rt2x00mmio_register_read(rt2x00dev, ARCSR2, ®);
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rt2x00_set_field32(®, ARCSR2_SIGNAL, 0x00);
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rt2x00_set_field32(®, ARCSR2_SERVICE, 0x04);
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rt2x00_set_field32(®, ARCSR2_LENGTH,
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GET_DURATION(ACK_SIZE, 10));
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rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
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rt2x00mmio_register_write(rt2x00dev, ARCSR2, reg);
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rt2x00pci_register_read(rt2x00dev, ARCSR3, ®);
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rt2x00mmio_register_read(rt2x00dev, ARCSR3, ®);
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rt2x00_set_field32(®, ARCSR3_SIGNAL, 0x01 | preamble_mask);
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rt2x00_set_field32(®, ARCSR3_SERVICE, 0x04);
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rt2x00_set_field32(®, ARCSR2_LENGTH,
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GET_DURATION(ACK_SIZE, 20));
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rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
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rt2x00mmio_register_write(rt2x00dev, ARCSR3, reg);
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rt2x00pci_register_read(rt2x00dev, ARCSR4, ®);
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rt2x00mmio_register_read(rt2x00dev, ARCSR4, ®);
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rt2x00_set_field32(®, ARCSR4_SIGNAL, 0x02 | preamble_mask);
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rt2x00_set_field32(®, ARCSR4_SERVICE, 0x04);
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rt2x00_set_field32(®, ARCSR2_LENGTH,
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GET_DURATION(ACK_SIZE, 55));
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rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
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rt2x00mmio_register_write(rt2x00dev, ARCSR4, reg);
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rt2x00pci_register_read(rt2x00dev, ARCSR5, ®);
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rt2x00mmio_register_read(rt2x00dev, ARCSR5, ®);
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rt2x00_set_field32(®, ARCSR5_SIGNAL, 0x03 | preamble_mask);
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rt2x00_set_field32(®, ARCSR5_SERVICE, 0x84);
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rt2x00_set_field32(®, ARCSR2_LENGTH,
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GET_DURATION(ACK_SIZE, 110));
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rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
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rt2x00mmio_register_write(rt2x00dev, ARCSR5, reg);
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}
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if (changed & BSS_CHANGED_BASIC_RATES)
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rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
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rt2x00mmio_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
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if (changed & BSS_CHANGED_ERP_SLOT) {
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rt2x00pci_register_read(rt2x00dev, CSR11, ®);
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rt2x00mmio_register_read(rt2x00dev, CSR11, ®);
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rt2x00_set_field32(®, CSR11_SLOT_TIME, erp->slot_time);
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rt2x00pci_register_write(rt2x00dev, CSR11, reg);
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rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
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rt2x00pci_register_read(rt2x00dev, CSR18, ®);
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rt2x00mmio_register_read(rt2x00dev, CSR18, ®);
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rt2x00_set_field32(®, CSR18_SIFS, erp->sifs);
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rt2x00_set_field32(®, CSR18_PIFS, erp->pifs);
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rt2x00pci_register_write(rt2x00dev, CSR18, reg);
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rt2x00mmio_register_write(rt2x00dev, CSR18, reg);
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rt2x00pci_register_read(rt2x00dev, CSR19, ®);
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rt2x00mmio_register_read(rt2x00dev, CSR19, ®);
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rt2x00_set_field32(®, CSR19_DIFS, erp->difs);
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rt2x00_set_field32(®, CSR19_EIFS, erp->eifs);
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rt2x00pci_register_write(rt2x00dev, CSR19, reg);
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rt2x00mmio_register_write(rt2x00dev, CSR19, reg);
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}
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if (changed & BSS_CHANGED_BEACON_INT) {
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rt2x00pci_register_read(rt2x00dev, CSR12, ®);
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rt2x00mmio_register_read(rt2x00dev, CSR12, ®);
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rt2x00_set_field32(®, CSR12_BEACON_INTERVAL,
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erp->beacon_int * 16);
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rt2x00_set_field32(®, CSR12_CFP_MAX_DURATION,
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erp->beacon_int * 16);
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rt2x00pci_register_write(rt2x00dev, CSR12, reg);
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rt2x00mmio_register_write(rt2x00dev, CSR12, reg);
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}
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}
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@ -418,7 +418,7 @@ static void rt2500pci_config_ant(struct rt2x00_dev *rt2x00dev,
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BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
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ant->tx == ANTENNA_SW_DIVERSITY);
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rt2x00pci_register_read(rt2x00dev, BBPCSR1, ®);
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rt2x00mmio_register_read(rt2x00dev, BBPCSR1, ®);
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rt2500pci_bbp_read(rt2x00dev, 14, &r14);
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rt2500pci_bbp_read(rt2x00dev, 2, &r2);
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@ -470,7 +470,7 @@ static void rt2500pci_config_ant(struct rt2x00_dev *rt2x00dev,
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rt2x00_set_field32(®, BBPCSR1_OFDM_FLIP, 0);
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}
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rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg);
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rt2x00mmio_register_write(rt2x00dev, BBPCSR1, reg);
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rt2500pci_bbp_write(rt2x00dev, 14, r14);
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rt2500pci_bbp_write(rt2x00dev, 2, r2);
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}
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@ -541,7 +541,7 @@ static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
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/*
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* Clear false CRC during channel switch.
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*/
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rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
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rt2x00mmio_register_read(rt2x00dev, CNT0, &rf->rf1);
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}
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static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
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@ -559,12 +559,12 @@ static void rt2500pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
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{
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u32 reg;
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rt2x00pci_register_read(rt2x00dev, CSR11, ®);
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rt2x00mmio_register_read(rt2x00dev, CSR11, ®);
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rt2x00_set_field32(®, CSR11_LONG_RETRY,
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libconf->conf->long_frame_max_tx_count);
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rt2x00_set_field32(®, CSR11_SHORT_RETRY,
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libconf->conf->short_frame_max_tx_count);
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rt2x00pci_register_write(rt2x00dev, CSR11, reg);
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rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
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}
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static void rt2500pci_config_ps(struct rt2x00_dev *rt2x00dev,
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@ -576,7 +576,7 @@ static void rt2500pci_config_ps(struct rt2x00_dev *rt2x00dev,
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u32 reg;
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if (state == STATE_SLEEP) {
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rt2x00pci_register_read(rt2x00dev, CSR20, ®);
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rt2x00mmio_register_read(rt2x00dev, CSR20, ®);
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rt2x00_set_field32(®, CSR20_DELAY_AFTER_TBCN,
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(rt2x00dev->beacon_int - 20) * 16);
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rt2x00_set_field32(®, CSR20_TBCN_BEFORE_WAKEUP,
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@ -584,14 +584,14 @@ static void rt2500pci_config_ps(struct rt2x00_dev *rt2x00dev,
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/* We must first disable autowake before it can be enabled */
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rt2x00_set_field32(®, CSR20_AUTOWAKE, 0);
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rt2x00pci_register_write(rt2x00dev, CSR20, reg);
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rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
|
||||
|
||||
rt2x00_set_field32(®, CSR20_AUTOWAKE, 1);
|
||||
rt2x00pci_register_write(rt2x00dev, CSR20, reg);
|
||||
rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
|
||||
} else {
|
||||
rt2x00pci_register_read(rt2x00dev, CSR20, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, CSR20, ®);
|
||||
rt2x00_set_field32(®, CSR20_AUTOWAKE, 0);
|
||||
rt2x00pci_register_write(rt2x00dev, CSR20, reg);
|
||||
rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
|
||||
}
|
||||
|
||||
rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
|
||||
|
|
@ -625,13 +625,13 @@ static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev,
|
|||
/*
|
||||
* Update FCS error count from register.
|
||||
*/
|
||||
rt2x00pci_register_read(rt2x00dev, CNT0, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, CNT0, ®);
|
||||
qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
|
||||
|
||||
/*
|
||||
* Update False CCA count from register.
|
||||
*/
|
||||
rt2x00pci_register_read(rt2x00dev, CNT3, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, CNT3, ®);
|
||||
qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
|
||||
}
|
||||
|
||||
|
|
@ -731,16 +731,16 @@ static void rt2500pci_start_queue(struct data_queue *queue)
|
|||
|
||||
switch (queue->qid) {
|
||||
case QID_RX:
|
||||
rt2x00pci_register_read(rt2x00dev, RXCSR0, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, RXCSR0, ®);
|
||||
rt2x00_set_field32(®, RXCSR0_DISABLE_RX, 0);
|
||||
rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
|
||||
rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
|
||||
break;
|
||||
case QID_BEACON:
|
||||
rt2x00pci_register_read(rt2x00dev, CSR14, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, CSR14, ®);
|
||||
rt2x00_set_field32(®, CSR14_TSF_COUNT, 1);
|
||||
rt2x00_set_field32(®, CSR14_TBCN, 1);
|
||||
rt2x00_set_field32(®, CSR14_BEACON_GEN, 1);
|
||||
rt2x00pci_register_write(rt2x00dev, CSR14, reg);
|
||||
rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
|
|
@ -754,19 +754,19 @@ static void rt2500pci_kick_queue(struct data_queue *queue)
|
|||
|
||||
switch (queue->qid) {
|
||||
case QID_AC_VO:
|
||||
rt2x00pci_register_read(rt2x00dev, TXCSR0, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, TXCSR0, ®);
|
||||
rt2x00_set_field32(®, TXCSR0_KICK_PRIO, 1);
|
||||
rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
|
||||
rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
|
||||
break;
|
||||
case QID_AC_VI:
|
||||
rt2x00pci_register_read(rt2x00dev, TXCSR0, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, TXCSR0, ®);
|
||||
rt2x00_set_field32(®, TXCSR0_KICK_TX, 1);
|
||||
rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
|
||||
rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
|
||||
break;
|
||||
case QID_ATIM:
|
||||
rt2x00pci_register_read(rt2x00dev, TXCSR0, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, TXCSR0, ®);
|
||||
rt2x00_set_field32(®, TXCSR0_KICK_ATIM, 1);
|
||||
rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
|
||||
rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
|
|
@ -782,21 +782,21 @@ static void rt2500pci_stop_queue(struct data_queue *queue)
|
|||
case QID_AC_VO:
|
||||
case QID_AC_VI:
|
||||
case QID_ATIM:
|
||||
rt2x00pci_register_read(rt2x00dev, TXCSR0, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, TXCSR0, ®);
|
||||
rt2x00_set_field32(®, TXCSR0_ABORT, 1);
|
||||
rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
|
||||
rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
|
||||
break;
|
||||
case QID_RX:
|
||||
rt2x00pci_register_read(rt2x00dev, RXCSR0, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, RXCSR0, ®);
|
||||
rt2x00_set_field32(®, RXCSR0_DISABLE_RX, 1);
|
||||
rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
|
||||
rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
|
||||
break;
|
||||
case QID_BEACON:
|
||||
rt2x00pci_register_read(rt2x00dev, CSR14, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, CSR14, ®);
|
||||
rt2x00_set_field32(®, CSR14_TSF_COUNT, 0);
|
||||
rt2x00_set_field32(®, CSR14_TBCN, 0);
|
||||
rt2x00_set_field32(®, CSR14_BEACON_GEN, 0);
|
||||
rt2x00pci_register_write(rt2x00dev, CSR14, reg);
|
||||
rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
|
||||
|
||||
/*
|
||||
* Wait for possibly running tbtt tasklets.
|
||||
|
|
@ -813,7 +813,7 @@ static void rt2500pci_stop_queue(struct data_queue *queue)
|
|||
*/
|
||||
static bool rt2500pci_get_entry_state(struct queue_entry *entry)
|
||||
{
|
||||
struct queue_entry_priv_pci *entry_priv = entry->priv_data;
|
||||
struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
|
||||
u32 word;
|
||||
|
||||
if (entry->queue->qid == QID_RX) {
|
||||
|
|
@ -830,7 +830,7 @@ static bool rt2500pci_get_entry_state(struct queue_entry *entry)
|
|||
|
||||
static void rt2500pci_clear_entry(struct queue_entry *entry)
|
||||
{
|
||||
struct queue_entry_priv_pci *entry_priv = entry->priv_data;
|
||||
struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
|
||||
struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
|
||||
u32 word;
|
||||
|
||||
|
|
@ -852,53 +852,53 @@ static void rt2500pci_clear_entry(struct queue_entry *entry)
|
|||
|
||||
static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
|
||||
{
|
||||
struct queue_entry_priv_pci *entry_priv;
|
||||
struct queue_entry_priv_mmio *entry_priv;
|
||||
u32 reg;
|
||||
|
||||
/*
|
||||
* Initialize registers.
|
||||
*/
|
||||
rt2x00pci_register_read(rt2x00dev, TXCSR2, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, TXCSR2, ®);
|
||||
rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
|
||||
rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
|
||||
rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit);
|
||||
rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
|
||||
rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
|
||||
rt2x00mmio_register_write(rt2x00dev, TXCSR2, reg);
|
||||
|
||||
entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
|
||||
rt2x00pci_register_read(rt2x00dev, TXCSR3, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, TXCSR3, ®);
|
||||
rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER,
|
||||
entry_priv->desc_dma);
|
||||
rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
|
||||
rt2x00mmio_register_write(rt2x00dev, TXCSR3, reg);
|
||||
|
||||
entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
|
||||
rt2x00pci_register_read(rt2x00dev, TXCSR5, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, TXCSR5, ®);
|
||||
rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER,
|
||||
entry_priv->desc_dma);
|
||||
rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
|
||||
rt2x00mmio_register_write(rt2x00dev, TXCSR5, reg);
|
||||
|
||||
entry_priv = rt2x00dev->atim->entries[0].priv_data;
|
||||
rt2x00pci_register_read(rt2x00dev, TXCSR4, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, TXCSR4, ®);
|
||||
rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER,
|
||||
entry_priv->desc_dma);
|
||||
rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
|
||||
rt2x00mmio_register_write(rt2x00dev, TXCSR4, reg);
|
||||
|
||||
entry_priv = rt2x00dev->bcn->entries[0].priv_data;
|
||||
rt2x00pci_register_read(rt2x00dev, TXCSR6, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, TXCSR6, ®);
|
||||
rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER,
|
||||
entry_priv->desc_dma);
|
||||
rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
|
||||
rt2x00mmio_register_write(rt2x00dev, TXCSR6, reg);
|
||||
|
||||
rt2x00pci_register_read(rt2x00dev, RXCSR1, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, RXCSR1, ®);
|
||||
rt2x00_set_field32(®, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
|
||||
rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
|
||||
rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
|
||||
rt2x00mmio_register_write(rt2x00dev, RXCSR1, reg);
|
||||
|
||||
entry_priv = rt2x00dev->rx->entries[0].priv_data;
|
||||
rt2x00pci_register_read(rt2x00dev, RXCSR2, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, RXCSR2, ®);
|
||||
rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER,
|
||||
entry_priv->desc_dma);
|
||||
rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
|
||||
rt2x00mmio_register_write(rt2x00dev, RXCSR2, reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -907,30 +907,30 @@ static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
|
|||
{
|
||||
u32 reg;
|
||||
|
||||
rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
|
||||
rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
|
||||
rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
|
||||
rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
|
||||
rt2x00mmio_register_write(rt2x00dev, PSCSR0, 0x00020002);
|
||||
rt2x00mmio_register_write(rt2x00dev, PSCSR1, 0x00000002);
|
||||
rt2x00mmio_register_write(rt2x00dev, PSCSR2, 0x00020002);
|
||||
rt2x00mmio_register_write(rt2x00dev, PSCSR3, 0x00000002);
|
||||
|
||||
rt2x00pci_register_read(rt2x00dev, TIMECSR, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, TIMECSR, ®);
|
||||
rt2x00_set_field32(®, TIMECSR_US_COUNT, 33);
|
||||
rt2x00_set_field32(®, TIMECSR_US_64_COUNT, 63);
|
||||
rt2x00_set_field32(®, TIMECSR_BEACON_EXPECT, 0);
|
||||
rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
|
||||
rt2x00mmio_register_write(rt2x00dev, TIMECSR, reg);
|
||||
|
||||
rt2x00pci_register_read(rt2x00dev, CSR9, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, CSR9, ®);
|
||||
rt2x00_set_field32(®, CSR9_MAX_FRAME_UNIT,
|
||||
rt2x00dev->rx->data_size / 128);
|
||||
rt2x00pci_register_write(rt2x00dev, CSR9, reg);
|
||||
rt2x00mmio_register_write(rt2x00dev, CSR9, reg);
|
||||
|
||||
/*
|
||||
* Always use CWmin and CWmax set in descriptor.
|
||||
*/
|
||||
rt2x00pci_register_read(rt2x00dev, CSR11, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, CSR11, ®);
|
||||
rt2x00_set_field32(®, CSR11_CW_SELECT, 0);
|
||||
rt2x00pci_register_write(rt2x00dev, CSR11, reg);
|
||||
rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
|
||||
|
||||
rt2x00pci_register_read(rt2x00dev, CSR14, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, CSR14, ®);
|
||||
rt2x00_set_field32(®, CSR14_TSF_COUNT, 0);
|
||||
rt2x00_set_field32(®, CSR14_TSF_SYNC, 0);
|
||||
rt2x00_set_field32(®, CSR14_TBCN, 0);
|
||||
|
|
@ -939,11 +939,11 @@ static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
|
|||
rt2x00_set_field32(®, CSR14_BEACON_GEN, 0);
|
||||
rt2x00_set_field32(®, CSR14_CFP_COUNT_PRELOAD, 0);
|
||||
rt2x00_set_field32(®, CSR14_TBCM_PRELOAD, 0);
|
||||
rt2x00pci_register_write(rt2x00dev, CSR14, reg);
|
||||
rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
|
||||
|
||||
rt2x00pci_register_write(rt2x00dev, CNT3, 0);
|
||||
rt2x00mmio_register_write(rt2x00dev, CNT3, 0);
|
||||
|
||||
rt2x00pci_register_read(rt2x00dev, TXCSR8, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, TXCSR8, ®);
|
||||
rt2x00_set_field32(®, TXCSR8_BBP_ID0, 10);
|
||||
rt2x00_set_field32(®, TXCSR8_BBP_ID0_VALID, 1);
|
||||
rt2x00_set_field32(®, TXCSR8_BBP_ID1, 11);
|
||||
|
|
@ -952,30 +952,30 @@ static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
|
|||
rt2x00_set_field32(®, TXCSR8_BBP_ID2_VALID, 1);
|
||||
rt2x00_set_field32(®, TXCSR8_BBP_ID3, 12);
|
||||
rt2x00_set_field32(®, TXCSR8_BBP_ID3_VALID, 1);
|
||||
rt2x00pci_register_write(rt2x00dev, TXCSR8, reg);
|
||||
rt2x00mmio_register_write(rt2x00dev, TXCSR8, reg);
|
||||
|
||||
rt2x00pci_register_read(rt2x00dev, ARTCSR0, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, ARTCSR0, ®);
|
||||
rt2x00_set_field32(®, ARTCSR0_ACK_CTS_1MBS, 112);
|
||||
rt2x00_set_field32(®, ARTCSR0_ACK_CTS_2MBS, 56);
|
||||
rt2x00_set_field32(®, ARTCSR0_ACK_CTS_5_5MBS, 20);
|
||||
rt2x00_set_field32(®, ARTCSR0_ACK_CTS_11MBS, 10);
|
||||
rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg);
|
||||
rt2x00mmio_register_write(rt2x00dev, ARTCSR0, reg);
|
||||
|
||||
rt2x00pci_register_read(rt2x00dev, ARTCSR1, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, ARTCSR1, ®);
|
||||
rt2x00_set_field32(®, ARTCSR1_ACK_CTS_6MBS, 45);
|
||||
rt2x00_set_field32(®, ARTCSR1_ACK_CTS_9MBS, 37);
|
||||
rt2x00_set_field32(®, ARTCSR1_ACK_CTS_12MBS, 33);
|
||||
rt2x00_set_field32(®, ARTCSR1_ACK_CTS_18MBS, 29);
|
||||
rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg);
|
||||
rt2x00mmio_register_write(rt2x00dev, ARTCSR1, reg);
|
||||
|
||||
rt2x00pci_register_read(rt2x00dev, ARTCSR2, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, ARTCSR2, ®);
|
||||
rt2x00_set_field32(®, ARTCSR2_ACK_CTS_24MBS, 29);
|
||||
rt2x00_set_field32(®, ARTCSR2_ACK_CTS_36MBS, 25);
|
||||
rt2x00_set_field32(®, ARTCSR2_ACK_CTS_48MBS, 25);
|
||||
rt2x00_set_field32(®, ARTCSR2_ACK_CTS_54MBS, 25);
|
||||
rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg);
|
||||
rt2x00mmio_register_write(rt2x00dev, ARTCSR2, reg);
|
||||
|
||||
rt2x00pci_register_read(rt2x00dev, RXCSR3, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, RXCSR3, ®);
|
||||
rt2x00_set_field32(®, RXCSR3_BBP_ID0, 47); /* CCK Signal */
|
||||
rt2x00_set_field32(®, RXCSR3_BBP_ID0_VALID, 1);
|
||||
rt2x00_set_field32(®, RXCSR3_BBP_ID1, 51); /* Rssi */
|
||||
|
|
@ -984,9 +984,9 @@ static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
|
|||
rt2x00_set_field32(®, RXCSR3_BBP_ID2_VALID, 1);
|
||||
rt2x00_set_field32(®, RXCSR3_BBP_ID3, 51); /* RSSI */
|
||||
rt2x00_set_field32(®, RXCSR3_BBP_ID3_VALID, 1);
|
||||
rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
|
||||
rt2x00mmio_register_write(rt2x00dev, RXCSR3, reg);
|
||||
|
||||
rt2x00pci_register_read(rt2x00dev, PCICSR, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, PCICSR, ®);
|
||||
rt2x00_set_field32(®, PCICSR_BIG_ENDIAN, 0);
|
||||
rt2x00_set_field32(®, PCICSR_RX_TRESHOLD, 0);
|
||||
rt2x00_set_field32(®, PCICSR_TX_TRESHOLD, 3);
|
||||
|
|
@ -994,54 +994,54 @@ static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
|
|||
rt2x00_set_field32(®, PCICSR_ENABLE_CLK, 1);
|
||||
rt2x00_set_field32(®, PCICSR_READ_MULTIPLE, 1);
|
||||
rt2x00_set_field32(®, PCICSR_WRITE_INVALID, 1);
|
||||
rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
|
||||
rt2x00mmio_register_write(rt2x00dev, PCICSR, reg);
|
||||
|
||||
rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
|
||||
rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
|
||||
|
||||
rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
|
||||
rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
|
||||
rt2x00mmio_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
|
||||
rt2x00mmio_register_write(rt2x00dev, TESTCSR, 0x000000f0);
|
||||
|
||||
if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
|
||||
return -EBUSY;
|
||||
|
||||
rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
|
||||
rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
|
||||
rt2x00mmio_register_write(rt2x00dev, MACCSR0, 0x00213223);
|
||||
rt2x00mmio_register_write(rt2x00dev, MACCSR1, 0x00235518);
|
||||
|
||||
rt2x00pci_register_read(rt2x00dev, MACCSR2, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, MACCSR2, ®);
|
||||
rt2x00_set_field32(®, MACCSR2_DELAY, 64);
|
||||
rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
|
||||
rt2x00mmio_register_write(rt2x00dev, MACCSR2, reg);
|
||||
|
||||
rt2x00pci_register_read(rt2x00dev, RALINKCSR, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, RALINKCSR, ®);
|
||||
rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA0, 17);
|
||||
rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID0, 26);
|
||||
rt2x00_set_field32(®, RALINKCSR_AR_BBP_VALID0, 1);
|
||||
rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA1, 0);
|
||||
rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID1, 26);
|
||||
rt2x00_set_field32(®, RALINKCSR_AR_BBP_VALID1, 1);
|
||||
rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
|
||||
rt2x00mmio_register_write(rt2x00dev, RALINKCSR, reg);
|
||||
|
||||
rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200);
|
||||
rt2x00mmio_register_write(rt2x00dev, BBPCSR1, 0x82188200);
|
||||
|
||||
rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
|
||||
rt2x00mmio_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
|
||||
|
||||
rt2x00pci_register_read(rt2x00dev, CSR1, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, CSR1, ®);
|
||||
rt2x00_set_field32(®, CSR1_SOFT_RESET, 1);
|
||||
rt2x00_set_field32(®, CSR1_BBP_RESET, 0);
|
||||
rt2x00_set_field32(®, CSR1_HOST_READY, 0);
|
||||
rt2x00pci_register_write(rt2x00dev, CSR1, reg);
|
||||
rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
|
||||
|
||||
rt2x00pci_register_read(rt2x00dev, CSR1, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, CSR1, ®);
|
||||
rt2x00_set_field32(®, CSR1_SOFT_RESET, 0);
|
||||
rt2x00_set_field32(®, CSR1_HOST_READY, 1);
|
||||
rt2x00pci_register_write(rt2x00dev, CSR1, reg);
|
||||
rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
|
||||
|
||||
/*
|
||||
* We must clear the FCS and FIFO error count.
|
||||
* These registers are cleared on read,
|
||||
* so we may pass a useless variable to store the value.
|
||||
*/
|
||||
rt2x00pci_register_read(rt2x00dev, CNT0, ®);
|
||||
rt2x00pci_register_read(rt2x00dev, CNT4, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, CNT0, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, CNT4, ®);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1131,8 +1131,8 @@ static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
|
|||
* should clear the register to assure a clean state.
|
||||
*/
|
||||
if (state == STATE_RADIO_IRQ_ON) {
|
||||
rt2x00pci_register_read(rt2x00dev, CSR7, ®);
|
||||
rt2x00pci_register_write(rt2x00dev, CSR7, reg);
|
||||
rt2x00mmio_register_read(rt2x00dev, CSR7, ®);
|
||||
rt2x00mmio_register_write(rt2x00dev, CSR7, reg);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -1141,13 +1141,13 @@ static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
|
|||
*/
|
||||
spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
|
||||
|
||||
rt2x00pci_register_read(rt2x00dev, CSR8, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, CSR8, ®);
|
||||
rt2x00_set_field32(®, CSR8_TBCN_EXPIRE, mask);
|
||||
rt2x00_set_field32(®, CSR8_TXDONE_TXRING, mask);
|
||||
rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, mask);
|
||||
rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, mask);
|
||||
rt2x00_set_field32(®, CSR8_RXDONE, mask);
|
||||
rt2x00pci_register_write(rt2x00dev, CSR8, reg);
|
||||
rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
|
||||
|
||||
spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
|
||||
|
||||
|
|
@ -1179,7 +1179,7 @@ static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
|
|||
/*
|
||||
* Disable power
|
||||
*/
|
||||
rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
|
||||
rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0);
|
||||
}
|
||||
|
||||
static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
|
||||
|
|
@ -1193,12 +1193,12 @@ static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
|
|||
|
||||
put_to_sleep = (state != STATE_AWAKE);
|
||||
|
||||
rt2x00pci_register_read(rt2x00dev, PWRCSR1, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, PWRCSR1, ®);
|
||||
rt2x00_set_field32(®, PWRCSR1_SET_STATE, 1);
|
||||
rt2x00_set_field32(®, PWRCSR1_BBP_DESIRE_STATE, state);
|
||||
rt2x00_set_field32(®, PWRCSR1_RF_DESIRE_STATE, state);
|
||||
rt2x00_set_field32(®, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
|
||||
rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
|
||||
rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg);
|
||||
|
||||
/*
|
||||
* Device is not guaranteed to be in the requested state yet.
|
||||
|
|
@ -1206,12 +1206,12 @@ static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
|
|||
* device has entered the correct state.
|
||||
*/
|
||||
for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
|
||||
rt2x00pci_register_read(rt2x00dev, PWRCSR1, ®2);
|
||||
rt2x00mmio_register_read(rt2x00dev, PWRCSR1, ®2);
|
||||
bbp_state = rt2x00_get_field32(reg2, PWRCSR1_BBP_CURR_STATE);
|
||||
rf_state = rt2x00_get_field32(reg2, PWRCSR1_RF_CURR_STATE);
|
||||
if (bbp_state == state && rf_state == state)
|
||||
return 0;
|
||||
rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
|
||||
rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg);
|
||||
msleep(10);
|
||||
}
|
||||
|
||||
|
|
@ -1259,7 +1259,7 @@ static void rt2500pci_write_tx_desc(struct queue_entry *entry,
|
|||
struct txentry_desc *txdesc)
|
||||
{
|
||||
struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
|
||||
struct queue_entry_priv_pci *entry_priv = entry->priv_data;
|
||||
struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
|
||||
__le32 *txd = entry_priv->desc;
|
||||
u32 word;
|
||||
|
||||
|
|
@ -1335,9 +1335,9 @@ static void rt2500pci_write_beacon(struct queue_entry *entry,
|
|||
* Disable beaconing while we are reloading the beacon data,
|
||||
* otherwise we might be sending out invalid data.
|
||||
*/
|
||||
rt2x00pci_register_read(rt2x00dev, CSR14, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, CSR14, ®);
|
||||
rt2x00_set_field32(®, CSR14_BEACON_GEN, 0);
|
||||
rt2x00pci_register_write(rt2x00dev, CSR14, reg);
|
||||
rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
|
||||
|
||||
if (rt2x00queue_map_txskb(entry)) {
|
||||
ERROR(rt2x00dev, "Fail to map beacon, aborting\n");
|
||||
|
|
@ -1358,7 +1358,7 @@ static void rt2500pci_write_beacon(struct queue_entry *entry,
|
|||
* Enable beaconing again.
|
||||
*/
|
||||
rt2x00_set_field32(®, CSR14_BEACON_GEN, 1);
|
||||
rt2x00pci_register_write(rt2x00dev, CSR14, reg);
|
||||
rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -1367,7 +1367,7 @@ static void rt2500pci_write_beacon(struct queue_entry *entry,
|
|||
static void rt2500pci_fill_rxdone(struct queue_entry *entry,
|
||||
struct rxdone_entry_desc *rxdesc)
|
||||
{
|
||||
struct queue_entry_priv_pci *entry_priv = entry->priv_data;
|
||||
struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
|
||||
u32 word0;
|
||||
u32 word2;
|
||||
|
||||
|
|
@ -1405,7 +1405,7 @@ static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
|
|||
const enum data_queue_qid queue_idx)
|
||||
{
|
||||
struct data_queue *queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
|
||||
struct queue_entry_priv_pci *entry_priv;
|
||||
struct queue_entry_priv_mmio *entry_priv;
|
||||
struct queue_entry *entry;
|
||||
struct txdone_entry_desc txdesc;
|
||||
u32 word;
|
||||
|
|
@ -1451,9 +1451,9 @@ static inline void rt2500pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
|
|||
*/
|
||||
spin_lock_irq(&rt2x00dev->irqmask_lock);
|
||||
|
||||
rt2x00pci_register_read(rt2x00dev, CSR8, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, CSR8, ®);
|
||||
rt2x00_set_field32(®, irq_field, 0);
|
||||
rt2x00pci_register_write(rt2x00dev, CSR8, reg);
|
||||
rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
|
||||
|
||||
spin_unlock_irq(&rt2x00dev->irqmask_lock);
|
||||
}
|
||||
|
|
@ -1476,11 +1476,11 @@ static void rt2500pci_txstatus_tasklet(unsigned long data)
|
|||
if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) {
|
||||
spin_lock_irq(&rt2x00dev->irqmask_lock);
|
||||
|
||||
rt2x00pci_register_read(rt2x00dev, CSR8, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, CSR8, ®);
|
||||
rt2x00_set_field32(®, CSR8_TXDONE_TXRING, 0);
|
||||
rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, 0);
|
||||
rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, 0);
|
||||
rt2x00pci_register_write(rt2x00dev, CSR8, reg);
|
||||
rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
|
||||
|
||||
spin_unlock_irq(&rt2x00dev->irqmask_lock);
|
||||
}
|
||||
|
|
@ -1497,7 +1497,7 @@ static void rt2500pci_tbtt_tasklet(unsigned long data)
|
|||
static void rt2500pci_rxdone_tasklet(unsigned long data)
|
||||
{
|
||||
struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
|
||||
if (rt2x00pci_rxdone(rt2x00dev))
|
||||
if (rt2x00mmio_rxdone(rt2x00dev))
|
||||
tasklet_schedule(&rt2x00dev->rxdone_tasklet);
|
||||
else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
|
||||
rt2500pci_enable_interrupt(rt2x00dev, CSR8_RXDONE);
|
||||
|
|
@ -1512,8 +1512,8 @@ static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
|
|||
* Get the interrupt sources & saved to local variable.
|
||||
* Write register value back to clear pending interrupts.
|
||||
*/
|
||||
rt2x00pci_register_read(rt2x00dev, CSR7, ®);
|
||||
rt2x00pci_register_write(rt2x00dev, CSR7, reg);
|
||||
rt2x00mmio_register_read(rt2x00dev, CSR7, ®);
|
||||
rt2x00mmio_register_write(rt2x00dev, CSR7, reg);
|
||||
|
||||
if (!reg)
|
||||
return IRQ_NONE;
|
||||
|
|
@ -1550,9 +1550,9 @@ static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
|
|||
*/
|
||||
spin_lock(&rt2x00dev->irqmask_lock);
|
||||
|
||||
rt2x00pci_register_read(rt2x00dev, CSR8, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, CSR8, ®);
|
||||
reg |= mask;
|
||||
rt2x00pci_register_write(rt2x00dev, CSR8, reg);
|
||||
rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
|
||||
|
||||
spin_unlock(&rt2x00dev->irqmask_lock);
|
||||
|
||||
|
|
@ -1569,7 +1569,7 @@ static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
|
|||
u16 word;
|
||||
u8 *mac;
|
||||
|
||||
rt2x00pci_register_read(rt2x00dev, CSR21, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, CSR21, ®);
|
||||
|
||||
eeprom.data = rt2x00dev;
|
||||
eeprom.register_read = rt2500pci_eepromregister_read;
|
||||
|
|
@ -1644,7 +1644,7 @@ static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
|
|||
* Identify RF chipset.
|
||||
*/
|
||||
value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
|
||||
rt2x00pci_register_read(rt2x00dev, CSR0, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, CSR0, ®);
|
||||
rt2x00_set_chip(rt2x00dev, RT2560, value,
|
||||
rt2x00_get_field32(reg, CSR0_REVISION));
|
||||
|
||||
|
|
@ -1950,9 +1950,9 @@ static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
|
|||
* Enable rfkill polling by setting GPIO direction of the
|
||||
* rfkill switch GPIO pin correctly.
|
||||
*/
|
||||
rt2x00pci_register_read(rt2x00dev, GPIOCSR, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, GPIOCSR, ®);
|
||||
rt2x00_set_field32(®, GPIOCSR_DIR0, 1);
|
||||
rt2x00pci_register_write(rt2x00dev, GPIOCSR, reg);
|
||||
rt2x00mmio_register_write(rt2x00dev, GPIOCSR, reg);
|
||||
|
||||
/*
|
||||
* Initialize hw specifications.
|
||||
|
|
@ -1986,9 +1986,9 @@ static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw,
|
|||
u64 tsf;
|
||||
u32 reg;
|
||||
|
||||
rt2x00pci_register_read(rt2x00dev, CSR17, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, CSR17, ®);
|
||||
tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
|
||||
rt2x00pci_register_read(rt2x00dev, CSR16, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, CSR16, ®);
|
||||
tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
|
||||
|
||||
return tsf;
|
||||
|
|
@ -1999,7 +1999,7 @@ static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
|
|||
struct rt2x00_dev *rt2x00dev = hw->priv;
|
||||
u32 reg;
|
||||
|
||||
rt2x00pci_register_read(rt2x00dev, CSR15, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, CSR15, ®);
|
||||
return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
|
||||
}
|
||||
|
||||
|
|
@ -2032,8 +2032,8 @@ static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
|
|||
.tbtt_tasklet = rt2500pci_tbtt_tasklet,
|
||||
.rxdone_tasklet = rt2500pci_rxdone_tasklet,
|
||||
.probe_hw = rt2500pci_probe_hw,
|
||||
.initialize = rt2x00pci_initialize,
|
||||
.uninitialize = rt2x00pci_uninitialize,
|
||||
.initialize = rt2x00mmio_initialize,
|
||||
.uninitialize = rt2x00mmio_uninitialize,
|
||||
.get_entry_state = rt2500pci_get_entry_state,
|
||||
.clear_entry = rt2500pci_clear_entry,
|
||||
.set_device_state = rt2500pci_set_device_state,
|
||||
|
|
@ -2044,7 +2044,7 @@ static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
|
|||
.start_queue = rt2500pci_start_queue,
|
||||
.kick_queue = rt2500pci_kick_queue,
|
||||
.stop_queue = rt2500pci_stop_queue,
|
||||
.flush_queue = rt2x00pci_flush_queue,
|
||||
.flush_queue = rt2x00mmio_flush_queue,
|
||||
.write_tx_desc = rt2500pci_write_tx_desc,
|
||||
.write_beacon = rt2500pci_write_beacon,
|
||||
.fill_rxdone = rt2500pci_fill_rxdone,
|
||||
|
|
@ -2059,28 +2059,28 @@ static const struct data_queue_desc rt2500pci_queue_rx = {
|
|||
.entry_num = 32,
|
||||
.data_size = DATA_FRAME_SIZE,
|
||||
.desc_size = RXD_DESC_SIZE,
|
||||
.priv_size = sizeof(struct queue_entry_priv_pci),
|
||||
.priv_size = sizeof(struct queue_entry_priv_mmio),
|
||||
};
|
||||
|
||||
static const struct data_queue_desc rt2500pci_queue_tx = {
|
||||
.entry_num = 32,
|
||||
.data_size = DATA_FRAME_SIZE,
|
||||
.desc_size = TXD_DESC_SIZE,
|
||||
.priv_size = sizeof(struct queue_entry_priv_pci),
|
||||
.priv_size = sizeof(struct queue_entry_priv_mmio),
|
||||
};
|
||||
|
||||
static const struct data_queue_desc rt2500pci_queue_bcn = {
|
||||
.entry_num = 1,
|
||||
.data_size = MGMT_FRAME_SIZE,
|
||||
.desc_size = TXD_DESC_SIZE,
|
||||
.priv_size = sizeof(struct queue_entry_priv_pci),
|
||||
.priv_size = sizeof(struct queue_entry_priv_mmio),
|
||||
};
|
||||
|
||||
static const struct data_queue_desc rt2500pci_queue_atim = {
|
||||
.entry_num = 8,
|
||||
.data_size = DATA_FRAME_SIZE,
|
||||
.desc_size = TXD_DESC_SIZE,
|
||||
.priv_size = sizeof(struct queue_entry_priv_pci),
|
||||
.priv_size = sizeof(struct queue_entry_priv_mmio),
|
||||
};
|
||||
|
||||
static const struct rt2x00_ops rt2500pci_ops = {
|
||||
|
|
|
|||
Loading…
Reference in New Issue