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Merge branch 'remotes/lorenzo/pci/pci-bridge-emul' 

- Fix conflicts in pci-bridge-emul descriptions of Device Status and Slot
    Control (Jon Derrick)

  - Add emulation for more Device Status, Link Control, and Slot Control
    bits (Jon Derrick)

  - Improve emulation of reserved bits (Jon Derrick)

* remotes/lorenzo/pci/pci-bridge-emul:
  PCI: pci-bridge-emul: Eliminate the 'reserved' member
  PCI: pci-bridge-emul: Update for PCIe 5.0 r1.0
  PCI: pci-bridge-emul: Fix Root Cap/Status comment
  PCI: pci-bridge-emul: Fix PCIe bit conflicts
This commit is contained in:
Bjorn Helgaas 2020-06-04 12:59:18 -05:00
parent 210d8ea82a 1446978d56
commit c521b7d5b8
1 changed files with 31 additions and 30 deletions
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61
drivers/pci/pci-bridge-emul.c
View File

@ -24,6 +24,17 @@
#define PCI_CAP_PCIE_START PCI_BRIDGE_CONF_END
#define PCI_CAP_PCIE_END (PCI_CAP_PCIE_START + PCI_EXP_SLTSTA2 + 2)
/**
* struct pci_bridge_reg_behavior - register bits behaviors
* @ro: Read-Only bits
* @rw: Read-Write bits
* @w1c: Write-1-to-Clear bits
*
* Reads and Writes will be filtered by specified behavior. All other bits not
* declared are assumed 'Reserved' and will return 0 on reads, per PCIe 5.0:
* "Reserved register fields must be read only and must return 0 (all 0's for
* multi-bit fields) when read".
*/
struct pci_bridge_reg_behavior {
/* Read-only bits */
u32 ro;
@ -33,9 +44,6 @@ struct pci_bridge_reg_behavior {
/* Write-1-to-clear bits */
u32 w1c;
/* Reserved bits (hardwired to 0) */
u32 rsvd;
};
static const struct pci_bridge_reg_behavior pci_regs_behavior[] = {
@ -49,7 +57,6 @@ static const struct pci_bridge_reg_behavior pci_regs_behavior[] = {
PCI_COMMAND_FAST_BACK) |
(PCI_STATUS_CAP_LIST | PCI_STATUS_66MHZ |
PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MASK) << 16),
.rsvd = GENMASK(15, 10) | ((BIT(6) | GENMASK(3, 0)) << 16),
.w1c = PCI_STATUS_ERROR_BITS << 16,
},
[PCI_CLASS_REVISION / 4] = { .ro = ~0 },
@ -96,8 +103,6 @@ static const struct pci_bridge_reg_behavior pci_regs_behavior[] = {
GENMASK(11, 8) | GENMASK(3, 0)),
.w1c = PCI_STATUS_ERROR_BITS << 16,
.rsvd = ((BIT(6) | GENMASK(4, 0)) << 16),
},
[PCI_MEMORY_BASE / 4] = {
@ -130,12 +135,10 @@ static const struct pci_bridge_reg_behavior pci_regs_behavior[] = {
[PCI_CAPABILITY_LIST / 4] = {
.ro = GENMASK(7, 0),
.rsvd = GENMASK(31, 8),
},
[PCI_ROM_ADDRESS1 / 4] = {
.rw = GENMASK(31, 11) | BIT(0),
.rsvd = GENMASK(10, 1),
},
/*
@ -158,8 +161,6 @@ static const struct pci_bridge_reg_behavior pci_regs_behavior[] = {
.ro = (GENMASK(15, 8) | ((PCI_BRIDGE_CTL_FAST_BACK) << 16)),
.w1c = BIT(10) << 16,
.rsvd = (GENMASK(15, 12) | BIT(4)) << 16,
},
};
@ -181,31 +182,29 @@ static const struct pci_bridge_reg_behavior pcie_cap_regs_behavior[] = {
.rw = GENMASK(15, 0),
/*
* Device status register has 4 bits W1C, then 2 bits
* RO, the rest is reserved
* Device status register has bits 6 and [3:0] W1C, [5:4] RO,
* the rest is reserved
*/
.w1c = GENMASK(19, 16),
.ro = GENMASK(20, 19),
.rsvd = GENMASK(31, 21),
.w1c = (BIT(6) | GENMASK(3, 0)) << 16,
.ro = GENMASK(5, 4) << 16,
},
[PCI_EXP_LNKCAP / 4] = {
/* All bits are RO, except bit 23 which is reserved */
.ro = lower_32_bits(~BIT(23)),
.rsvd = BIT(23),
},
[PCI_EXP_LNKCTL / 4] = {
/*
* Link control has bits [1:0] and [11:3] RW, the
* other bits are reserved.
* Link status has bits [13:0] RO, and bits [14:15]
* Link control has bits [15:14], [11:3] and [1:0] RW, the
* rest is reserved.
*
* Link status has bits [13:0] RO, and bits [15:14]
* W1C.
*/
.rw = GENMASK(11, 3) | GENMASK(1, 0),
.rw = GENMASK(15, 14) | GENMASK(11, 3) | GENMASK(1, 0),
.ro = GENMASK(13, 0) << 16,
.w1c = GENMASK(15, 14) << 16,
.rsvd = GENMASK(15, 12) | BIT(2),
},
[PCI_EXP_SLTCAP / 4] = {
@ -214,19 +213,18 @@ static const struct pci_bridge_reg_behavior pcie_cap_regs_behavior[] = {
[PCI_EXP_SLTCTL / 4] = {
/*
* Slot control has bits [12:0] RW, the rest is
* Slot control has bits [14:0] RW, the rest is
* reserved.
*
* Slot status has a mix of W1C and RO bits, as well
* as reserved bits.
* Slot status has bits 8 and [4:0] W1C, bits [7:5] RO, the
* rest is reserved.
*/
.rw = GENMASK(12, 0),
.rw = GENMASK(14, 0),
.w1c = (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC) << 16,
.ro = (PCI_EXP_SLTSTA_MRLSS | PCI_EXP_SLTSTA_PDS |
PCI_EXP_SLTSTA_EIS) << 16,
.rsvd = GENMASK(15, 12) | (GENMASK(15, 9) << 16),
},
[PCI_EXP_RTCTL / 4] = {
@ -234,19 +232,21 @@ static const struct pci_bridge_reg_behavior pcie_cap_regs_behavior[] = {
* Root control has bits [4:0] RW, the rest is
* reserved.
*
* Root status has bit 0 RO, the rest is reserved.
* Root capabilities has bit 0 RO, the rest is reserved.
*/
.rw = (PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE |
PCI_EXP_RTCTL_SEFEE | PCI_EXP_RTCTL_PMEIE |
PCI_EXP_RTCTL_CRSSVE),
.ro = PCI_EXP_RTCAP_CRSVIS << 16,
.rsvd = GENMASK(15, 5) | (GENMASK(15, 1) << 16),
},
[PCI_EXP_RTSTA / 4] = {
/*
* Root status has bits 17 and [15:0] RO, bit 16 W1C, the rest
* is reserved.
*/
.ro = GENMASK(15, 0) | PCI_EXP_RTSTA_PENDING,
.w1c = PCI_EXP_RTSTA_PME,
.rsvd = GENMASK(31, 18),
},
};
@ -354,7 +354,8 @@ int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where,
* Make sure we never return any reserved bit with a value
* different from 0.
*/
*value &= ~behavior[reg / 4].rsvd;
*value &= behavior[reg / 4].ro | behavior[reg / 4].rw |
behavior[reg / 4].w1c;
if (size == 1)
*value = (*value >> (8 * (where & 3))) & 0xff;