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ARM: sun8i: Add reset controller nodes to the DTSI 

The A23 has the same MMIO reset controllers matching the clocks gates,
just like in the A31. This patch adds the reset controller nodes and
the reset control phandles for the peripherals needing them to the
DTSI.

Unlike the sun6i DTSI, this patch uses sun6i-a31-clock-reset for
ahb1_rst. sun6i-a31-ahb-reset is for early init, and requires some
additions to the machine code. It is used to support the hstimer.
However the hstimer on sun8i only has 1 timer, which is somewhat
useless. Support for it will probably not be added. Hence the
decision to use sun6i-a31-clock-reset here to avoid the changes to
sun8i machine code.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This commit is contained in:
Chen-Yu Tsai 2014-07-03 22:55:49 +08:00 committed by Maxime Ripard
parent 8e9842406c
commit c571111ac1
1 changed files with 23 additions and 0 deletions
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23
arch/arm/boot/dts/sun8i-a23.dtsi
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@ -187,6 +187,24 @@ soc@01c00000 {
#size-cells = <1>; #size-cells = <1>;
ranges; ranges;
ahb1_rst: reset@01c202c0 {
#reset-cells = <1>;
compatible = "allwinner,sun6i-a31-clock-reset";
reg = <0x01c202c0 0xc>;
};
apb1_rst: reset@01c202d0 {
#reset-cells = <1>;
compatible = "allwinner,sun6i-a31-clock-reset";
reg = <0x01c202d0 0x4>;
};
apb2_rst: reset@01c202d8 {
#reset-cells = <1>;
compatible = "allwinner,sun6i-a31-clock-reset";
reg = <0x01c202d8 0x4>;
};
timer@01c20c00 { timer@01c20c00 {
compatible = "allwinner,sun4i-a10-timer"; compatible = "allwinner,sun4i-a10-timer";
reg = <0x01c20c00 0xa0>; reg = <0x01c20c00 0xa0>;
@ -208,6 +226,7 @@ uart0: serial@01c28000 {
reg-shift = <2>; reg-shift = <2>;
reg-io-width = <4>; reg-io-width = <4>;
clocks = <&apb2_gates 16>; clocks = <&apb2_gates 16>;
resets = <&apb2_rst 16>;
status = "disabled"; status = "disabled";
}; };
@ -218,6 +237,7 @@ uart1: serial@01c28400 {
reg-shift = <2>; reg-shift = <2>;
reg-io-width = <4>; reg-io-width = <4>;
clocks = <&apb2_gates 17>; clocks = <&apb2_gates 17>;
resets = <&apb2_rst 17>;
status = "disabled"; status = "disabled";
}; };
@ -228,6 +248,7 @@ uart2: serial@01c28800 {
reg-shift = <2>; reg-shift = <2>;
reg-io-width = <4>; reg-io-width = <4>;
clocks = <&apb2_gates 18>; clocks = <&apb2_gates 18>;
resets = <&apb2_rst 18>;
status = "disabled"; status = "disabled";
}; };
@ -238,6 +259,7 @@ uart3: serial@01c28c00 {
reg-shift = <2>; reg-shift = <2>;
reg-io-width = <4>; reg-io-width = <4>;
clocks = <&apb2_gates 19>; clocks = <&apb2_gates 19>;
resets = <&apb2_rst 19>;
status = "disabled"; status = "disabled";
}; };
@ -248,6 +270,7 @@ uart4: serial@01c29000 {
reg-shift = <2>; reg-shift = <2>;
reg-io-width = <4>; reg-io-width = <4>;
clocks = <&apb2_gates 20>; clocks = <&apb2_gates 20>;
resets = <&apb2_rst 20>;
status = "disabled"; status = "disabled";
}; };