mirror of https://gitee.com/openkylin/linux.git
ARM: S5P64X0: Add SPI clkdev support
Registered the SPI bus clocks with clkdev using generic connection id. Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
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02717bb9aa
commit
c596704f73
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@ -267,18 +267,6 @@ static struct clk init_clocks_off[] = {
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.parent = &clk_pclk.clk,
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.enable = s5p64x0_pclk_ctrl,
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.ctrlbit = (1 << 31),
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}, {
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.name = "sclk_spi_48",
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.devname = "s3c64xx-spi.0",
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.parent = &clk_48m,
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.enable = s5p64x0_sclk_ctrl,
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.ctrlbit = (1 << 22),
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}, {
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.name = "sclk_spi_48",
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.devname = "s3c64xx-spi.1",
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.parent = &clk_48m,
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.enable = s5p64x0_sclk_ctrl,
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.ctrlbit = (1 << 23),
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}, {
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.name = "mmc_48m",
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.devname = "s3c-sdhci.0",
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@ -419,26 +407,6 @@ static struct clksrc_clk clksrcs[] = {
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.sources = &clkset_group1,
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.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
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.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_spi",
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.devname = "s3c64xx-spi.0",
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.ctrlbit = (1 << 20),
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.enable = s5p64x0_sclk_ctrl,
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},
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.sources = &clkset_group1,
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.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
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.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_spi",
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.devname = "s3c64xx-spi.1",
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.ctrlbit = (1 << 21),
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.enable = s5p64x0_sclk_ctrl,
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},
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.sources = &clkset_group1,
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.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
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.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_post",
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@ -489,6 +457,30 @@ static struct clksrc_clk clk_sclk_uclk = {
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.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
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};
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static struct clksrc_clk clk_sclk_spi0 = {
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.clk = {
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.name = "sclk_spi",
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.devname = "s3c64xx-spi.0",
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.ctrlbit = (1 << 20),
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.enable = s5p64x0_sclk_ctrl,
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},
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.sources = &clkset_group1,
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.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
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.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
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};
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static struct clksrc_clk clk_sclk_spi1 = {
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.clk = {
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.name = "sclk_spi",
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.devname = "s3c64xx-spi.1",
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.ctrlbit = (1 << 21),
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.enable = s5p64x0_sclk_ctrl,
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},
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.sources = &clkset_group1,
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.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
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.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
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};
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/* Clock initialization code */
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static struct clksrc_clk *sysclks[] = {
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&clk_mout_apll,
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@ -509,11 +501,16 @@ static struct clk dummy_apb_pclk = {
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static struct clksrc_clk *clksrc_cdev[] = {
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&clk_sclk_uclk,
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&clk_sclk_spi0,
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&clk_sclk_spi1,
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};
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static struct clk_lookup s5p6440_clk_lookup[] = {
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CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
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CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
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CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
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CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
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CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
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};
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void __init_or_cpufreq s5p6440_setup_clocks(void)
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@ -441,26 +441,6 @@ static struct clksrc_clk clksrcs[] = {
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.sources = &clkset_group2,
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.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
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.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_spi",
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.devname = "s3c64xx-spi.0",
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.ctrlbit = (1 << 20),
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.enable = s5p64x0_sclk_ctrl,
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},
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.sources = &clkset_group2,
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.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
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.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_spi",
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.devname = "s3c64xx-spi.1",
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.ctrlbit = (1 << 21),
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.enable = s5p64x0_sclk_ctrl,
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},
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.sources = &clkset_group2,
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.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
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.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_fimc",
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@ -538,13 +518,42 @@ static struct clksrc_clk clk_sclk_uclk = {
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.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
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};
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static struct clksrc_clk clk_sclk_spi0 = {
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.clk = {
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.name = "sclk_spi",
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.devname = "s3c64xx-spi.0",
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.ctrlbit = (1 << 20),
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.enable = s5p64x0_sclk_ctrl,
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},
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.sources = &clkset_group2,
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.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
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.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
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};
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static struct clksrc_clk clk_sclk_spi1 = {
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.clk = {
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.name = "sclk_spi",
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.devname = "s3c64xx-spi.1",
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.ctrlbit = (1 << 21),
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.enable = s5p64x0_sclk_ctrl,
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},
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.sources = &clkset_group2,
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.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
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.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
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};
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static struct clksrc_clk *clksrc_cdev[] = {
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&clk_sclk_uclk,
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&clk_sclk_spi0,
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&clk_sclk_spi1,
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};
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static struct clk_lookup s5p6450_clk_lookup[] = {
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CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
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CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
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CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
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CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
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CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
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};
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/* Clock initialization code */
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