mirror of https://gitee.com/openkylin/linux.git
x86, mce: clean up p4.c
Make the coding style match that of the rest of the x86 arch code. [ Impact: cleanup ] Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
This commit is contained in:
Ingo Molnar
H. Peter Anvin
parent
3b58dfd04b
commit
c5aaf0e070
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@ -2,18 +2,17 @@
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* P4 specific Machine Check Exception Reporting
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*/
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <asm/therm_throt.h>
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#include <asm/processor.h>
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#include <asm/system.h>
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#include <asm/msr.h>
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#include <asm/apic.h>
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#include <asm/therm_throt.h>
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#include <asm/msr.h>
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#include "mce.h"
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@ -36,6 +35,7 @@ static int mce_num_extended_msrs;
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#ifdef CONFIG_X86_MCE_P4THERMAL
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static void unexpected_thermal_interrupt(struct pt_regs *regs)
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{
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printk(KERN_ERR "CPU%d: Unexpected LVT TMR interrupt!\n",
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@ -43,7 +43,7 @@ static void unexpected_thermal_interrupt(struct pt_regs *regs)
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add_taint(TAINT_MACHINE_CHECK);
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}
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/* P4/Xeon Thermal transition interrupt handler */
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/* P4/Xeon Thermal transition interrupt handler: */
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static void intel_thermal_interrupt(struct pt_regs *regs)
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{
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__u64 msr_val;
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@ -54,8 +54,9 @@ static void intel_thermal_interrupt(struct pt_regs *regs)
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therm_throt_process(msr_val & 0x1);
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}
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/* Thermal interrupt handler for this CPU setup */
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static void (*vendor_thermal_interrupt)(struct pt_regs *regs) = unexpected_thermal_interrupt;
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/* Thermal interrupt handler for this CPU setup: */
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static void (*vendor_thermal_interrupt)(struct pt_regs *regs) =
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unexpected_thermal_interrupt;
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void smp_thermal_interrupt(struct pt_regs *regs)
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{
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@ -65,67 +66,76 @@ void smp_thermal_interrupt(struct pt_regs *regs)
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irq_exit();
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}
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/* P4/Xeon Thermal regulation detect and init */
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/* P4/Xeon Thermal regulation detect and init: */
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static void intel_init_thermal(struct cpuinfo_x86 *c)
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{
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u32 l, h;
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unsigned int cpu = smp_processor_id();
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u32 l, h;
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/* Thermal monitoring */
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/* Thermal monitoring: */
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if (!cpu_has(c, X86_FEATURE_ACPI))
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return; /* -ENODEV */
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/* Clock modulation */
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/* Clock modulation: */
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if (!cpu_has(c, X86_FEATURE_ACC))
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return; /* -ENODEV */
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/* first check if its enabled already, in which case there might
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/*
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* First check if its enabled already, in which case there might
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* be some SMM goo which handles it, so we can't even put a handler
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* since it might be delivered via SMI already -zwanem.
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* since it might be delivered via SMI already:
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*/
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rdmsr(MSR_IA32_MISC_ENABLE, l, h);
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h = apic_read(APIC_LVTTHMR);
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if ((l & MSR_IA32_MISC_ENABLE_TM1) && (h & APIC_DM_SMI)) {
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printk(KERN_DEBUG "CPU%d: Thermal monitoring handled by SMI\n",
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cpu);
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printk(KERN_DEBUG
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"CPU%d: Thermal monitoring handled by SMI\n", cpu);
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return; /* -EBUSY */
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}
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/* check whether a vector already exists, temporarily masked? */
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/* Check whether a vector already exists, temporarily masked? */
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if (h & APIC_VECTOR_MASK) {
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printk(KERN_DEBUG "CPU%d: Thermal LVT vector (%#x) already "
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"installed\n",
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cpu, (h & APIC_VECTOR_MASK));
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printk(KERN_DEBUG
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"CPU%d: Thermal LVT vector (%#x) already installed\n",
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cpu, (h & APIC_VECTOR_MASK));
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return; /* -EBUSY */
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}
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/* The temperature transition interrupt handler setup */
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h = THERMAL_APIC_VECTOR; /* our delivery vector */
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h |= (APIC_DM_FIXED | APIC_LVT_MASKED); /* we'll mask till we're ready */
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/*
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* The temperature transition interrupt handler setup:
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*/
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/* Our delivery vector: */
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h = THERMAL_APIC_VECTOR;
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/* We'll mask the thermal vector in the lapic till we're ready: */
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h |= APIC_DM_FIXED | APIC_LVT_MASKED;
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apic_write(APIC_LVTTHMR, h);
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rdmsr(MSR_IA32_THERM_INTERRUPT, l, h);
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wrmsr(MSR_IA32_THERM_INTERRUPT, l | 0x03 , h);
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/* ok we're good to go... */
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/* Ok, we're good to go... */
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vendor_thermal_interrupt = intel_thermal_interrupt;
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rdmsr(MSR_IA32_MISC_ENABLE, l, h);
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wrmsr(MSR_IA32_MISC_ENABLE, l | MSR_IA32_MISC_ENABLE_TM1, h);
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/* Unmask the thermal vector: */
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l = apic_read(APIC_LVTTHMR);
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apic_write(APIC_LVTTHMR, l & ~APIC_LVT_MASKED);
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printk(KERN_INFO "CPU%d: Thermal monitoring enabled\n", cpu);
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/* enable thermal throttle processing */
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atomic_set(&therm_throt_en, 1);
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return;
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}
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#endif /* CONFIG_X86_MCE_P4THERMAL */
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/* P4/Xeon Extended MCE MSR retrieval, return 0 if unsupported */
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static inline void intel_get_extended_msrs(struct intel_mce_extended_msrs *r)
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static void intel_get_extended_msrs(struct intel_mce_extended_msrs *r)
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{
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u32 h;
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@ -143,9 +153,9 @@ static inline void intel_get_extended_msrs(struct intel_mce_extended_msrs *r)
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static void intel_machine_check(struct pt_regs *regs, long error_code)
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{
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int recover = 1;
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u32 alow, ahigh, high, low;
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u32 mcgstl, mcgsth;
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int recover = 1;
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int i;
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rdmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
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@ -157,7 +167,9 @@ static void intel_machine_check(struct pt_regs *regs, long error_code)
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if (mce_num_extended_msrs > 0) {
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struct intel_mce_extended_msrs dbg;
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intel_get_extended_msrs(&dbg);
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printk(KERN_DEBUG "CPU %d: EIP: %08x EFLAGS: %08x\n"
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"\teax: %08x ebx: %08x ecx: %08x edx: %08x\n"
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"\tesi: %08x edi: %08x ebp: %08x esp: %08x\n",
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@ -171,6 +183,7 @@ static void intel_machine_check(struct pt_regs *regs, long error_code)
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if (high & (1<<31)) {
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char misc[20];
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char addr[24];
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misc[0] = addr[0] = '\0';
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if (high & (1<<29))
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recover |= 1;
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@ -196,6 +209,7 @@ static void intel_machine_check(struct pt_regs *regs, long error_code)
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panic("Unable to continue");
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printk(KERN_EMERG "Attempting to continue.\n");
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/*
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* Do not clear the MSR_IA32_MCi_STATUS if the error is not
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* recoverable/continuable.This will allow BIOS to look at the MSRs
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@ -217,7 +231,6 @@ static void intel_machine_check(struct pt_regs *regs, long error_code)
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wrmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
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}
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void intel_p4_mcheck_init(struct cpuinfo_x86 *c)
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{
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u32 l, h;
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