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drm/i915: Make sure PND deadline mode is enabled on VLV/CHV 

Poke at the CBR1_VLV register during init_clock_gating to make sure the
PND deadline scheme is used.

The hardware has two modes of operation wrt. watermarks:

1) PND deadline mode:
 - memory request deadline is calculated from actual FIFO level * DDL
 - WM1 watermark values are unused (AFAIK)
 - WM watermark level defines when to start fetching data from memory
   (assuming trickle feed is not used)

2) backup mode
 - deadline is based on FIFO status, DDL is unused
 - FIFO split into three regions with WM and WM1 watermarks, each
   part specifying a different FIFO status

We want to use the PND deadline mode, so let's make sure the chicken
bit is in the correct position on init.

Also take the opportunity to refactor the shared code between VLV and
CHV to a shared function.

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Ville Syrjälä 2015-03-05 21:19:48 +02:00 committed by Daniel Vetter
parent b500472026
commit c6beb13ef3
2 changed files with 16 additions and 6 deletions
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3
drivers/gpu/drm/i915/i915_reg.h
View File

@ -4216,6 +4216,9 @@ enum skl_disp_power_wells {
#define DDL_PRECISION_LOW (0<<7) #define DDL_PRECISION_LOW (0<<7)
#define DRAIN_LATENCY_MASK 0x7f #define DRAIN_LATENCY_MASK 0x7f
#define CBR1_VLV (VLV_DISPLAY_BASE + 0x70400)
#define CBR_PND_DEADLINE_DISABLE (1<<31)
/* FIFO watermark sizes etc */ /* FIFO watermark sizes etc */
#define G4X_FIFO_LINE_SIZE 64 #define G4X_FIFO_LINE_SIZE 64
#define I915_FIFO_LINE_SIZE 64 #define I915_FIFO_LINE_SIZE 64

19
drivers/gpu/drm/i915/intel_pm.c
View File

@ -6141,11 +6141,22 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
gen6_check_mch_setup(dev); gen6_check_mch_setup(dev);
} }
static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
{
I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
/*
* Disable trickle feed and enable pnd deadline calculation
*/
I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
I915_WRITE(CBR1_VLV, 0);
}
static void valleyview_init_clock_gating(struct drm_device *dev) static void valleyview_init_clock_gating(struct drm_device *dev)
{ {
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); vlv_init_display_clock_gating(dev_priv);
/* WaDisableEarlyCull:vlv */ /* WaDisableEarlyCull:vlv */
I915_WRITE(_3D_CHICKEN3, I915_WRITE(_3D_CHICKEN3,
@ -6193,8 +6204,6 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
I915_WRITE(GEN7_UCGCTL4, I915_WRITE(GEN7_UCGCTL4,
I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE); I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
/* /*
* BSpec says this must be set, even though * BSpec says this must be set, even though
* WaDisable4x2SubspanOptimization isn't listed for VLV. * WaDisable4x2SubspanOptimization isn't listed for VLV.
@ -6231,9 +6240,7 @@ static void cherryview_init_clock_gating(struct drm_device *dev)
{ {
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); vlv_init_display_clock_gating(dev_priv);
I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
/* WaVSRefCountFullforceMissDisable:chv */ /* WaVSRefCountFullforceMissDisable:chv */
/* WaDSRefCountFullforceMissDisable:chv */ /* WaDSRefCountFullforceMissDisable:chv */