mirror of https://gitee.com/openkylin/linux.git
drm/amdgpu:cleanup GMC & gart garbage function
for gart_ram_alloc/free, they are never used in driver thus ripe them out totally. for gart_vram_pin/unpin, they are not needed becuase we can use bo_creat_kernel/free to replace the original manual way in the gart_vram_alloc/free, thus gart_vram_pin/unpin can also be riped out. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
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11c6b82afb
commit
c79ee7d8c6
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@ -56,63 +56,6 @@
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* Common GART table functions.
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* Common GART table functions.
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*/
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*/
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/**
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* amdgpu_gart_table_ram_alloc - allocate system ram for gart page table
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*
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* @adev: amdgpu_device pointer
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*
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* Allocate system memory for GART page table
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* (r1xx-r3xx, non-pcie r4xx, rs400). These asics require the
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* gart table to be in system memory.
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* Returns 0 for success, -ENOMEM for failure.
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*/
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int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev)
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{
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void *ptr;
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ptr = pci_alloc_consistent(adev->pdev, adev->gart.table_size,
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&adev->gart.table_addr);
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if (ptr == NULL) {
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return -ENOMEM;
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}
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#ifdef CONFIG_X86
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if (0) {
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set_memory_uc((unsigned long)ptr,
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adev->gart.table_size >> PAGE_SHIFT);
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}
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#endif
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adev->gart.ptr = ptr;
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memset((void *)adev->gart.ptr, 0, adev->gart.table_size);
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return 0;
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}
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/**
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* amdgpu_gart_table_ram_free - free system ram for gart page table
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*
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* @adev: amdgpu_device pointer
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*
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* Free system memory for GART page table
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* (r1xx-r3xx, non-pcie r4xx, rs400). These asics require the
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* gart table to be in system memory.
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*/
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void amdgpu_gart_table_ram_free(struct amdgpu_device *adev)
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{
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if (adev->gart.ptr == NULL) {
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return;
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}
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#ifdef CONFIG_X86
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if (0) {
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set_memory_wb((unsigned long)adev->gart.ptr,
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adev->gart.table_size >> PAGE_SHIFT);
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}
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#endif
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pci_free_consistent(adev->pdev, adev->gart.table_size,
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(void *)adev->gart.ptr,
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adev->gart.table_addr);
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adev->gart.ptr = NULL;
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adev->gart.table_addr = 0;
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}
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/**
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/**
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* amdgpu_gart_table_vram_alloc - allocate vram for gart page table
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* amdgpu_gart_table_vram_alloc - allocate vram for gart page table
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*
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*
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@ -125,75 +68,9 @@ void amdgpu_gart_table_ram_free(struct amdgpu_device *adev)
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*/
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*/
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int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev)
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int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev)
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{
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{
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int r;
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return amdgpu_bo_create_kernel(adev, adev->gart.table_size, PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_VRAM, &adev->gart.robj,
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if (adev->gart.robj == NULL) {
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&adev->gart.table_addr, &adev->gart.ptr);
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r = amdgpu_bo_create(adev, adev->gart.table_size,
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PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM,
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AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
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AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
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NULL, NULL, 0, &adev->gart.robj);
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if (r) {
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return r;
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}
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}
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return 0;
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}
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/**
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* amdgpu_gart_table_vram_pin - pin gart page table in vram
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*
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* @adev: amdgpu_device pointer
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*
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* Pin the GART page table in vram so it will not be moved
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* by the memory manager (pcie r4xx, r5xx+). These asics require the
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* gart table to be in video memory.
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* Returns 0 for success, error for failure.
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*/
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int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev)
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{
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uint64_t gpu_addr;
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int r;
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r = amdgpu_bo_reserve(adev->gart.robj, false);
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if (unlikely(r != 0))
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return r;
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r = amdgpu_bo_pin(adev->gart.robj,
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AMDGPU_GEM_DOMAIN_VRAM, &gpu_addr);
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if (r) {
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amdgpu_bo_unreserve(adev->gart.robj);
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return r;
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}
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r = amdgpu_bo_kmap(adev->gart.robj, &adev->gart.ptr);
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if (r)
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amdgpu_bo_unpin(adev->gart.robj);
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amdgpu_bo_unreserve(adev->gart.robj);
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adev->gart.table_addr = gpu_addr;
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return r;
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}
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/**
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* amdgpu_gart_table_vram_unpin - unpin gart page table in vram
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*
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* @adev: amdgpu_device pointer
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*
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* Unpin the GART page table in vram (pcie r4xx, r5xx+).
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* These asics require the gart table to be in video memory.
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*/
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void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev)
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{
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int r;
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if (adev->gart.robj == NULL) {
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return;
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}
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r = amdgpu_bo_reserve(adev->gart.robj, true);
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if (likely(r == 0)) {
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amdgpu_bo_kunmap(adev->gart.robj);
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amdgpu_bo_unpin(adev->gart.robj);
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amdgpu_bo_unreserve(adev->gart.robj);
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adev->gart.ptr = NULL;
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}
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}
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}
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/**
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/**
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@ -207,10 +84,9 @@ void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev)
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*/
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*/
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void amdgpu_gart_table_vram_free(struct amdgpu_device *adev)
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void amdgpu_gart_table_vram_free(struct amdgpu_device *adev)
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{
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{
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if (adev->gart.robj == NULL) {
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amdgpu_bo_free_kernel(&adev->gart.robj,
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return;
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&adev->gart.table_addr,
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}
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&adev->gart.ptr);
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amdgpu_bo_unref(&adev->gart.robj);
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}
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}
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/*
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/*
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@ -56,12 +56,8 @@ struct amdgpu_gart {
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const struct amdgpu_gart_funcs *gart_funcs;
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const struct amdgpu_gart_funcs *gart_funcs;
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};
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};
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int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
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void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
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int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
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int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
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void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
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void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
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int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
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void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
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int amdgpu_gart_init(struct amdgpu_device *adev);
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int amdgpu_gart_init(struct amdgpu_device *adev);
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void amdgpu_gart_fini(struct amdgpu_device *adev);
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void amdgpu_gart_fini(struct amdgpu_device *adev);
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int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
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int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
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@ -1397,8 +1397,6 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
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void amdgpu_ttm_fini(struct amdgpu_device *adev)
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void amdgpu_ttm_fini(struct amdgpu_device *adev)
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{
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{
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int r;
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if (!adev->mman.initialized)
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if (!adev->mman.initialized)
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return;
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return;
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@ -483,16 +483,14 @@ static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable)
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static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
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static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
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{
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{
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int r, i;
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int i;
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u32 field;
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u32 field;
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if (adev->gart.robj == NULL) {
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if (adev->gart.robj == NULL) {
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dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
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dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
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return -EINVAL;
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return -EINVAL;
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}
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}
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r = amdgpu_gart_table_vram_pin(adev);
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if (r)
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return r;
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/* Setup TLB control */
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/* Setup TLB control */
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WREG32(mmMC_VM_MX_L1_TLB_CNTL,
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WREG32(mmMC_VM_MX_L1_TLB_CNTL,
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(0xA << 7) |
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(0xA << 7) |
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WREG32(mmVM_L2_CNTL3,
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WREG32(mmVM_L2_CNTL3,
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VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
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VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
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(0UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
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(0UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
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amdgpu_gart_table_vram_unpin(adev);
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}
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}
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static void gmc_v6_0_gart_fini(struct amdgpu_device *adev)
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static void gmc_v6_0_gart_fini(struct amdgpu_device *adev)
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@ -588,16 +588,14 @@ static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable)
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*/
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*/
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static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
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static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
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{
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{
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int r, i;
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int i;
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u32 tmp, field;
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u32 tmp, field;
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if (adev->gart.robj == NULL) {
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if (adev->gart.robj == NULL) {
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dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
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dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
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return -EINVAL;
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return -EINVAL;
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}
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}
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r = amdgpu_gart_table_vram_pin(adev);
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if (r)
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return r;
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/* Setup TLB control */
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/* Setup TLB control */
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tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
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tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
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tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
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tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
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tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
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tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
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WREG32(mmVM_L2_CNTL, tmp);
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WREG32(mmVM_L2_CNTL, tmp);
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WREG32(mmVM_L2_CNTL2, 0);
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WREG32(mmVM_L2_CNTL2, 0);
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amdgpu_gart_table_vram_unpin(adev);
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}
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}
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/**
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/**
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*/
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*/
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static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
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static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
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{
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{
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int r, i;
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int i;
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u32 tmp, field;
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u32 tmp, field;
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if (adev->gart.robj == NULL) {
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if (adev->gart.robj == NULL) {
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dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
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dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
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return -EINVAL;
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return -EINVAL;
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}
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}
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r = amdgpu_gart_table_vram_pin(adev);
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if (r)
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return r;
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/* Setup TLB control */
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/* Setup TLB control */
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tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
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tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
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tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
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tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
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tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
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tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
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WREG32(mmVM_L2_CNTL, tmp);
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WREG32(mmVM_L2_CNTL, tmp);
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WREG32(mmVM_L2_CNTL2, 0);
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WREG32(mmVM_L2_CNTL2, 0);
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amdgpu_gart_table_vram_unpin(adev);
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}
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}
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/**
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/**
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@ -869,7 +869,7 @@ static int gmc_v9_0_sw_init(void *handle)
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}
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}
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/**
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/**
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* gmc_v8_0_gart_fini - vm fini callback
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* gmc_v9_0_gart_fini - vm fini callback
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*
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*
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* @adev: amdgpu_device pointer
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* @adev: amdgpu_device pointer
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*
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*
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dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
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dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
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return -EINVAL;
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return -EINVAL;
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}
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}
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r = amdgpu_gart_table_vram_pin(adev);
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if (r)
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return r;
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switch (adev->asic_type) {
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switch (adev->asic_type) {
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case CHIP_RAVEN:
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case CHIP_RAVEN:
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{
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{
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gfxhub_v1_0_gart_disable(adev);
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gfxhub_v1_0_gart_disable(adev);
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mmhub_v1_0_gart_disable(adev);
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mmhub_v1_0_gart_disable(adev);
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amdgpu_gart_table_vram_unpin(adev);
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}
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}
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static int gmc_v9_0_hw_fini(void *handle)
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static int gmc_v9_0_hw_fini(void *handle)
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