mirror of https://gitee.com/openkylin/linux.git
ath9k_hw: clean up iniModesAdditional
use iniModesFastClock for 5 ghz fast clock specific settings, and iniAdditional for clock/chip specific initval overrides Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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9951c4d042
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@ -869,10 +869,9 @@ static int ar5008_hw_process_ini(struct ath_hw *ah,
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REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites);
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if (IS_CHAN_A_FAST_CLOCK(ah, chan)) {
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REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
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if (IS_CHAN_A_FAST_CLOCK(ah, chan))
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REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex,
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regWrites);
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}
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ar5008_hw_override_ini(ah, chan);
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ar5008_hw_set_channel_regs(ah, chan);
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@ -73,7 +73,7 @@ static void ar9002_hw_init_mode_regs(struct ath_hw *ah)
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INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
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ARRAY_SIZE(ar9280Common_9280_2), 2);
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INIT_INI_ARRAY(&ah->iniModesAdditional,
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INIT_INI_ARRAY(&ah->iniModesFastClock,
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ar9280Modes_fast_clock_9280_2,
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ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
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} else if (AR_SREV_9160_10_OR_LATER(ah)) {
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@ -87,11 +87,11 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
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/* additional clock settings */
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if (ah->is_clk_25mhz)
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INIT_INI_ARRAY(&ah->iniModesAdditional,
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INIT_INI_ARRAY(&ah->iniAdditional,
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ar9331_1p1_xtal_25M,
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ARRAY_SIZE(ar9331_1p1_xtal_25M), 2);
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else
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INIT_INI_ARRAY(&ah->iniModesAdditional,
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INIT_INI_ARRAY(&ah->iniAdditional,
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ar9331_1p1_xtal_40M,
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ARRAY_SIZE(ar9331_1p1_xtal_40M), 2);
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} else if (AR_SREV_9330_12(ah)) {
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@ -140,11 +140,11 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
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/* additional clock settings */
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if (ah->is_clk_25mhz)
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INIT_INI_ARRAY(&ah->iniModesAdditional,
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INIT_INI_ARRAY(&ah->iniAdditional,
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ar9331_1p2_xtal_25M,
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ARRAY_SIZE(ar9331_1p2_xtal_25M), 2);
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else
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INIT_INI_ARRAY(&ah->iniModesAdditional,
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INIT_INI_ARRAY(&ah->iniAdditional,
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ar9331_1p2_xtal_40M,
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ARRAY_SIZE(ar9331_1p2_xtal_40M), 2);
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} else if (AR_SREV_9340(ah)) {
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@ -194,15 +194,16 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
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ARRAY_SIZE(ar9340Modes_high_ob_db_tx_gain_table_1p0),
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5);
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INIT_INI_ARRAY(&ah->iniModesAdditional,
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INIT_INI_ARRAY(&ah->iniModesFastClock,
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ar9340Modes_fast_clock_1p0,
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ARRAY_SIZE(ar9340Modes_fast_clock_1p0),
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3);
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INIT_INI_ARRAY(&ah->iniModesAdditional_40M,
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ar9340_1p0_radio_core_40M,
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ARRAY_SIZE(ar9340_1p0_radio_core_40M),
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2);
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if (!ah->is_clk_25mhz)
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INIT_INI_ARRAY(&ah->iniAdditional,
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ar9340_1p0_radio_core_40M,
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ARRAY_SIZE(ar9340_1p0_radio_core_40M),
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2);
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} else if (AR_SREV_9485_11(ah)) {
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/* mac */
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
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@ -321,7 +322,7 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
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2);
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/* Fast clock modal settings */
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INIT_INI_ARRAY(&ah->iniModesAdditional,
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INIT_INI_ARRAY(&ah->iniModesFastClock,
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ar9462_modes_fast_clock_2p0,
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ARRAY_SIZE(ar9462_modes_fast_clock_2p0), 3);
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@ -378,7 +379,7 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
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ARRAY_SIZE(ar9580_1p0_low_ob_db_tx_gain_table),
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5);
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INIT_INI_ARRAY(&ah->iniModesAdditional,
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INIT_INI_ARRAY(&ah->iniModesFastClock,
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ar9580_1p0_modes_fast_clock,
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ARRAY_SIZE(ar9580_1p0_modes_fast_clock),
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3);
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@ -445,7 +446,7 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
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2);
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/* Fast clock modal settings */
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INIT_INI_ARRAY(&ah->iniModesAdditional,
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INIT_INI_ARRAY(&ah->iniModesFastClock,
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ar9300Modes_fast_clock_2p2,
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ARRAY_SIZE(ar9300Modes_fast_clock_2p2),
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3);
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@ -679,14 +679,10 @@ static int ar9003_hw_process_ini(struct ath_hw *ah,
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* different modal values.
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*/
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if (IS_CHAN_A_FAST_CLOCK(ah, chan))
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REG_WRITE_ARRAY(&ah->iniModesAdditional,
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REG_WRITE_ARRAY(&ah->iniModesFastClock,
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modesIndex, regWrites);
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if (AR_SREV_9330(ah))
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REG_WRITE_ARRAY(&ah->iniModesAdditional, 1, regWrites);
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if (AR_SREV_9340(ah) && !ah->is_clk_25mhz)
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REG_WRITE_ARRAY(&ah->iniModesAdditional_40M, 1, regWrites);
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REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);
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if (AR_SREV_9462(ah))
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ar9003_hw_prog_ini(ah, &ah->ini_BTCOEX_MAX_TXPWR, 1);
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@ -1323,13 +1319,9 @@ static int ar9003_hw_fast_chan_change(struct ath_hw *ah,
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* different modal values.
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*/
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if (IS_CHAN_A_FAST_CLOCK(ah, chan))
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REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex, regWrites);
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REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, regWrites);
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if (AR_SREV_9330(ah))
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REG_WRITE_ARRAY(&ah->iniModesAdditional, 1, regWrites);
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if (AR_SREV_9340(ah) && !ah->is_clk_25mhz)
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REG_WRITE_ARRAY(&ah->iniModesAdditional_40M, 1, regWrites);
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REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);
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ah->modes_index = modesIndex;
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*ini_reloaded = true;
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@ -827,8 +827,8 @@ struct ath_hw {
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struct ar5416IniArray iniAddac;
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struct ar5416IniArray iniPcieSerdes;
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struct ar5416IniArray iniPcieSerdesLowPower;
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struct ar5416IniArray iniModesAdditional;
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struct ar5416IniArray iniModesAdditional_40M;
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struct ar5416IniArray iniModesFastClock;
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struct ar5416IniArray iniAdditional;
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struct ar5416IniArray iniModesRxGain;
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struct ar5416IniArray iniModesTxGain;
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struct ar5416IniArray iniModes_9271_1_0_only;
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