mirror of https://gitee.com/openkylin/linux.git
Merge branch 'pci/virtualization' into next
* pci/virtualization: PCI: Enable quirks for PCIe ACS on Intel PCH root ports PCI: Add pci_dev_flag for ACS enable quirks PCI: Add device-specific PCI ACS enable
This commit is contained in:
Bjorn Helgaas
commit
c80ef97ae4
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@ -2180,21 +2180,18 @@ void pci_request_acs(void)
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}
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/**
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* pci_enable_acs - enable ACS if hardware support it
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* pci_std_enable_acs - enable ACS on devices using standard ACS capabilites
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* @dev: the PCI device
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*/
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void pci_enable_acs(struct pci_dev *dev)
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static int pci_std_enable_acs(struct pci_dev *dev)
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{
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int pos;
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u16 cap;
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u16 ctrl;
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if (!pci_acs_enable)
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return;
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pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
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if (!pos)
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return;
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return -ENODEV;
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pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
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pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
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@ -2212,6 +2209,23 @@ void pci_enable_acs(struct pci_dev *dev)
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ctrl |= (cap & PCI_ACS_UF);
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pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
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return 0;
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}
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/**
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* pci_enable_acs - enable ACS if hardware support it
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* @dev: the PCI device
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*/
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void pci_enable_acs(struct pci_dev *dev)
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{
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if (!pci_acs_enable)
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return;
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if (!pci_std_enable_acs(dev))
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return;
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pci_dev_specific_enable_acs(dev);
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}
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static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
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@ -3423,6 +3423,61 @@ static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
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#endif
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}
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/*
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* Many Intel PCH root ports do provide ACS-like features to disable peer
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* transactions and validate bus numbers in requests, but do not provide an
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* actual PCIe ACS capability. This is the list of device IDs known to fall
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* into that category as provided by Intel in Red Hat bugzilla 1037684.
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*/
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static const u16 pci_quirk_intel_pch_acs_ids[] = {
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/* Ibexpeak PCH */
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0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
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0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
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/* Cougarpoint PCH */
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0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
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0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
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/* Pantherpoint PCH */
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0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
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0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
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/* Lynxpoint-H PCH */
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0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
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0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
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/* Lynxpoint-LP PCH */
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0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
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0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
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/* Wildcat PCH */
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0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
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0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
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};
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static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev)
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{
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int i;
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/* Filter out a few obvious non-matches first */
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if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
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return false;
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for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++)
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if (pci_quirk_intel_pch_acs_ids[i] == dev->device)
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return true;
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return false;
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}
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#define INTEL_PCH_ACS_FLAGS (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV)
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static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
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{
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u16 flags = dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK ?
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INTEL_PCH_ACS_FLAGS : 0;
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if (!pci_quirk_intel_pch_acs_match(dev))
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return -ENOTTY;
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return acs_flags & ~flags ? 0 : 1;
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}
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static const struct pci_dev_acs_enabled {
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u16 vendor;
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u16 device;
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@ -3434,6 +3489,7 @@ static const struct pci_dev_acs_enabled {
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{ PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
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{ PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
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{ PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
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{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
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{ 0 }
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};
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@ -3461,3 +3517,132 @@ int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
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return -ENOTTY;
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}
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/* Config space offset of Root Complex Base Address register */
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#define INTEL_LPC_RCBA_REG 0xf0
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/* 31:14 RCBA address */
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#define INTEL_LPC_RCBA_MASK 0xffffc000
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/* RCBA Enable */
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#define INTEL_LPC_RCBA_ENABLE (1 << 0)
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/* Backbone Scratch Pad Register */
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#define INTEL_BSPR_REG 0x1104
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/* Backbone Peer Non-Posted Disable */
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#define INTEL_BSPR_REG_BPNPD (1 << 8)
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/* Backbone Peer Posted Disable */
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#define INTEL_BSPR_REG_BPPD (1 << 9)
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/* Upstream Peer Decode Configuration Register */
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#define INTEL_UPDCR_REG 0x1114
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/* 5:0 Peer Decode Enable bits */
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#define INTEL_UPDCR_REG_MASK 0x3f
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static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)
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{
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u32 rcba, bspr, updcr;
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void __iomem *rcba_mem;
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/*
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* Read the RCBA register from the LPC (D31:F0). PCH root ports
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* are D28:F* and therefore get probed before LPC, thus we can't
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* use pci_get_slot/pci_read_config_dword here.
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*/
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pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0),
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INTEL_LPC_RCBA_REG, &rcba);
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if (!(rcba & INTEL_LPC_RCBA_ENABLE))
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return -EINVAL;
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rcba_mem = ioremap_nocache(rcba & INTEL_LPC_RCBA_MASK,
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PAGE_ALIGN(INTEL_UPDCR_REG));
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if (!rcba_mem)
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return -ENOMEM;
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/*
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* The BSPR can disallow peer cycles, but it's set by soft strap and
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* therefore read-only. If both posted and non-posted peer cycles are
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* disallowed, we're ok. If either are allowed, then we need to use
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* the UPDCR to disable peer decodes for each port. This provides the
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* PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
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*/
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bspr = readl(rcba_mem + INTEL_BSPR_REG);
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bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD;
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if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) {
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updcr = readl(rcba_mem + INTEL_UPDCR_REG);
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if (updcr & INTEL_UPDCR_REG_MASK) {
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dev_info(&dev->dev, "Disabling UPDCR peer decodes\n");
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updcr &= ~INTEL_UPDCR_REG_MASK;
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writel(updcr, rcba_mem + INTEL_UPDCR_REG);
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}
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}
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iounmap(rcba_mem);
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return 0;
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}
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/* Miscellaneous Port Configuration register */
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#define INTEL_MPC_REG 0xd8
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/* MPC: Invalid Receive Bus Number Check Enable */
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#define INTEL_MPC_REG_IRBNCE (1 << 26)
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static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev)
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{
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u32 mpc;
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/*
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* When enabled, the IRBNCE bit of the MPC register enables the
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* equivalent of PCI ACS Source Validation (PCI_ACS_SV), which
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* ensures that requester IDs fall within the bus number range
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* of the bridge. Enable if not already.
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*/
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pci_read_config_dword(dev, INTEL_MPC_REG, &mpc);
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if (!(mpc & INTEL_MPC_REG_IRBNCE)) {
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dev_info(&dev->dev, "Enabling MPC IRBNCE\n");
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mpc |= INTEL_MPC_REG_IRBNCE;
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pci_write_config_word(dev, INTEL_MPC_REG, mpc);
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}
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}
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static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
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{
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if (!pci_quirk_intel_pch_acs_match(dev))
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return -ENOTTY;
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if (pci_quirk_enable_intel_lpc_acs(dev)) {
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dev_warn(&dev->dev, "Failed to enable Intel PCH ACS quirk\n");
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return 0;
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}
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pci_quirk_enable_intel_rp_mpc_acs(dev);
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dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK;
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dev_info(&dev->dev, "Intel PCH root port ACS workaround enabled\n");
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return 0;
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}
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static const struct pci_dev_enable_acs {
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u16 vendor;
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u16 device;
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int (*enable_acs)(struct pci_dev *dev);
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} pci_dev_enable_acs[] = {
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{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_enable_intel_pch_acs },
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{ 0 }
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};
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void pci_dev_specific_enable_acs(struct pci_dev *dev)
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{
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const struct pci_dev_enable_acs *i;
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int ret;
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for (i = pci_dev_enable_acs; i->enable_acs; i++) {
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if ((i->vendor == dev->vendor ||
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i->vendor == (u16)PCI_ANY_ID) &&
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(i->device == dev->device ||
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i->device == (u16)PCI_ANY_ID)) {
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ret = i->enable_acs(dev);
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if (ret >= 0)
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return;
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}
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}
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}
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@ -170,6 +170,8 @@ enum pci_dev_flags {
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PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
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/* Provide indication device is assigned by a Virtual Machine Manager */
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PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) 4,
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/* Flag for quirk use to store if quirk-specific ACS is enabled */
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PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) 8,
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};
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enum pci_irq_reroute_variant {
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@ -1510,6 +1512,7 @@ enum pci_fixup_pass {
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void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
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struct pci_dev *pci_get_dma_source(struct pci_dev *dev);
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int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
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void pci_dev_specific_enable_acs(struct pci_dev *dev);
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#else
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static inline void pci_fixup_device(enum pci_fixup_pass pass,
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struct pci_dev *dev) { }
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@ -1522,6 +1525,7 @@ static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
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{
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return -ENOTTY;
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}
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static inline void pci_dev_specific_enable_acs(struct pci_dev *dev) { }
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#endif
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void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
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