mirror of https://gitee.com/openkylin/linux.git
drm/i915: extract ironlake_set_pipeconf form ironlake_crtc_mode_set
Because ironlake_crtc_mode_set is a giant function that used to have 404 lines. Let's try to make it less complex/confusing. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Paulo Zanoni
Daniel Vetter
parent
9da3da660d
commit
c8203565b0
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@ -4648,6 +4648,50 @@ static int ironlake_get_refclk(struct drm_crtc *crtc)
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return 120000;
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}
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static void ironlake_set_pipeconf(struct drm_crtc *crtc,
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struct drm_display_mode *adjusted_mode,
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bool dither)
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{
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struct drm_i915_private *dev_priv = crtc->dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int pipe = intel_crtc->pipe;
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uint32_t val;
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val = I915_READ(PIPECONF(pipe));
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val &= ~PIPE_BPC_MASK;
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switch (intel_crtc->bpp) {
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case 18:
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val |= PIPE_6BPC;
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break;
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case 24:
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val |= PIPE_8BPC;
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break;
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case 30:
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val |= PIPE_10BPC;
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break;
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case 36:
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val |= PIPE_12BPC;
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break;
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default:
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val |= PIPE_8BPC;
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break;
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}
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val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
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if (dither)
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val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
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val &= ~PIPECONF_INTERLACE_MASK;
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if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
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val |= PIPECONF_INTERLACED_ILK;
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else
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val |= PIPECONF_PROGRESSIVE;
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I915_WRITE(PIPECONF(pipe), val);
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POSTING_READ(PIPECONF(pipe));
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}
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static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode,
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@ -4661,7 +4705,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
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int plane = intel_crtc->plane;
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int refclk, num_connectors = 0;
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intel_clock_t clock, reduced_clock;
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u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
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u32 dpll, fp = 0, fp2 = 0, dspcntr;
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bool ok, has_reduced_clock = false, is_sdvo = false;
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bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
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struct intel_encoder *encoder, *edp_encoder = NULL;
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@ -4770,32 +4814,17 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
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target_clock = adjusted_mode->clock;
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/* determine panel color depth */
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temp = I915_READ(PIPECONF(pipe));
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temp &= ~PIPE_BPC_MASK;
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dither = intel_choose_pipe_bpp_dither(crtc, fb, &pipe_bpp, mode);
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switch (pipe_bpp) {
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case 18:
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temp |= PIPE_6BPC;
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break;
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case 24:
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temp |= PIPE_8BPC;
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break;
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case 30:
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temp |= PIPE_10BPC;
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break;
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case 36:
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temp |= PIPE_12BPC;
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break;
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default:
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WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
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pipe_bpp);
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temp |= PIPE_8BPC;
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pipe_bpp = 24;
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break;
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}
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if (is_lvds && dev_priv->lvds_dither)
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dither = true;
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if (pipe_bpp != 18 && pipe_bpp != 24 && pipe_bpp != 30 &&
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pipe_bpp != 36) {
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WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
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pipe_bpp);
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pipe_bpp = 24;
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}
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intel_crtc->bpp = pipe_bpp;
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I915_WRITE(PIPECONF(pipe), temp);
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if (!lane) {
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/*
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@ -4879,9 +4908,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
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else
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dpll |= PLL_REF_INPUT_DREFCLK;
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/* setup pipeconf */
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pipeconf = I915_READ(PIPECONF(pipe));
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/* Set up the display plane register */
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dspcntr = DISPPLANE_GAMMA_ENABLE;
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@ -4944,12 +4970,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
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I915_WRITE(PCH_LVDS, temp);
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}
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pipeconf &= ~PIPECONF_DITHER_EN;
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pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
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if ((is_lvds && dev_priv->lvds_dither) || dither) {
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pipeconf |= PIPECONF_DITHER_EN;
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pipeconf |= PIPECONF_DITHER_TYPE_SP;
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}
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if (is_dp && !is_cpu_edp) {
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intel_dp_set_m_n(crtc, mode, adjusted_mode);
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} else {
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@ -4985,9 +5005,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
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}
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}
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pipeconf &= ~PIPECONF_INTERLACE_MASK;
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if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
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pipeconf |= PIPECONF_INTERLACED_ILK;
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/* the chip adds 2 halflines automatically */
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adjusted_mode->crtc_vtotal -= 1;
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adjusted_mode->crtc_vblank_end -= 1;
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@ -4995,7 +5013,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
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adjusted_mode->crtc_hsync_start
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- adjusted_mode->crtc_htotal/2);
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} else {
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pipeconf |= PIPECONF_PROGRESSIVE;
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I915_WRITE(VSYNCSHIFT(pipe), 0);
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}
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@ -5033,8 +5050,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
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if (is_cpu_edp)
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ironlake_set_pll_edp(crtc, adjusted_mode->clock);
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I915_WRITE(PIPECONF(pipe), pipeconf);
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POSTING_READ(PIPECONF(pipe));
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ironlake_set_pipeconf(crtc, adjusted_mode, dither);
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intel_wait_for_vblank(dev, pipe);
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