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drm/i915: Add support for the YCbCr COLOR_RANGE property 

Add support for the COLOR_RANGE property on planes. This property
selects whether the input YCbCr data is to treated as limited range
or full range.

On most platforms this is a matter of setting the "YUV range correction
disable" bit, and on VLV/CHV we'll just have to program the color
correction logic to pass the data through unmodified.

v2: Rebase

Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Daniel Vetter <daniel@ffwll.ch>
Cc: Daniel Stone <daniel@fooishbar.org>
Cc: Russell King - ARM Linux <linux@armlinux.org.uk>
Cc: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: Hans Verkuil <hverkuil@xs4all.nl>
Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Shashank Sharma <shashank.sharma@intel.com>
Cc: Jyri Sarha <jsarha@ti.com>
Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180214192327.3250-9-ville.syrjala@linux.intel.com
This commit is contained in:
Ville Syrjälä 2018-02-14 21:23:27 +02:00
parent 23b280890a
commit c8624ede3e
3 changed files with 22 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/drm/i915/i915_reg.h
View File

@ -6105,6 +6105,7 @@ enum {
#define _DVSACNTR 0x72180 #define _DVSACNTR 0x72180
#define DVS_ENABLE (1<<31) #define DVS_ENABLE (1<<31)
#define DVS_GAMMA_ENABLE (1<<30) #define DVS_GAMMA_ENABLE (1<<30)
#define DVS_YUV_RANGE_CORRECTION_DISABLE (1<<27)
#define DVS_PIXFORMAT_MASK (3<<25) #define DVS_PIXFORMAT_MASK (3<<25)
#define DVS_FORMAT_YUV422 (0<<25) #define DVS_FORMAT_YUV422 (0<<25)
#define DVS_FORMAT_RGBX101010 (1<<25) #define DVS_FORMAT_RGBX101010 (1<<25)
@ -6173,6 +6174,7 @@ enum {
#define _SPRA_CTL 0x70280 #define _SPRA_CTL 0x70280
#define SPRITE_ENABLE (1<<31) #define SPRITE_ENABLE (1<<31)
#define SPRITE_GAMMA_ENABLE (1<<30) #define SPRITE_GAMMA_ENABLE (1<<30)
#define SPRITE_YUV_RANGE_CORRECTION_DISABLE (1<<28)
#define SPRITE_PIXFORMAT_MASK (7<<25) #define SPRITE_PIXFORMAT_MASK (7<<25)
#define SPRITE_FORMAT_YUV422 (0<<25) #define SPRITE_FORMAT_YUV422 (0<<25)
#define SPRITE_FORMAT_RGBX101010 (1<<25) #define SPRITE_FORMAT_RGBX101010 (1<<25)
@ -6364,6 +6366,7 @@ enum {
#define _PLANE_CTL_3_A 0x70380 #define _PLANE_CTL_3_A 0x70380
#define PLANE_CTL_ENABLE (1 << 31) #define PLANE_CTL_ENABLE (1 << 31)
#define PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-GLK */ #define PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-GLK */
#define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
/* /*
* ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition
* expanded to include bit 23 as well. However, the shift-24 based values * expanded to include bit 23 as well. However, the shift-24 based values
@ -6438,6 +6441,7 @@ enum {
#define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */ #define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */
#define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */ #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
#define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30) #define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30)
#define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
#define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) #define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23)
#define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17) #define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17)
#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709 (1 << 17) #define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709 (1 << 17)

9
drivers/gpu/drm/i915/intel_display.c
View File

@ -3539,6 +3539,9 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709) if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709; plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709;
if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE;
} }
plane_ctl |= skl_plane_ctl_format(fb->format->format); plane_ctl |= skl_plane_ctl_format(fb->format->format);
@ -3573,6 +3576,9 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709; plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
else else
plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709; plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
} }
return plane_color_ctl; return plane_color_ctl;
@ -13300,7 +13306,8 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
drm_plane_create_color_properties(&primary->base, drm_plane_create_color_properties(&primary->base,
BIT(DRM_COLOR_YCBCR_BT601) | BIT(DRM_COLOR_YCBCR_BT601) |
BIT(DRM_COLOR_YCBCR_BT709), BIT(DRM_COLOR_YCBCR_BT709),
BIT(DRM_COLOR_YCBCR_LIMITED_RANGE), BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
BIT(DRM_COLOR_YCBCR_FULL_RANGE),
DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_BT709,
DRM_COLOR_YCBCR_LIMITED_RANGE); DRM_COLOR_YCBCR_LIMITED_RANGE);

12
drivers/gpu/drm/i915/intel_sprite.c
View File

@ -414,7 +414,8 @@ vlv_update_clrc(const struct intel_plane_state *plane_state)
enum plane_id plane_id = plane->id; enum plane_id plane_id = plane->id;
int contrast, brightness, sh_scale, sh_sin, sh_cos; int contrast, brightness, sh_scale, sh_sin, sh_cos;
if (intel_format_is_yuv(fb->format->format)) { if (intel_format_is_yuv(fb->format->format) &&
plane_state->base.color_range == DRM_COLOR_YCBCR_LIMITED_RANGE) {
/* /*
* Expand limited range to full range: * Expand limited range to full range:
* Contrast is applied first and is used to expand Y range. * Contrast is applied first and is used to expand Y range.
@ -650,6 +651,9 @@ static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709) if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
sprctl |= SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709; sprctl |= SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709;
if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
sprctl |= SPRITE_YUV_RANGE_CORRECTION_DISABLE;
if (fb->modifier == I915_FORMAT_MOD_X_TILED) if (fb->modifier == I915_FORMAT_MOD_X_TILED)
sprctl |= SPRITE_TILED; sprctl |= SPRITE_TILED;
@ -809,6 +813,9 @@ static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709) if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
dvscntr |= DVS_YUV_FORMAT_BT709; dvscntr |= DVS_YUV_FORMAT_BT709;
if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
dvscntr |= DVS_YUV_RANGE_CORRECTION_DISABLE;
if (fb->modifier == I915_FORMAT_MOD_X_TILED) if (fb->modifier == I915_FORMAT_MOD_X_TILED)
dvscntr |= DVS_TILED; dvscntr |= DVS_TILED;
@ -1528,7 +1535,8 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
drm_plane_create_color_properties(&intel_plane->base, drm_plane_create_color_properties(&intel_plane->base,
BIT(DRM_COLOR_YCBCR_BT601) | BIT(DRM_COLOR_YCBCR_BT601) |
BIT(DRM_COLOR_YCBCR_BT709), BIT(DRM_COLOR_YCBCR_BT709),
BIT(DRM_COLOR_YCBCR_LIMITED_RANGE), BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
BIT(DRM_COLOR_YCBCR_FULL_RANGE),
DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_BT709,
DRM_COLOR_YCBCR_LIMITED_RANGE); DRM_COLOR_YCBCR_LIMITED_RANGE);