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NTB: Fix typo in setting one translation register 

In the code for Xeon devices in back-to-back mode with xeon_errata_workaround
disabled, the downstream device puts the wrong value in SNB_B2B_XLAT_OFFSETL
(SNB_MBAR01_DSD_ADDR vs. SNB_MBAR01_USD_ADDR).

This was spotted while reading code, since the typo has no practical effect,
at least for now: the low 32 bits of both constants are actually identical
anyway.  However, it's clearer and safer to use the right name.

Signed-off-by: Roland Dreier <roland@purestorage.com>
Signed-off-by: Jon Mason <jon.mason@intel.com>
This commit is contained in:
Roland Dreier 2014-02-21 08:07:21 -08:00 committed by Jon Mason
parent e8bc2ebdce
commit c8eee3795d
1 changed files with 1 additions and 1 deletions
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2
drivers/ntb/ntb_hw.c
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@ -785,7 +785,7 @@ static int ntb_xeon_setup(struct ntb_device *ndev)
/* B2B_XLAT_OFFSET is a 64bit register, but can
* only take 32bit writes
*/
writel(SNB_MBAR01_DSD_ADDR & 0xffffffff,
writel(SNB_MBAR01_USD_ADDR & 0xffffffff,
ndev->reg_base + SNB_B2B_XLAT_OFFSETL);
writel(SNB_MBAR01_USD_ADDR >> 32,
ndev->reg_base + SNB_B2B_XLAT_OFFSETU);