mirror of https://gitee.com/openkylin/linux.git
mrf24j40: rework rx handling to async rx handling
This patch prepares that we can do the receive handling inside interrupt context by using spi_async. This is necessary for introduce a non-threaded irq handling. Also we drop the bit setting for "RXDECINV" at register "BBREG1", we do a driectly full write of register "BBREG1", because it contains the bit RXDECINV only. Reviewed-by: Stefan Schmidt <stefan@osg.samsung.com> Signed-off-by: Alexander Aring <alex.aring@gmail.com> Signed-off-by: Marcel Holtmann <marcel@holtmann.org>
This commit is contained in:
Alexander Aring
Marcel Holtmann
parent
6844a0e4de
commit
c91a301162
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@ -167,6 +167,20 @@ struct mrf24j40 {
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u8 tx_post_buf[2];
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struct spi_transfer tx_post_trx;
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/* for protect/unprotect/read length rxfifo */
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struct spi_message rx_msg;
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u8 rx_buf[3];
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struct spi_transfer rx_trx;
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/* receive handling */
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struct spi_message rx_buf_msg;
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u8 rx_addr_buf[2];
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struct spi_transfer rx_addr_trx;
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u8 rx_lqi_buf[2];
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struct spi_transfer rx_lqi_trx;
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u8 rx_fifo_buf[RX_FIFO_SIZE];
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struct spi_transfer rx_fifo_buf_trx;
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struct mutex buffer_mutex; /* only used to protect buf */
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u8 *buf; /* 3 bytes. Used for SPI single-register transfers. */
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};
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@ -472,32 +486,6 @@ static const struct regmap_bus mrf24j40_long_regmap_bus = {
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.val_format_endian_default = REGMAP_ENDIAN_BIG,
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};
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static int write_short_reg(struct mrf24j40 *devrec, u8 reg, u8 value)
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{
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int ret;
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struct spi_message msg;
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struct spi_transfer xfer = {
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.len = 2,
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.tx_buf = devrec->buf,
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.rx_buf = devrec->buf,
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};
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spi_message_init(&msg);
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spi_message_add_tail(&xfer, &msg);
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mutex_lock(&devrec->buffer_mutex);
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devrec->buf[0] = MRF24J40_WRITESHORT(reg);
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devrec->buf[1] = value;
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ret = spi_sync(devrec->spi, &msg);
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if (ret)
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dev_err(printdev(devrec),
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"SPI write Failed for short register 0x%hhx\n", reg);
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mutex_unlock(&devrec->buffer_mutex);
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return ret;
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}
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static int read_short_reg(struct mrf24j40 *devrec, u8 reg, u8 *val)
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{
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int ret = -1;
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@ -526,37 +514,6 @@ static int read_short_reg(struct mrf24j40 *devrec, u8 reg, u8 *val)
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return ret;
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}
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static int read_long_reg(struct mrf24j40 *devrec, u16 reg, u8 *value)
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{
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int ret;
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u16 cmd;
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struct spi_message msg;
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struct spi_transfer xfer = {
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.len = 3,
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.tx_buf = devrec->buf,
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.rx_buf = devrec->buf,
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};
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spi_message_init(&msg);
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spi_message_add_tail(&xfer, &msg);
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cmd = MRF24J40_READLONG(reg);
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mutex_lock(&devrec->buffer_mutex);
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devrec->buf[0] = cmd >> 8 & 0xff;
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devrec->buf[1] = cmd & 0xff;
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devrec->buf[2] = 0;
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ret = spi_sync(devrec->spi, &msg);
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if (ret)
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dev_err(printdev(devrec),
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"SPI read Failed for long register 0x%hx\n", reg);
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else
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*value = devrec->buf[2];
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mutex_unlock(&devrec->buffer_mutex);
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return ret;
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}
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static void write_tx_buf_complete(void *context)
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{
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struct mrf24j40 *devrec = context;
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@ -616,78 +573,6 @@ static int mrf24j40_tx(struct ieee802154_hw *hw, struct sk_buff *skb)
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return write_tx_buf(devrec, 0x000, skb->data, skb->len);
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}
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static int mrf24j40_read_rx_buf(struct mrf24j40 *devrec,
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u8 *data, u8 *len, u8 *lqi)
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{
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u8 rx_len;
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u8 addr[2];
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u8 lqi_rssi[2];
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u16 cmd;
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int ret;
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struct spi_message msg;
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struct spi_transfer addr_xfer = {
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.len = 2,
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.tx_buf = &addr,
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};
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struct spi_transfer data_xfer = {
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.len = 0x0, /* set below */
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.rx_buf = data,
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};
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struct spi_transfer status_xfer = {
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.len = 2,
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.rx_buf = &lqi_rssi,
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};
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/* Get the length of the data in the RX FIFO. The length in this
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* register exclues the 1-byte length field at the beginning. */
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ret = read_long_reg(devrec, REG_RX_FIFO, &rx_len);
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if (ret)
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goto out;
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/* Range check the RX FIFO length, accounting for the one-byte
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* length field at the beginning. */
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if (rx_len > RX_FIFO_SIZE-1) {
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dev_err(printdev(devrec), "Invalid length read from device. Performing short read.\n");
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rx_len = RX_FIFO_SIZE-1;
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}
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if (rx_len > *len) {
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/* Passed in buffer wasn't big enough. Should never happen. */
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dev_err(printdev(devrec), "Buffer not big enough. Performing short read\n");
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rx_len = *len;
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}
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/* Set up the commands to read the data. */
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cmd = MRF24J40_READLONG(REG_RX_FIFO+1);
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addr[0] = cmd >> 8 & 0xff;
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addr[1] = cmd & 0xff;
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data_xfer.len = rx_len;
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spi_message_init(&msg);
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spi_message_add_tail(&addr_xfer, &msg);
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spi_message_add_tail(&data_xfer, &msg);
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spi_message_add_tail(&status_xfer, &msg);
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ret = spi_sync(devrec->spi, &msg);
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if (ret) {
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dev_err(printdev(devrec), "SPI RX Buffer Read Failed.\n");
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goto out;
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}
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*lqi = lqi_rssi[0];
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*len = rx_len;
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#ifdef DEBUG
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print_hex_dump(KERN_DEBUG, "mrf24j40 rx: ",
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DUMP_PREFIX_OFFSET, 16, 1, data, *len, 0);
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pr_debug("mrf24j40 rx: lqi: %02hhx rssi: %02hhx\n",
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lqi_rssi[0], lqi_rssi[1]);
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#endif
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out:
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return ret;
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}
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static int mrf24j40_ed(struct ieee802154_hw *hw, u8 *level)
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{
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/* TODO: */
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@ -823,53 +708,98 @@ static int mrf24j40_filter(struct ieee802154_hw *hw,
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return 0;
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}
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static int mrf24j40_handle_rx(struct mrf24j40 *devrec)
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static void mrf24j40_handle_rx_read_buf_unlock(struct mrf24j40 *devrec)
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{
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u8 len = RX_FIFO_SIZE;
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u8 lqi = 0;
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u8 val;
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int ret = 0;
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int ret2;
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int ret;
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/* Turn back on reception of packets off the air. */
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devrec->rx_msg.complete = NULL;
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devrec->rx_buf[0] = MRF24J40_WRITESHORT(REG_BBREG1);
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devrec->rx_buf[1] = 0x00; /* CLR RXDECINV */
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ret = spi_async(devrec->spi, &devrec->rx_msg);
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if (ret)
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dev_err(printdev(devrec), "failed to unlock rx buffer\n");
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}
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static void mrf24j40_handle_rx_read_buf_complete(void *context)
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{
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struct mrf24j40 *devrec = context;
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u8 len = devrec->rx_buf[2];
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u8 rx_local_buf[RX_FIFO_SIZE];
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struct sk_buff *skb;
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/* Turn off reception of packets off the air. This prevents the
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* device from overwriting the buffer while we're reading it. */
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ret = read_short_reg(devrec, REG_BBREG1, &val);
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if (ret)
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goto out;
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val |= 4; /* SET RXDECINV */
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write_short_reg(devrec, REG_BBREG1, val);
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memcpy(rx_local_buf, devrec->rx_fifo_buf, len);
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mrf24j40_handle_rx_read_buf_unlock(devrec);
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skb = dev_alloc_skb(len);
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skb = dev_alloc_skb(IEEE802154_MTU);
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if (!skb) {
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ret = -ENOMEM;
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goto out;
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dev_err(printdev(devrec), "failed to allocate skb\n");
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return;
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}
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ret = mrf24j40_read_rx_buf(devrec, skb_put(skb, len), &len, &lqi);
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if (ret < 0) {
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dev_err(printdev(devrec), "Failure reading RX FIFO\n");
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kfree_skb(skb);
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ret = -EINVAL;
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goto out;
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memcpy(skb_put(skb, len), rx_local_buf, len);
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ieee802154_rx_irqsafe(devrec->hw, skb, 0);
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#ifdef DEBUG
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print_hex_dump(KERN_DEBUG, "mrf24j40 rx: ", DUMP_PREFIX_OFFSET, 16, 1,
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rx_local_buf, len, 0);
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pr_debug("mrf24j40 rx: lqi: %02hhx rssi: %02hhx\n",
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devrec->rx_lqi_buf[0], devrec->rx_lqi_buf[1]);
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#endif
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}
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static void mrf24j40_handle_rx_read_buf(void *context)
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{
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struct mrf24j40 *devrec = context;
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u16 cmd;
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int ret;
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/* if length is invalid read the full MTU */
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if (!ieee802154_is_valid_psdu_len(devrec->rx_buf[2]))
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devrec->rx_buf[2] = IEEE802154_MTU;
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cmd = MRF24J40_READLONG(REG_RX_FIFO + 1);
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devrec->rx_addr_buf[0] = cmd >> 8 & 0xff;
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devrec->rx_addr_buf[1] = cmd & 0xff;
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devrec->rx_fifo_buf_trx.len = devrec->rx_buf[2];
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ret = spi_async(devrec->spi, &devrec->rx_buf_msg);
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if (ret) {
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dev_err(printdev(devrec), "failed to read rx buffer\n");
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mrf24j40_handle_rx_read_buf_unlock(devrec);
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}
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}
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/* TODO: Other drivers call ieee20154_rx_irqsafe() here (eg: cc2040,
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* also from a workqueue). I think irqsafe is not necessary here.
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* Can someone confirm? */
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ieee802154_rx_irqsafe(devrec->hw, skb, lqi);
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static void mrf24j40_handle_rx_read_len(void *context)
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{
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struct mrf24j40 *devrec = context;
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u16 cmd;
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int ret;
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dev_dbg(printdev(devrec), "RX Handled\n");
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/* read the length of received frame */
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devrec->rx_msg.complete = mrf24j40_handle_rx_read_buf;
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devrec->rx_trx.len = 3;
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cmd = MRF24J40_READLONG(REG_RX_FIFO);
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devrec->rx_buf[0] = cmd >> 8 & 0xff;
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devrec->rx_buf[1] = cmd & 0xff;
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out:
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/* Turn back on reception of packets off the air. */
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ret2 = read_short_reg(devrec, REG_BBREG1, &val);
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if (ret2)
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return ret2;
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val &= ~0x4; /* Clear RXDECINV */
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write_short_reg(devrec, REG_BBREG1, val);
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ret = spi_async(devrec->spi, &devrec->rx_msg);
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if (ret) {
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dev_err(printdev(devrec), "failed to read rx buffer length\n");
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mrf24j40_handle_rx_read_buf_unlock(devrec);
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}
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}
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return ret;
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static int mrf24j40_handle_rx(struct mrf24j40 *devrec)
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{
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/* Turn off reception of packets off the air. This prevents the
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* device from overwriting the buffer while we're reading it.
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*/
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devrec->rx_msg.complete = mrf24j40_handle_rx_read_len;
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devrec->rx_trx.len = 2;
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devrec->rx_buf[0] = MRF24J40_WRITESHORT(REG_BBREG1);
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devrec->rx_buf[1] = 0x04; /* SET RXDECINV */
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return spi_async(devrec->spi, &devrec->rx_msg);
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}
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static const struct ieee802154_ops mrf24j40_ops = {
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@ -1025,6 +955,29 @@ mrf24j40_setup_tx_spi_messages(struct mrf24j40 *devrec)
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spi_message_add_tail(&devrec->tx_post_trx, &devrec->tx_post_msg);
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}
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static void
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mrf24j40_setup_rx_spi_messages(struct mrf24j40 *devrec)
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{
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spi_message_init(&devrec->rx_msg);
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devrec->rx_msg.context = devrec;
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devrec->rx_trx.len = 2;
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devrec->rx_trx.tx_buf = devrec->rx_buf;
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devrec->rx_trx.rx_buf = devrec->rx_buf;
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spi_message_add_tail(&devrec->rx_trx, &devrec->rx_msg);
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spi_message_init(&devrec->rx_buf_msg);
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devrec->rx_buf_msg.context = devrec;
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devrec->rx_buf_msg.complete = mrf24j40_handle_rx_read_buf_complete;
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devrec->rx_addr_trx.len = 2;
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devrec->rx_addr_trx.tx_buf = devrec->rx_addr_buf;
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spi_message_add_tail(&devrec->rx_addr_trx, &devrec->rx_buf_msg);
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devrec->rx_fifo_buf_trx.rx_buf = devrec->rx_fifo_buf;
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spi_message_add_tail(&devrec->rx_fifo_buf_trx, &devrec->rx_buf_msg);
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devrec->rx_lqi_trx.len = 2;
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devrec->rx_lqi_trx.rx_buf = devrec->rx_lqi_buf;
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spi_message_add_tail(&devrec->rx_lqi_trx, &devrec->rx_buf_msg);
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}
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static void mrf24j40_phy_setup(struct mrf24j40 *devrec)
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{
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ieee802154_random_extended_addr(&devrec->hw->phy->perm_extended_addr);
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@ -1054,6 +1007,7 @@ static int mrf24j40_probe(struct spi_device *spi)
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devrec->hw->flags = IEEE802154_HW_TX_OMIT_CKSUM | IEEE802154_HW_AFILT;
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mrf24j40_setup_tx_spi_messages(devrec);
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mrf24j40_setup_rx_spi_messages(devrec);
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devrec->regmap_short = devm_regmap_init_spi(spi,
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&mrf24j40_short_regmap);
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