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drm/nouveau/mmu: convert to new-style nvkm_subdev 

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2015-08-20 14:54:21 +10:00
parent 54dcadd5b6
commit c9582455ab
21 changed files with 389 additions and 480 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/nouveau/include/nvif/device.h
View File

@ -52,7 +52,7 @@ u64 nvif_device_time(struct nvif_device *);
})
#define nvxx_bios(a) nvxx_device(a)->bios
#define nvxx_fb(a) nvxx_device(a)->fb
#define nvxx_mmu(a) nvkm_mmu(nvxx_device(a))
#define nvxx_mmu(a) nvxx_device(a)->mmu
#define nvxx_bar(a) nvxx_device(a)->bar
#define nvxx_gpio(a) nvxx_device(a)->gpio
#define nvxx_clk(a) nvxx_device(a)->clk

71
drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h
View File

@ -39,62 +39,6 @@ struct nvkm_vm {
u32 lpde;
};
struct nvkm_mmu {
struct nvkm_subdev subdev;
u64 limit;
u8 dma_bits;
u32 pgt_bits;
u8 spg_shift;
u8 lpg_shift;
int (*create)(struct nvkm_mmu *, u64 offset, u64 length,
u64 mm_offset, struct lock_class_key *,
struct nvkm_vm **);
void (*map_pgt)(struct nvkm_gpuobj *pgd, u32 pde,
struct nvkm_memory *pgt[2]);
void (*map)(struct nvkm_vma *, struct nvkm_memory *,
struct nvkm_mem *, u32 pte, u32 cnt,
u64 phys, u64 delta);
void (*map_sg)(struct nvkm_vma *, struct nvkm_memory *,
struct nvkm_mem *, u32 pte, u32 cnt, dma_addr_t *);
void (*unmap)(struct nvkm_vma *, struct nvkm_memory *pgt,
u32 pte, u32 cnt);
void (*flush)(struct nvkm_vm *);
};
static inline struct nvkm_mmu *
nvkm_mmu(void *obj)
{
return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_MMU);
}
#define nvkm_mmu_create(p,e,o,i,f,d) \
nvkm_subdev_create((p), (e), (o), 0, (i), (f), (d))
#define nvkm_mmu_destroy(p) \
nvkm_subdev_destroy(&(p)->subdev)
#define nvkm_mmu_init(p) \
nvkm_subdev_init_old(&(p)->subdev)
#define nvkm_mmu_fini(p,s) \
nvkm_subdev_fini_old(&(p)->subdev, (s))
#define _nvkm_mmu_dtor _nvkm_subdev_dtor
#define _nvkm_mmu_init _nvkm_subdev_init
#define _nvkm_mmu_fini _nvkm_subdev_fini
extern struct nvkm_oclass nv04_mmu_oclass;
extern struct nvkm_oclass nv41_mmu_oclass;
extern struct nvkm_oclass nv44_mmu_oclass;
extern struct nvkm_oclass nv50_mmu_oclass;
extern struct nvkm_oclass gf100_mmu_oclass;
int nv04_vm_create(struct nvkm_mmu *, u64, u64, u64, struct lock_class_key *,
struct nvkm_vm **);
void nv04_mmu_dtor(struct nvkm_object *);
int nvkm_vm_create(struct nvkm_mmu *, u64 offset, u64 length, u64 mm_offset,
u32 block, struct lock_class_key *, struct nvkm_vm **);
int nvkm_vm_new(struct nvkm_device *, u64 offset, u64 length, u64 mm_offset,
struct lock_class_key *, struct nvkm_vm **);
int nvkm_vm_ref(struct nvkm_vm *, struct nvkm_vm **, struct nvkm_gpuobj *pgd);
@ -106,4 +50,19 @@ void nvkm_vm_map(struct nvkm_vma *, struct nvkm_mem *);
void nvkm_vm_map_at(struct nvkm_vma *, u64 offset, struct nvkm_mem *);
void nvkm_vm_unmap(struct nvkm_vma *);
void nvkm_vm_unmap_at(struct nvkm_vma *, u64 offset, u64 length);
struct nvkm_mmu {
const struct nvkm_mmu_func *func;
struct nvkm_subdev subdev;
u64 limit;
u8 dma_bits;
u8 lpg_shift;
};
int nv04_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);
int nv41_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);
int nv44_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);
int nv50_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);
int gf100_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);
#endif

140
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
View File

@ -84,7 +84,7 @@ nv4_chipset = {
.i2c = nv04_i2c_new,
.imem = nv04_instmem_new,
.mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
.mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
@ -104,7 +104,7 @@ nv5_chipset = {
.i2c = nv04_i2c_new,
.imem = nv04_instmem_new,
.mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
.mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
@ -125,7 +125,7 @@ nv10_chipset = {
.i2c = nv04_i2c_new,
.imem = nv04_instmem_new,
.mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
.mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
@ -144,7 +144,7 @@ nv11_chipset = {
.i2c = nv04_i2c_new,
.imem = nv04_instmem_new,
.mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
.mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
@ -165,7 +165,7 @@ nv15_chipset = {
.i2c = nv04_i2c_new,
.imem = nv04_instmem_new,
.mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
.mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
@ -186,7 +186,7 @@ nv17_chipset = {
.i2c = nv04_i2c_new,
.imem = nv04_instmem_new,
.mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
.mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
@ -207,7 +207,7 @@ nv18_chipset = {
.i2c = nv04_i2c_new,
.imem = nv04_instmem_new,
.mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
.mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
@ -228,7 +228,7 @@ nv1a_chipset = {
.i2c = nv04_i2c_new,
.imem = nv04_instmem_new,
.mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
.mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
@ -249,7 +249,7 @@ nv1f_chipset = {
.i2c = nv04_i2c_new,
.imem = nv04_instmem_new,
.mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
.mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
@ -270,7 +270,7 @@ nv20_chipset = {
.i2c = nv04_i2c_new,
.imem = nv04_instmem_new,
.mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
.mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
@ -291,7 +291,7 @@ nv25_chipset = {
.i2c = nv04_i2c_new,
.imem = nv04_instmem_new,
.mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
.mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
@ -312,7 +312,7 @@ nv28_chipset = {
.i2c = nv04_i2c_new,
.imem = nv04_instmem_new,
.mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
.mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
@ -333,7 +333,7 @@ nv2a_chipset = {
.i2c = nv04_i2c_new,
.imem = nv04_instmem_new,
.mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
.mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
@ -354,7 +354,7 @@ nv30_chipset = {
.i2c = nv04_i2c_new,
.imem = nv04_instmem_new,
.mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
.mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
@ -375,7 +375,7 @@ nv31_chipset = {
.i2c = nv04_i2c_new,
.imem = nv04_instmem_new,
.mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
.mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
@ -397,7 +397,7 @@ nv34_chipset = {
.i2c = nv04_i2c_new,
.imem = nv04_instmem_new,
.mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
.mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
@ -419,7 +419,7 @@ nv35_chipset = {
.i2c = nv04_i2c_new,
.imem = nv04_instmem_new,
.mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
.mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
@ -440,7 +440,7 @@ nv36_chipset = {
.i2c = nv04_i2c_new,
.imem = nv04_instmem_new,
.mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
.mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
@ -462,7 +462,7 @@ nv40_chipset = {
.i2c = nv04_i2c_new,
.imem = nv40_instmem_new,
.mc = nv40_mc_new,
// .mmu = nv04_mmu_new,
.mmu = nv04_mmu_new,
// .therm = nv40_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
@ -487,7 +487,7 @@ nv41_chipset = {
.i2c = nv04_i2c_new,
.imem = nv40_instmem_new,
.mc = nv40_mc_new,
// .mmu = nv41_mmu_new,
.mmu = nv41_mmu_new,
// .therm = nv40_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
@ -512,7 +512,7 @@ nv42_chipset = {
.i2c = nv04_i2c_new,
.imem = nv40_instmem_new,
.mc = nv40_mc_new,
// .mmu = nv41_mmu_new,
.mmu = nv41_mmu_new,
// .therm = nv40_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
@ -537,7 +537,7 @@ nv43_chipset = {
.i2c = nv04_i2c_new,
.imem = nv40_instmem_new,
.mc = nv40_mc_new,
// .mmu = nv41_mmu_new,
.mmu = nv41_mmu_new,
// .therm = nv40_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
@ -562,7 +562,7 @@ nv44_chipset = {
.i2c = nv04_i2c_new,
.imem = nv40_instmem_new,
.mc = nv44_mc_new,
// .mmu = nv44_mmu_new,
.mmu = nv44_mmu_new,
// .therm = nv40_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
@ -587,7 +587,7 @@ nv45_chipset = {
.i2c = nv04_i2c_new,
.imem = nv40_instmem_new,
.mc = nv40_mc_new,
// .mmu = nv04_mmu_new,
.mmu = nv04_mmu_new,
// .therm = nv40_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
@ -612,7 +612,7 @@ nv46_chipset = {
.i2c = nv04_i2c_new,
.imem = nv40_instmem_new,
.mc = nv44_mc_new,
// .mmu = nv44_mmu_new,
.mmu = nv44_mmu_new,
// .therm = nv40_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
@ -637,7 +637,7 @@ nv47_chipset = {
.i2c = nv04_i2c_new,
.imem = nv40_instmem_new,
.mc = nv40_mc_new,
// .mmu = nv41_mmu_new,
.mmu = nv41_mmu_new,
// .therm = nv40_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
@ -662,7 +662,7 @@ nv49_chipset = {
.i2c = nv04_i2c_new,
.imem = nv40_instmem_new,
.mc = nv40_mc_new,
// .mmu = nv41_mmu_new,
.mmu = nv41_mmu_new,
// .therm = nv40_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
@ -687,7 +687,7 @@ nv4a_chipset = {
.i2c = nv04_i2c_new,
.imem = nv40_instmem_new,
.mc = nv44_mc_new,
// .mmu = nv44_mmu_new,
.mmu = nv44_mmu_new,
// .therm = nv40_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
@ -712,7 +712,7 @@ nv4b_chipset = {
.i2c = nv04_i2c_new,
.imem = nv40_instmem_new,
.mc = nv40_mc_new,
// .mmu = nv41_mmu_new,
.mmu = nv41_mmu_new,
// .therm = nv40_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
@ -737,7 +737,7 @@ nv4c_chipset = {
.i2c = nv04_i2c_new,
.imem = nv40_instmem_new,
.mc = nv4c_mc_new,
// .mmu = nv44_mmu_new,
.mmu = nv44_mmu_new,
// .therm = nv40_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
@ -762,7 +762,7 @@ nv4e_chipset = {
.i2c = nv4e_i2c_new,
.imem = nv40_instmem_new,
.mc = nv4c_mc_new,
// .mmu = nv44_mmu_new,
.mmu = nv44_mmu_new,
// .therm = nv40_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
@ -789,7 +789,7 @@ nv50_chipset = {
.i2c = nv50_i2c_new,
.imem = nv50_instmem_new,
.mc = nv50_mc_new,
// .mmu = nv50_mmu_new,
.mmu = nv50_mmu_new,
// .mxm = nv50_mxm_new,
// .therm = nv50_therm_new,
// .timer = nv04_timer_new,
@ -815,7 +815,7 @@ nv63_chipset = {
.i2c = nv04_i2c_new,
.imem = nv40_instmem_new,
.mc = nv4c_mc_new,
// .mmu = nv44_mmu_new,
.mmu = nv44_mmu_new,
// .therm = nv40_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
@ -840,7 +840,7 @@ nv67_chipset = {
.i2c = nv04_i2c_new,
.imem = nv40_instmem_new,
.mc = nv4c_mc_new,
// .mmu = nv44_mmu_new,
.mmu = nv44_mmu_new,
// .therm = nv40_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
@ -865,7 +865,7 @@ nv68_chipset = {
.i2c = nv04_i2c_new,
.imem = nv40_instmem_new,
.mc = nv4c_mc_new,
// .mmu = nv44_mmu_new,
.mmu = nv44_mmu_new,
// .therm = nv40_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
@ -892,7 +892,7 @@ nv84_chipset = {
.i2c = nv50_i2c_new,
.imem = nv50_instmem_new,
.mc = nv50_mc_new,
// .mmu = nv50_mmu_new,
.mmu = nv50_mmu_new,
// .mxm = nv50_mxm_new,
// .therm = g84_therm_new,
// .timer = nv04_timer_new,
@ -923,7 +923,7 @@ nv86_chipset = {
.i2c = nv50_i2c_new,
.imem = nv50_instmem_new,
.mc = nv50_mc_new,
// .mmu = nv50_mmu_new,
.mmu = nv50_mmu_new,
// .mxm = nv50_mxm_new,
// .therm = g84_therm_new,
// .timer = nv04_timer_new,
@ -954,7 +954,7 @@ nv92_chipset = {
.i2c = nv50_i2c_new,
.imem = nv50_instmem_new,
.mc = nv50_mc_new,
// .mmu = nv50_mmu_new,
.mmu = nv50_mmu_new,
// .mxm = nv50_mxm_new,
// .therm = g84_therm_new,
// .timer = nv04_timer_new,
@ -985,7 +985,7 @@ nv94_chipset = {
.i2c = g94_i2c_new,
.imem = nv50_instmem_new,
.mc = g94_mc_new,
// .mmu = nv50_mmu_new,
.mmu = nv50_mmu_new,
// .mxm = nv50_mxm_new,
// .therm = g84_therm_new,
// .timer = nv04_timer_new,
@ -1018,7 +1018,7 @@ nv96_chipset = {
// .timer = nv04_timer_new,
.fb = g84_fb_new,
.imem = nv50_instmem_new,
// .mmu = nv50_mmu_new,
.mmu = nv50_mmu_new,
.bar = g84_bar_new,
// .volt = nv40_volt_new,
// .dma = nv50_dma_new,
@ -1049,7 +1049,7 @@ nv98_chipset = {
// .timer = nv04_timer_new,
.fb = g84_fb_new,
.imem = nv50_instmem_new,
// .mmu = nv50_mmu_new,
.mmu = nv50_mmu_new,
.bar = g84_bar_new,
// .volt = nv40_volt_new,
// .dma = nv50_dma_new,
@ -1078,7 +1078,7 @@ nva0_chipset = {
.i2c = nv50_i2c_new,
.imem = nv50_instmem_new,
.mc = g98_mc_new,
// .mmu = nv50_mmu_new,
.mmu = nv50_mmu_new,
// .mxm = nv50_mxm_new,
// .therm = g84_therm_new,
// .timer = nv04_timer_new,
@ -1109,7 +1109,7 @@ nva3_chipset = {
.i2c = g94_i2c_new,
.imem = nv50_instmem_new,
.mc = g98_mc_new,
// .mmu = nv50_mmu_new,
.mmu = nv50_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gt215_pmu_new,
// .therm = gt215_therm_new,
@ -1142,7 +1142,7 @@ nva5_chipset = {
.i2c = g94_i2c_new,
.imem = nv50_instmem_new,
.mc = g98_mc_new,
// .mmu = nv50_mmu_new,
.mmu = nv50_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gt215_pmu_new,
// .therm = gt215_therm_new,
@ -1174,7 +1174,7 @@ nva8_chipset = {
.i2c = g94_i2c_new,
.imem = nv50_instmem_new,
.mc = g98_mc_new,
// .mmu = nv50_mmu_new,
.mmu = nv50_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gt215_pmu_new,
// .therm = gt215_therm_new,
@ -1206,7 +1206,7 @@ nvaa_chipset = {
.i2c = g94_i2c_new,
.imem = nv50_instmem_new,
.mc = g98_mc_new,
// .mmu = nv50_mmu_new,
.mmu = nv50_mmu_new,
// .mxm = nv50_mxm_new,
// .therm = g84_therm_new,
// .timer = nv04_timer_new,
@ -1237,7 +1237,7 @@ nvac_chipset = {
.i2c = g94_i2c_new,
.imem = nv50_instmem_new,
.mc = g98_mc_new,
// .mmu = nv50_mmu_new,
.mmu = nv50_mmu_new,
// .mxm = nv50_mxm_new,
// .therm = g84_therm_new,
// .timer = nv04_timer_new,
@ -1268,7 +1268,7 @@ nvaf_chipset = {
.i2c = g94_i2c_new,
.imem = nv50_instmem_new,
.mc = g98_mc_new,
// .mmu = nv50_mmu_new,
.mmu = nv50_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gt215_pmu_new,
// .therm = gt215_therm_new,
@ -1302,7 +1302,7 @@ nvc0_chipset = {
.imem = nv50_instmem_new,
.ltc = gf100_ltc_new,
.mc = gf100_mc_new,
// .mmu = gf100_mmu_new,
.mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gf100_pmu_new,
// .therm = gt215_therm_new,
@ -1337,7 +1337,7 @@ nvc1_chipset = {
.imem = nv50_instmem_new,
.ltc = gf100_ltc_new,
.mc = gf106_mc_new,
// .mmu = gf100_mmu_new,
.mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gf100_pmu_new,
// .therm = gt215_therm_new,
@ -1371,7 +1371,7 @@ nvc3_chipset = {
.imem = nv50_instmem_new,
.ltc = gf100_ltc_new,
.mc = gf106_mc_new,
// .mmu = gf100_mmu_new,
.mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gf100_pmu_new,
// .therm = gt215_therm_new,
@ -1405,7 +1405,7 @@ nvc4_chipset = {
.imem = nv50_instmem_new,
.ltc = gf100_ltc_new,
.mc = gf100_mc_new,
// .mmu = gf100_mmu_new,
.mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gf100_pmu_new,
// .therm = gt215_therm_new,
@ -1440,7 +1440,7 @@ nvc8_chipset = {
.imem = nv50_instmem_new,
.ltc = gf100_ltc_new,
.mc = gf100_mc_new,
// .mmu = gf100_mmu_new,
.mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gf100_pmu_new,
// .therm = gt215_therm_new,
@ -1475,7 +1475,7 @@ nvce_chipset = {
.imem = nv50_instmem_new,
.ltc = gf100_ltc_new,
.mc = gf100_mc_new,
// .mmu = gf100_mmu_new,
.mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gf100_pmu_new,
// .therm = gt215_therm_new,
@ -1510,7 +1510,7 @@ nvcf_chipset = {
.imem = nv50_instmem_new,
.ltc = gf100_ltc_new,
.mc = gf106_mc_new,
// .mmu = gf100_mmu_new,
.mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gf100_pmu_new,
// .therm = gt215_therm_new,
@ -1544,7 +1544,7 @@ nvd7_chipset = {
.imem = nv50_instmem_new,
.ltc = gf100_ltc_new,
.mc = gf106_mc_new,
// .mmu = gf100_mmu_new,
.mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .therm = gf110_therm_new,
// .timer = nv04_timer_new,
@ -1576,7 +1576,7 @@ nvd9_chipset = {
.imem = nv50_instmem_new,
.ltc = gf100_ltc_new,
.mc = gf106_mc_new,
// .mmu = gf100_mmu_new,
.mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gf110_pmu_new,
// .therm = gf110_therm_new,
@ -1610,7 +1610,7 @@ nve4_chipset = {
.imem = nv50_instmem_new,
.ltc = gk104_ltc_new,
.mc = gf106_mc_new,
// .mmu = gf100_mmu_new,
.mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gk104_pmu_new,
// .therm = gf110_therm_new,
@ -1646,7 +1646,7 @@ nve6_chipset = {
.imem = nv50_instmem_new,
.ltc = gk104_ltc_new,
.mc = gf106_mc_new,
// .mmu = gf100_mmu_new,
.mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gk104_pmu_new,
// .therm = gf110_therm_new,
@ -1682,7 +1682,7 @@ nve7_chipset = {
.imem = nv50_instmem_new,
.ltc = gk104_ltc_new,
.mc = gf106_mc_new,
// .mmu = gf100_mmu_new,
.mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gf110_pmu_new,
// .therm = gf110_therm_new,
@ -1714,7 +1714,7 @@ nvea_chipset = {
.imem = gk20a_instmem_new,
.ltc = gk104_ltc_new,
.mc = gk20a_mc_new,
// .mmu = gf100_mmu_new,
.mmu = gf100_mmu_new,
// .pmu = gk20a_pmu_new,
// .timer = gk20a_timer_new,
// .volt = gk20a_volt_new,
@ -1742,7 +1742,7 @@ nvf0_chipset = {
.imem = nv50_instmem_new,
.ltc = gk104_ltc_new,
.mc = gf106_mc_new,
// .mmu = gf100_mmu_new,
.mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gk110_pmu_new,
// .therm = gf110_therm_new,
@ -1778,7 +1778,7 @@ nvf1_chipset = {
.imem = nv50_instmem_new,
.ltc = gk104_ltc_new,
.mc = gf106_mc_new,
// .mmu = gf100_mmu_new,
.mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gk110_pmu_new,
// .therm = gf110_therm_new,
@ -1814,7 +1814,7 @@ nv106_chipset = {
.imem = nv50_instmem_new,
.ltc = gk104_ltc_new,
.mc = gk20a_mc_new,
// .mmu = gf100_mmu_new,
.mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gk208_pmu_new,
// .therm = gf110_therm_new,
@ -1849,7 +1849,7 @@ nv108_chipset = {
.imem = nv50_instmem_new,
.ltc = gk104_ltc_new,
.mc = gk20a_mc_new,
// .mmu = gf100_mmu_new,
.mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gk208_pmu_new,
// .therm = gf110_therm_new,
@ -1884,7 +1884,7 @@ nv117_chipset = {
.imem = nv50_instmem_new,
.ltc = gm107_ltc_new,
.mc = gk20a_mc_new,
// .mmu = gf100_mmu_new,
.mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gk208_pmu_new,
// .therm = gm107_therm_new,
@ -1913,7 +1913,7 @@ nv124_chipset = {
.imem = nv50_instmem_new,
.ltc = gm107_ltc_new,
.mc = gk20a_mc_new,
// .mmu = gf100_mmu_new,
.mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gk208_pmu_new,
// .timer = gk20a_timer_new,
@ -1942,7 +1942,7 @@ nv126_chipset = {
.imem = nv50_instmem_new,
.ltc = gm107_ltc_new,
.mc = gk20a_mc_new,
// .mmu = gf100_mmu_new,
.mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gk208_pmu_new,
// .timer = gk20a_timer_new,
@ -1967,8 +1967,8 @@ nv12b_chipset = {
.imem = gk20a_instmem_new,
.ltc = gm107_ltc_new,
.mc = gk20a_mc_new,
// .mmu = gf100_mmu_new,
// .mmu = gf100_mmu_new,
.mmu = gf100_mmu_new,
.mmu = gf100_mmu_new,
// .timer = gk20a_timer_new,
// .ce[2] = gm204_ce2_new,
// .dma = gf119_dma_new,

9
drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c
View File

@ -31,7 +31,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
@ -50,7 +49,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
@ -69,7 +67,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
@ -87,7 +84,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
@ -106,7 +102,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
@ -124,7 +119,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
@ -142,7 +136,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
@ -161,7 +154,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
@ -179,7 +171,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;

8
drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c
View File

@ -31,7 +31,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
@ -51,7 +50,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
@ -71,7 +69,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
@ -89,7 +86,6 @@ gk104_identify(struct nvkm_device *device)
break;
case 0xea:
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
@ -103,7 +99,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk110_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
@ -123,7 +118,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk110_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
@ -143,7 +137,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
@ -162,7 +155,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;

5
drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
View File

@ -31,7 +31,6 @@ gm100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
#if 0
@ -61,7 +60,6 @@ gm100_identify(struct nvkm_device *device)
#endif
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
#if 0
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -88,7 +86,6 @@ gm100_identify(struct nvkm_device *device)
#endif
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
#if 0
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -109,9 +106,7 @@ gm100_identify(struct nvkm_device *device)
break;
case 0x12b:
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gm20b_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;

2
drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
View File

@ -29,7 +29,6 @@ nv04_identify(struct nvkm_device *device)
switch (device->chipset) {
case 0x04:
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass;
@ -38,7 +37,6 @@ nv04_identify(struct nvkm_device *device)
break;
case 0x05:
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass;

8
drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
View File

@ -29,14 +29,12 @@ nv10_identify(struct nvkm_device *device)
switch (device->chipset) {
case 0x10:
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x15:
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
@ -45,7 +43,6 @@ nv10_identify(struct nvkm_device *device)
break;
case 0x16:
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
@ -54,7 +51,6 @@ nv10_identify(struct nvkm_device *device)
break;
case 0x1a:
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
@ -63,7 +59,6 @@ nv10_identify(struct nvkm_device *device)
break;
case 0x11:
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
@ -72,7 +67,6 @@ nv10_identify(struct nvkm_device *device)
break;
case 0x17:
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
@ -81,7 +75,6 @@ nv10_identify(struct nvkm_device *device)
break;
case 0x1f:
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
@ -90,7 +83,6 @@ nv10_identify(struct nvkm_device *device)
break;
case 0x18:
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;

4
drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
View File

@ -29,7 +29,6 @@ nv20_identify(struct nvkm_device *device)
switch (device->chipset) {
case 0x20:
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
@ -38,7 +37,6 @@ nv20_identify(struct nvkm_device *device)
break;
case 0x25:
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
@ -47,7 +45,6 @@ nv20_identify(struct nvkm_device *device)
break;
case 0x28:
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
@ -56,7 +53,6 @@ nv20_identify(struct nvkm_device *device)
break;
case 0x2a:
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;

5
drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
View File

@ -29,7 +29,6 @@ nv30_identify(struct nvkm_device *device)
switch (device->chipset) {
case 0x30:
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
@ -38,7 +37,6 @@ nv30_identify(struct nvkm_device *device)
break;
case 0x35:
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
@ -47,7 +45,6 @@ nv30_identify(struct nvkm_device *device)
break;
case 0x31:
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
@ -57,7 +54,6 @@ nv30_identify(struct nvkm_device *device)
break;
case 0x36:
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
@ -67,7 +63,6 @@ nv30_identify(struct nvkm_device *device)
break;
case 0x34:
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;

16
drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
View File

@ -30,7 +30,6 @@ nv40_identify(struct nvkm_device *device)
case 0x40:
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@ -43,7 +42,6 @@ nv40_identify(struct nvkm_device *device)
case 0x41:
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@ -56,7 +54,6 @@ nv40_identify(struct nvkm_device *device)
case 0x42:
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@ -69,7 +66,6 @@ nv40_identify(struct nvkm_device *device)
case 0x43:
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@ -82,7 +78,6 @@ nv40_identify(struct nvkm_device *device)
case 0x45:
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@ -95,7 +90,6 @@ nv40_identify(struct nvkm_device *device)
case 0x47:
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@ -108,7 +102,6 @@ nv40_identify(struct nvkm_device *device)
case 0x49:
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@ -121,7 +114,6 @@ nv40_identify(struct nvkm_device *device)
case 0x4b:
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@ -134,7 +126,6 @@ nv40_identify(struct nvkm_device *device)
case 0x44:
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@ -147,7 +138,6 @@ nv40_identify(struct nvkm_device *device)
case 0x46:
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@ -160,7 +150,6 @@ nv40_identify(struct nvkm_device *device)
case 0x4a:
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@ -173,7 +162,6 @@ nv40_identify(struct nvkm_device *device)
case 0x4c:
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@ -186,7 +174,6 @@ nv40_identify(struct nvkm_device *device)
case 0x4e:
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@ -199,7 +186,6 @@ nv40_identify(struct nvkm_device *device)
case 0x63:
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@ -212,7 +198,6 @@ nv40_identify(struct nvkm_device *device)
case 0x67:
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@ -225,7 +210,6 @@ nv40_identify(struct nvkm_device *device)
case 0x68:
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;

14
drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
View File

@ -31,7 +31,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv50_fifo_oclass;
@ -45,7 +44,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
@ -62,7 +60,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
@ -79,7 +76,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
@ -96,7 +92,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
@ -113,7 +108,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
@ -130,7 +124,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
@ -147,7 +140,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
@ -164,7 +156,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
@ -181,7 +172,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
@ -198,7 +188,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
@ -217,7 +206,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
@ -235,7 +223,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
@ -253,7 +240,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;

4
drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c
View File

@ -81,7 +81,7 @@ int
nv04_dmaobj_new(struct nvkm_dma *dma, const struct nvkm_oclass *oclass,
void *data, u32 size, struct nvkm_dmaobj **pdmaobj)
{
struct nv04_mmu *mmu = nv04_mmu(dma);
struct nvkm_device *device = dma->engine.subdev.device;
struct nv04_dmaobj *dmaobj;
int ret;
@ -95,7 +95,7 @@ nv04_dmaobj_new(struct nvkm_dma *dma, const struct nvkm_oclass *oclass,
return ret;
if (dmaobj->base.target == NV_MEM_TARGET_VM) {
if (nv_object(mmu)->oclass == &nv04_mmu_oclass)
if (device->mmu->func == &nv04_mmu)
dmaobj->clone = true;
dmaobj->base.target = NV_MEM_TARGET_PCI;
dmaobj->base.access = NV_MEM_ACCESS_RW;

143
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c
View File

@ -21,10 +21,10 @@
*
* Authors: Ben Skeggs
*/
#include <subdev/mmu.h>
#include <subdev/fb.h>
#include "priv.h"
#include <core/gpuobj.h>
#include <subdev/fb.h>
void
nvkm_vm_map_at(struct nvkm_vma *vma, u64 delta, struct nvkm_mem *node)
@ -32,12 +32,12 @@ nvkm_vm_map_at(struct nvkm_vma *vma, u64 delta, struct nvkm_mem *node)
struct nvkm_vm *vm = vma->vm;
struct nvkm_mmu *mmu = vm->mmu;
struct nvkm_mm_node *r;
int big = vma->node->type != mmu->spg_shift;
int big = vma->node->type != mmu->func->spg_shift;
u32 offset = vma->node->offset + (delta >> 12);
u32 bits = vma->node->type - 12;
u32 pde = (offset >> mmu->pgt_bits) - vm->fpde;
u32 pte = (offset & ((1 << mmu->pgt_bits) - 1)) >> bits;
u32 max = 1 << (mmu->pgt_bits - bits);
u32 pde = (offset >> mmu->func->pgt_bits) - vm->fpde;
u32 pte = (offset & ((1 << mmu->func->pgt_bits) - 1)) >> bits;
u32 max = 1 << (mmu->func->pgt_bits - bits);
u32 end, len;
delta = 0;
@ -53,7 +53,7 @@ nvkm_vm_map_at(struct nvkm_vma *vma, u64 delta, struct nvkm_mem *node)
end = max;
len = end - pte;
mmu->map(vma, pgt, node, pte, len, phys, delta);
mmu->func->map(vma, pgt, node, pte, len, phys, delta);
num -= len;
pte += len;
@ -67,7 +67,7 @@ nvkm_vm_map_at(struct nvkm_vma *vma, u64 delta, struct nvkm_mem *node)
}
}
mmu->flush(vm);
mmu->func->flush(vm);
}
static void
@ -76,13 +76,13 @@ nvkm_vm_map_sg_table(struct nvkm_vma *vma, u64 delta, u64 length,
{
struct nvkm_vm *vm = vma->vm;
struct nvkm_mmu *mmu = vm->mmu;
int big = vma->node->type != mmu->spg_shift;
int big = vma->node->type != mmu->func->spg_shift;
u32 offset = vma->node->offset + (delta >> 12);
u32 bits = vma->node->type - 12;
u32 num = length >> vma->node->type;
u32 pde = (offset >> mmu->pgt_bits) - vm->fpde;
u32 pte = (offset & ((1 << mmu->pgt_bits) - 1)) >> bits;
u32 max = 1 << (mmu->pgt_bits - bits);
u32 pde = (offset >> mmu->func->pgt_bits) - vm->fpde;
u32 pte = (offset & ((1 << mmu->func->pgt_bits) - 1)) >> bits;
u32 max = 1 << (mmu->func->pgt_bits - bits);
unsigned m, sglen;
u32 end, len;
int i;
@ -100,7 +100,7 @@ nvkm_vm_map_sg_table(struct nvkm_vma *vma, u64 delta, u64 length,
for (m = 0; m < len; m++) {
dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
mmu->map_sg(vma, pgt, mem, pte, 1, &addr);
mmu->func->map_sg(vma, pgt, mem, pte, 1, &addr);
num--;
pte++;
@ -115,7 +115,7 @@ nvkm_vm_map_sg_table(struct nvkm_vma *vma, u64 delta, u64 length,
for (; m < sglen; m++) {
dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
mmu->map_sg(vma, pgt, mem, pte, 1, &addr);
mmu->func->map_sg(vma, pgt, mem, pte, 1, &addr);
num--;
pte++;
if (num == 0)
@ -125,7 +125,7 @@ nvkm_vm_map_sg_table(struct nvkm_vma *vma, u64 delta, u64 length,
}
finish:
mmu->flush(vm);
mmu->func->flush(vm);
}
static void
@ -135,13 +135,13 @@ nvkm_vm_map_sg(struct nvkm_vma *vma, u64 delta, u64 length,
struct nvkm_vm *vm = vma->vm;
struct nvkm_mmu *mmu = vm->mmu;
dma_addr_t *list = mem->pages;
int big = vma->node->type != mmu->spg_shift;
int big = vma->node->type != mmu->func->spg_shift;
u32 offset = vma->node->offset + (delta >> 12);
u32 bits = vma->node->type - 12;
u32 num = length >> vma->node->type;
u32 pde = (offset >> mmu->pgt_bits) - vm->fpde;
u32 pte = (offset & ((1 << mmu->pgt_bits) - 1)) >> bits;
u32 max = 1 << (mmu->pgt_bits - bits);
u32 pde = (offset >> mmu->func->pgt_bits) - vm->fpde;
u32 pte = (offset & ((1 << mmu->func->pgt_bits) - 1)) >> bits;
u32 max = 1 << (mmu->func->pgt_bits - bits);
u32 end, len;
while (num) {
@ -152,7 +152,7 @@ nvkm_vm_map_sg(struct nvkm_vma *vma, u64 delta, u64 length,
end = max;
len = end - pte;
mmu->map_sg(vma, pgt, mem, pte, len, list);
mmu->func->map_sg(vma, pgt, mem, pte, len, list);
num -= len;
pte += len;
@ -163,7 +163,7 @@ nvkm_vm_map_sg(struct nvkm_vma *vma, u64 delta, u64 length,
}
}
mmu->flush(vm);
mmu->func->flush(vm);
}
void
@ -183,13 +183,13 @@ nvkm_vm_unmap_at(struct nvkm_vma *vma, u64 delta, u64 length)
{
struct nvkm_vm *vm = vma->vm;
struct nvkm_mmu *mmu = vm->mmu;
int big = vma->node->type != mmu->spg_shift;
int big = vma->node->type != mmu->func->spg_shift;
u32 offset = vma->node->offset + (delta >> 12);
u32 bits = vma->node->type - 12;
u32 num = length >> vma->node->type;
u32 pde = (offset >> mmu->pgt_bits) - vm->fpde;
u32 pte = (offset & ((1 << mmu->pgt_bits) - 1)) >> bits;
u32 max = 1 << (mmu->pgt_bits - bits);
u32 pde = (offset >> mmu->func->pgt_bits) - vm->fpde;
u32 pte = (offset & ((1 << mmu->func->pgt_bits) - 1)) >> bits;
u32 max = 1 << (mmu->func->pgt_bits - bits);
u32 end, len;
while (num) {
@ -200,7 +200,7 @@ nvkm_vm_unmap_at(struct nvkm_vma *vma, u64 delta, u64 length)
end = max;
len = end - pte;
mmu->unmap(vma, pgt, pte, len);
mmu->func->unmap(vma, pgt, pte, len);
num -= len;
pte += len;
@ -210,7 +210,7 @@ nvkm_vm_unmap_at(struct nvkm_vma *vma, u64 delta, u64 length)
}
}
mmu->flush(vm);
mmu->func->flush(vm);
}
void
@ -237,7 +237,7 @@ nvkm_vm_unmap_pgt(struct nvkm_vm *vm, int big, u32 fpde, u32 lpde)
vpgt->mem[big] = NULL;
list_for_each_entry(vpgd, &vm->pgd_list, head) {
mmu->map_pgt(vpgd->obj, pde, vpgt->mem);
mmu->func->map_pgt(vpgd->obj, pde, vpgt->mem);
}
nvkm_memory_del(&pgt);
@ -250,11 +250,11 @@ nvkm_vm_map_pgt(struct nvkm_vm *vm, u32 pde, u32 type)
struct nvkm_mmu *mmu = vm->mmu;
struct nvkm_vm_pgt *vpgt = &vm->pgt[pde - vm->fpde];
struct nvkm_vm_pgd *vpgd;
int big = (type != mmu->spg_shift);
int big = (type != mmu->func->spg_shift);
u32 pgt_size;
int ret;
pgt_size = (1 << (mmu->pgt_bits + 12)) >> type;
pgt_size = (1 << (mmu->func->pgt_bits + 12)) >> type;
pgt_size *= 8;
ret = nvkm_memory_new(mmu->subdev.device, NVKM_MEM_TARGET_INST,
@ -263,7 +263,7 @@ nvkm_vm_map_pgt(struct nvkm_vm *vm, u32 pde, u32 type)
return ret;
list_for_each_entry(vpgd, &vm->pgd_list, head) {
mmu->map_pgt(vpgd->obj, pde, vpgt->mem);
mmu->func->map_pgt(vpgd->obj, pde, vpgt->mem);
}
vpgt->refcount[big]++;
@ -288,12 +288,12 @@ nvkm_vm_get(struct nvkm_vm *vm, u64 size, u32 page_shift, u32 access,
return ret;
}
fpde = (vma->node->offset >> mmu->pgt_bits);
lpde = (vma->node->offset + vma->node->length - 1) >> mmu->pgt_bits;
fpde = (vma->node->offset >> mmu->func->pgt_bits);
lpde = (vma->node->offset + vma->node->length - 1) >> mmu->func->pgt_bits;
for (pde = fpde; pde <= lpde; pde++) {
struct nvkm_vm_pgt *vpgt = &vm->pgt[pde - vm->fpde];
int big = (vma->node->type != mmu->spg_shift);
int big = (vma->node->type != mmu->func->spg_shift);
if (likely(vpgt->refcount[big])) {
vpgt->refcount[big]++;
@ -330,11 +330,11 @@ nvkm_vm_put(struct nvkm_vma *vma)
vm = vma->vm;
mmu = vm->mmu;
fpde = (vma->node->offset >> mmu->pgt_bits);
lpde = (vma->node->offset + vma->node->length - 1) >> mmu->pgt_bits;
fpde = (vma->node->offset >> mmu->func->pgt_bits);
lpde = (vma->node->offset + vma->node->length - 1) >> mmu->func->pgt_bits;
mutex_lock(&vm->mutex);
nvkm_vm_unmap_pgt(vm, vma->node->type != mmu->spg_shift, fpde, lpde);
nvkm_vm_unmap_pgt(vm, vma->node->type != mmu->func->spg_shift, fpde, lpde);
nvkm_mm_free(&vm->mm, &vma->node);
mutex_unlock(&vm->mutex);
@ -349,7 +349,7 @@ nvkm_vm_boot(struct nvkm_vm *vm, u64 size)
int ret;
ret = nvkm_memory_new(mmu->subdev.device, NVKM_MEM_TARGET_INST,
(size >> mmu->spg_shift) * 8, 0x1000, true, &pgt);
(size >> mmu->func->spg_shift) * 8, 0x1000, true, &pgt);
if (ret == 0) {
vm->pgt[0].refcount[0] = 1;
vm->pgt[0].mem[0] = pgt;
@ -376,8 +376,8 @@ nvkm_vm_create(struct nvkm_mmu *mmu, u64 offset, u64 length, u64 mm_offset,
INIT_LIST_HEAD(&vm->pgd_list);
vm->mmu = mmu;
kref_init(&vm->refcount);
vm->fpde = offset >> (mmu->pgt_bits + 12);
vm->lpde = (offset + length - 1) >> (mmu->pgt_bits + 12);
vm->fpde = offset >> (mmu->func->pgt_bits + 12);
vm->lpde = (offset + length - 1) >> (mmu->func->pgt_bits + 12);
vm->pgt = vzalloc((vm->lpde - vm->fpde + 1) * sizeof(*vm->pgt));
if (!vm->pgt) {
@ -402,8 +402,10 @@ int
nvkm_vm_new(struct nvkm_device *device, u64 offset, u64 length, u64 mm_offset,
struct lock_class_key *key, struct nvkm_vm **pvm)
{
struct nvkm_mmu *mmu = nvkm_mmu(device);
return mmu->create(mmu, offset, length, mm_offset, key, pvm);
struct nvkm_mmu *mmu = device->mmu;
if (!mmu->func->create)
return -EINVAL;
return mmu->func->create(mmu, offset, length, mm_offset, key, pvm);
}
static int
@ -424,7 +426,7 @@ nvkm_vm_link(struct nvkm_vm *vm, struct nvkm_gpuobj *pgd)
mutex_lock(&vm->mutex);
for (i = vm->fpde; i <= vm->lpde; i++)
mmu->map_pgt(pgd, i, vm->pgt[i - vm->fpde].mem);
mmu->func->map_pgt(pgd, i, vm->pgt[i - vm->fpde].mem);
list_add(&vpgd->head, &vm->pgd_list);
mutex_unlock(&vm->mutex);
return 0;
@ -483,3 +485,58 @@ nvkm_vm_ref(struct nvkm_vm *ref, struct nvkm_vm **ptr, struct nvkm_gpuobj *pgd)
*ptr = ref;
return 0;
}
static int
nvkm_mmu_oneinit(struct nvkm_subdev *subdev)
{
struct nvkm_mmu *mmu = nvkm_mmu(subdev);
if (mmu->func->oneinit)
return mmu->func->oneinit(mmu);
return 0;
}
static int
nvkm_mmu_init(struct nvkm_subdev *subdev)
{
struct nvkm_mmu *mmu = nvkm_mmu(subdev);
if (mmu->func->init)
mmu->func->init(mmu);
return 0;
}
static void *
nvkm_mmu_dtor(struct nvkm_subdev *subdev)
{
struct nvkm_mmu *mmu = nvkm_mmu(subdev);
if (mmu->func->dtor)
return mmu->func->dtor(mmu);
return mmu;
}
static const struct nvkm_subdev_func
nvkm_mmu = {
.dtor = nvkm_mmu_dtor,
.oneinit = nvkm_mmu_oneinit,
.init = nvkm_mmu_init,
};
void
nvkm_mmu_ctor(const struct nvkm_mmu_func *func, struct nvkm_device *device,
int index, struct nvkm_mmu *mmu)
{
nvkm_subdev_ctor(&nvkm_mmu, device, index, 0, &mmu->subdev);
mmu->func = func;
mmu->limit = func->limit;
mmu->dma_bits = func->dma_bits;
mmu->lpg_shift = func->lpg_shift;
}
int
nvkm_mmu_new_(const struct nvkm_mmu_func *func, struct nvkm_device *device,
int index, struct nvkm_mmu **pmmu)
{
if (!(*pmmu = kzalloc(sizeof(**pmmu), GFP_KERNEL)))
return -ENOMEM;
nvkm_mmu_ctor(func, device, index, *pmmu);
return 0;
}

64
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c
View File

@ -21,7 +21,8 @@
*
* Authors: Ben Skeggs
*/
#include <subdev/mmu.h>
#include "priv.h"
#include <subdev/fb.h>
#include <subdev/ltc.h>
#include <subdev/timer.h>
@ -160,7 +161,7 @@ gf100_vm_unmap(struct nvkm_vma *vma, struct nvkm_memory *pgt, u32 pte, u32 cnt)
static void
gf100_vm_flush(struct nvkm_vm *vm)
{
struct nvkm_mmu *mmu = (void *)vm->mmu;
struct nvkm_mmu *mmu = vm->mmu;
struct nvkm_device *device = mmu->subdev.device;
struct nvkm_vm_pgd *vpgd;
u32 type;
@ -169,7 +170,7 @@ gf100_vm_flush(struct nvkm_vm *vm)
if (atomic_read(&vm->engref[NVDEV_SUBDEV_BAR]))
type |= 0x00000004; /* HUB_ONLY */
mutex_lock(&nv_subdev(mmu)->mutex);
mutex_lock(&mmu->subdev.mutex);
list_for_each_entry(vpgd, &vm->pgd_list, head) {
/* looks like maybe a "free flush slots" counter, the
* faster you write to 0x100cbc to more it decreases
@ -188,7 +189,7 @@ gf100_vm_flush(struct nvkm_vm *vm)
break;
);
}
mutex_unlock(&nv_subdev(mmu)->mutex);
mutex_unlock(&mmu->subdev.mutex);
}
static int
@ -198,40 +199,23 @@ gf100_vm_create(struct nvkm_mmu *mmu, u64 offset, u64 length, u64 mm_offset,
return nvkm_vm_create(mmu, offset, length, mm_offset, 4096, key, pvm);
}
static int
gf100_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
struct nvkm_mmu *mmu;
int ret;
ret = nvkm_mmu_create(parent, engine, oclass, "VM", "mmu", &mmu);
*pobject = nv_object(mmu);
if (ret)
return ret;
mmu->limit = 1ULL << 40;
mmu->dma_bits = 40;
mmu->pgt_bits = 27 - 12;
mmu->spg_shift = 12;
mmu->lpg_shift = 17;
mmu->create = gf100_vm_create;
mmu->map_pgt = gf100_vm_map_pgt;
mmu->map = gf100_vm_map;
mmu->map_sg = gf100_vm_map_sg;
mmu->unmap = gf100_vm_unmap;
mmu->flush = gf100_vm_flush;
return 0;
}
struct nvkm_oclass
gf100_mmu_oclass = {
.handle = NV_SUBDEV(MMU, 0xc0),
.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gf100_mmu_ctor,
.dtor = _nvkm_mmu_dtor,
.init = _nvkm_mmu_init,
.fini = _nvkm_mmu_fini,
},
static const struct nvkm_mmu_func
gf100_mmu = {
.limit = (1ULL << 40),
.dma_bits = 40,
.pgt_bits = 27 - 12,
.spg_shift = 12,
.lpg_shift = 17,
.create = gf100_vm_create,
.map_pgt = gf100_vm_map_pgt,
.map = gf100_vm_map,
.map_sg = gf100_vm_map_sg,
.unmap = gf100_vm_unmap,
.flush = gf100_vm_flush,
};
int
gf100_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu)
{
return nvkm_mmu_new_(&gf100_mmu, device, index, pmmu);
}

85
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c
View File

@ -68,47 +68,18 @@ nv04_vm_flush(struct nvkm_vm *vm)
{
}
/*******************************************************************************
* VM object
******************************************************************************/
int
nv04_vm_create(struct nvkm_mmu *mmu, u64 offset, u64 length, u64 mmstart,
struct lock_class_key *key, struct nvkm_vm **pvm)
{
return -EINVAL;
}
/*******************************************************************************
* MMU subdev
******************************************************************************/
static int
nv04_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
nv04_mmu_oneinit(struct nvkm_mmu *base)
{
struct nvkm_device *device = (void *)parent;
struct nv04_mmu *mmu;
struct nv04_mmu *mmu = nv04_mmu(base);
struct nvkm_device *device = mmu->base.subdev.device;
struct nvkm_memory *dma;
int ret;
ret = nvkm_mmu_create(parent, engine, oclass, "PCIGART",
"mmu", &mmu);
*pobject = nv_object(mmu);
if (ret)
return ret;
mmu->base.create = nv04_vm_create;
mmu->base.limit = NV04_PDMA_SIZE;
mmu->base.dma_bits = 32;
mmu->base.pgt_bits = 32 - 12;
mmu->base.spg_shift = 12;
mmu->base.lpg_shift = 12;
mmu->base.map_sg = nv04_vm_map_sg;
mmu->base.unmap = nv04_vm_unmap;
mmu->base.flush = nv04_vm_flush;
ret = nvkm_vm_create(&mmu->base, 0, NV04_PDMA_SIZE, 0, 4096, NULL,
&mmu->vm);
if (ret)
@ -129,28 +100,50 @@ nv04_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
return 0;
}
void
nv04_mmu_dtor(struct nvkm_object *object)
void *
nv04_mmu_dtor(struct nvkm_mmu *base)
{
struct nv04_mmu *mmu = (void *)object;
struct nv04_mmu *mmu = nv04_mmu(base);
struct nvkm_device *device = mmu->base.subdev.device;
if (mmu->vm) {
nvkm_memory_del(&mmu->vm->pgt[0].mem[0]);
nvkm_vm_ref(NULL, &mmu->vm, NULL);
}
if (mmu->nullp) {
pci_free_consistent(nv_device(mmu)->pdev, 16 * 1024,
pci_free_consistent(device->pdev, 16 * 1024,
mmu->nullp, mmu->null);
}
nvkm_mmu_destroy(&mmu->base);
return mmu;
}
struct nvkm_oclass
nv04_mmu_oclass = {
.handle = NV_SUBDEV(MMU, 0x04),
.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_mmu_ctor,
.dtor = nv04_mmu_dtor,
.init = _nvkm_mmu_init,
.fini = _nvkm_mmu_fini,
},
int
nv04_mmu_new_(const struct nvkm_mmu_func *func, struct nvkm_device *device,
int index, struct nvkm_mmu **pmmu)
{
struct nv04_mmu *mmu;
if (!(mmu = kzalloc(sizeof(*mmu), GFP_KERNEL)))
return -ENOMEM;
*pmmu = &mmu->base;
nvkm_mmu_ctor(func, device, index, &mmu->base);
return 0;
}
const struct nvkm_mmu_func
nv04_mmu = {
.oneinit = nv04_mmu_oneinit,
.dtor = nv04_mmu_dtor,
.limit = NV04_PDMA_SIZE,
.dma_bits = 32,
.pgt_bits = 32 - 12,
.spg_shift = 12,
.lpg_shift = 12,
.map_sg = nv04_vm_map_sg,
.unmap = nv04_vm_unmap,
.flush = nv04_vm_flush,
};
int
nv04_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu)
{
return nv04_mmu_new_(&nv04_mmu, device, index, pmmu);
}

13
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.h
View File

@ -1,6 +1,7 @@
#ifndef __NV04_MMU_PRIV__
#define __NV04_MMU_PRIV__
#include <subdev/mmu.h>
#define nv04_mmu(p) container_of((p), struct nv04_mmu, base)
#include "priv.h"
struct nv04_mmu {
struct nvkm_mmu base;
@ -9,9 +10,9 @@ struct nv04_mmu {
void *nullp;
};
static inline struct nv04_mmu *
nv04_mmu(void *obj)
{
return (void *)nvkm_mmu(obj);
}
int nv04_mmu_new_(const struct nvkm_mmu_func *, struct nvkm_device *,
int index, struct nvkm_mmu **);
void *nv04_mmu_dtor(struct nvkm_mmu *);
extern const struct nvkm_mmu_func nv04_mmu;
#endif

84
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c
View File

@ -71,14 +71,14 @@ nv41_vm_flush(struct nvkm_vm *vm)
struct nv04_mmu *mmu = nv04_mmu(vm->mmu);
struct nvkm_device *device = mmu->base.subdev.device;
mutex_lock(&nv_subdev(mmu)->mutex);
mutex_lock(&mmu->base.subdev.mutex);
nvkm_wr32(device, 0x100810, 0x00000022);
nvkm_msec(device, 2000,
if (nvkm_rd32(device, 0x100810) & 0x00000020)
break;
);
nvkm_wr32(device, 0x100810, 0x00000000);
mutex_unlock(&nv_subdev(mmu)->mutex);
mutex_unlock(&mmu->base.subdev.mutex);
}
/*******************************************************************************
@ -86,36 +86,12 @@ nv41_vm_flush(struct nvkm_vm *vm)
******************************************************************************/
static int
nv41_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
nv41_mmu_oneinit(struct nvkm_mmu *base)
{
struct nvkm_device *device = nv_device(parent);
struct nv04_mmu *mmu;
struct nv04_mmu *mmu = nv04_mmu(base);
struct nvkm_device *device = mmu->base.subdev.device;
int ret;
if (pci_find_capability(device->pdev, PCI_CAP_ID_AGP) ||
!nvkm_boolopt(device->cfgopt, "NvPCIE", true)) {
return nvkm_object_old(parent, engine, &nv04_mmu_oclass,
data, size, pobject);
}
ret = nvkm_mmu_create(parent, engine, oclass, "PCIEGART",
"mmu", &mmu);
*pobject = nv_object(mmu);
if (ret)
return ret;
mmu->base.create = nv04_vm_create;
mmu->base.limit = NV41_GART_SIZE;
mmu->base.dma_bits = 39;
mmu->base.pgt_bits = 32 - 12;
mmu->base.spg_shift = 12;
mmu->base.lpg_shift = 12;
mmu->base.map_sg = nv41_vm_map_sg;
mmu->base.unmap = nv41_vm_unmap;
mmu->base.flush = nv41_vm_flush;
ret = nvkm_vm_create(&mmu->base, 0, NV41_GART_SIZE, 0, 4096, NULL,
&mmu->vm);
if (ret)
@ -125,37 +101,41 @@ nv41_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
(NV41_GART_SIZE / NV41_GART_PAGE) * 4, 16, true,
&mmu->vm->pgt[0].mem[0]);
mmu->vm->pgt[0].refcount[0] = 1;
if (ret)
return ret;
return 0;
return ret;
}
static int
nv41_mmu_init(struct nvkm_object *object)
static void
nv41_mmu_init(struct nvkm_mmu *base)
{
struct nv04_mmu *mmu = (void *)object;
struct nv04_mmu *mmu = nv04_mmu(base);
struct nvkm_device *device = mmu->base.subdev.device;
struct nvkm_memory *dma = mmu->vm->pgt[0].mem[0];
int ret;
ret = nvkm_mmu_init(&mmu->base);
if (ret)
return ret;
nvkm_wr32(device, 0x100800, 0x00000002 | nvkm_memory_addr(dma));
nvkm_mask(device, 0x10008c, 0x00000100, 0x00000100);
nvkm_wr32(device, 0x100820, 0x00000000);
return 0;
}
struct nvkm_oclass
nv41_mmu_oclass = {
.handle = NV_SUBDEV(MMU, 0x41),
.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv41_mmu_ctor,
.dtor = nv04_mmu_dtor,
.init = nv41_mmu_init,
.fini = _nvkm_mmu_fini,
},
static const struct nvkm_mmu_func
nv41_mmu = {
.dtor = nv04_mmu_dtor,
.oneinit = nv41_mmu_oneinit,
.init = nv41_mmu_init,
.limit = NV41_GART_SIZE,
.dma_bits = 39,
.pgt_bits = 32 - 12,
.spg_shift = 12,
.lpg_shift = 12,
.map_sg = nv41_vm_map_sg,
.unmap = nv41_vm_unmap,
.flush = nv41_vm_flush,
};
int
nv41_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu)
{
if (pci_find_capability(device->pdev, PCI_CAP_ID_AGP) ||
!nvkm_boolopt(device->cfgopt, "NvPCIE", true))
return nv04_mmu_new(device, index, pmmu);
return nv04_mmu_new_(&nv41_mmu, device, index, pmmu);
}

79
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c
View File

@ -159,36 +159,12 @@ nv44_vm_flush(struct nvkm_vm *vm)
******************************************************************************/
static int
nv44_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
nv44_mmu_oneinit(struct nvkm_mmu *base)
{
struct nvkm_device *device = nv_device(parent);
struct nv04_mmu *mmu;
struct nv04_mmu *mmu = nv04_mmu(base);
struct nvkm_device *device = mmu->base.subdev.device;
int ret;
if (pci_find_capability(device->pdev, PCI_CAP_ID_AGP) ||
!nvkm_boolopt(device->cfgopt, "NvPCIE", true)) {
return nvkm_object_old(parent, engine, &nv04_mmu_oclass,
data, size, pobject);
}
ret = nvkm_mmu_create(parent, engine, oclass, "PCIEGART",
"mmu", &mmu);
*pobject = nv_object(mmu);
if (ret)
return ret;
mmu->base.create = nv04_vm_create;
mmu->base.limit = NV44_GART_SIZE;
mmu->base.dma_bits = 39;
mmu->base.pgt_bits = 32 - 12;
mmu->base.spg_shift = 12;
mmu->base.lpg_shift = 12;
mmu->base.map_sg = nv44_vm_map_sg;
mmu->base.unmap = nv44_vm_unmap;
mmu->base.flush = nv44_vm_flush;
mmu->nullp = pci_alloc_consistent(device->pdev, 16 * 1024, &mmu->null);
if (!mmu->nullp) {
nvkm_warn(&mmu->base.subdev, "unable to allocate dummy pages\n");
@ -205,24 +181,16 @@ nv44_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
512 * 1024, true,
&mmu->vm->pgt[0].mem[0]);
mmu->vm->pgt[0].refcount[0] = 1;
if (ret)
return ret;
return 0;
return ret;
}
static int
nv44_mmu_init(struct nvkm_object *object)
static void
nv44_mmu_init(struct nvkm_mmu *base)
{
struct nv04_mmu *mmu = (void *)object;
struct nv04_mmu *mmu = nv04_mmu(base);
struct nvkm_device *device = mmu->base.subdev.device;
struct nvkm_memory *gart = mmu->vm->pgt[0].mem[0];
u32 addr;
int ret;
ret = nvkm_mmu_init(&mmu->base);
if (ret)
return ret;
/* calculate vram address of this PRAMIN block, object must be
* allocated on 512KiB alignment, and not exceed a total size
@ -239,16 +207,29 @@ nv44_mmu_init(struct nvkm_object *object)
nvkm_wr32(device, 0x100820, 0x00000000);
nvkm_wr32(device, 0x10082c, 0x00000001);
nvkm_wr32(device, 0x100800, addr | 0x00000010);
return 0;
}
struct nvkm_oclass
nv44_mmu_oclass = {
.handle = NV_SUBDEV(MMU, 0x44),
.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv44_mmu_ctor,
.dtor = nv04_mmu_dtor,
.init = nv44_mmu_init,
.fini = _nvkm_mmu_fini,
},
static const struct nvkm_mmu_func
nv44_mmu = {
.dtor = nv04_mmu_dtor,
.oneinit = nv44_mmu_oneinit,
.init = nv44_mmu_init,
.limit = NV44_GART_SIZE,
.dma_bits = 39,
.pgt_bits = 32 - 12,
.spg_shift = 12,
.lpg_shift = 12,
.map_sg = nv44_vm_map_sg,
.unmap = nv44_vm_unmap,
.flush = nv44_vm_flush,
};
int
nv44_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu)
{
if (pci_find_capability(device->pdev, PCI_CAP_ID_AGP) ||
!nvkm_boolopt(device->cfgopt, "NvPCIE", true))
return nv04_mmu_new(device, index, pmmu);
return nv04_mmu_new_(&nv44_mmu, device, index, pmmu);
}

74
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c
View File

@ -21,7 +21,8 @@
*
* Authors: Ben Skeggs
*/
#include <subdev/mmu.h>
#include "priv.h"
#include <subdev/fb.h>
#include <subdev/timer.h>
@ -155,10 +156,9 @@ nv50_vm_unmap(struct nvkm_vma *vma, struct nvkm_memory *pgt, u32 pte, u32 cnt)
static void
nv50_vm_flush(struct nvkm_vm *vm)
{
struct nvkm_mmu *mmu = (void *)vm->mmu;
struct nvkm_mmu *mmu = vm->mmu;
struct nvkm_subdev *subdev = &mmu->subdev;
struct nvkm_device *device = subdev->device;
struct nvkm_engine *engine;
int i, vme;
mutex_lock(&subdev->mutex);
@ -167,10 +167,13 @@ nv50_vm_flush(struct nvkm_vm *vm)
continue;
/* unfortunate hw bug workaround... */
engine = nvkm_engine(mmu, i);
if (engine && engine->tlb_flush) {
engine->tlb_flush(engine);
continue;
if (i == NVDEV_ENGINE_GR) {
struct nvkm_engine *engine =
nvkm_device_engine(device, i);
if (engine && engine->tlb_flush) {
engine->tlb_flush(engine);
continue;
}
}
switch (i) {
@ -203,47 +206,30 @@ static int
nv50_vm_create(struct nvkm_mmu *mmu, u64 offset, u64 length, u64 mm_offset,
struct lock_class_key *key, struct nvkm_vm **pvm)
{
u32 block = (1 << (mmu->pgt_bits + 12));
u32 block = (1 << (mmu->func->pgt_bits + 12));
if (block > length)
block = length;
return nvkm_vm_create(mmu, offset, length, mm_offset, block, key, pvm);
}
static int
nv50_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
struct nvkm_mmu *mmu;
int ret;
ret = nvkm_mmu_create(parent, engine, oclass, "VM", "mmu", &mmu);
*pobject = nv_object(mmu);
if (ret)
return ret;
mmu->limit = 1ULL << 40;
mmu->dma_bits = 40;
mmu->pgt_bits = 29 - 12;
mmu->spg_shift = 12;
mmu->lpg_shift = 16;
mmu->create = nv50_vm_create;
mmu->map_pgt = nv50_vm_map_pgt;
mmu->map = nv50_vm_map;
mmu->map_sg = nv50_vm_map_sg;
mmu->unmap = nv50_vm_unmap;
mmu->flush = nv50_vm_flush;
return 0;
}
struct nvkm_oclass
nv50_mmu_oclass = {
.handle = NV_SUBDEV(MMU, 0x50),
.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_mmu_ctor,
.dtor = _nvkm_mmu_dtor,
.init = _nvkm_mmu_init,
.fini = _nvkm_mmu_fini,
},
static const struct nvkm_mmu_func
nv50_mmu = {
.limit = (1ULL << 40),
.dma_bits = 40,
.pgt_bits = 29 - 12,
.spg_shift = 12,
.lpg_shift = 16,
.create = nv50_vm_create,
.map_pgt = nv50_vm_map_pgt,
.map = nv50_vm_map,
.map_sg = nv50_vm_map_sg,
.unmap = nv50_vm_unmap,
.flush = nv50_vm_flush,
};
int
nv50_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu)
{
return nvkm_mmu_new_(&nv50_mmu, device, index, pmmu);
}

39
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/priv.h Normal file
View File

@ -0,0 +1,39 @@
#ifndef __NVKM_MMU_PRIV_H__
#define __NVKM_MMU_PRIV_H__
#define nvkm_mmu(p) container_of((p), struct nvkm_mmu, subdev)
#include <subdev/mmu.h>
void nvkm_mmu_ctor(const struct nvkm_mmu_func *, struct nvkm_device *,
int index, struct nvkm_mmu *);
int nvkm_mmu_new_(const struct nvkm_mmu_func *, struct nvkm_device *,
int index, struct nvkm_mmu **);
struct nvkm_mmu_func {
void *(*dtor)(struct nvkm_mmu *);
int (*oneinit)(struct nvkm_mmu *);
void (*init)(struct nvkm_mmu *);
u64 limit;
u8 dma_bits;
u32 pgt_bits;
u8 spg_shift;
u8 lpg_shift;
int (*create)(struct nvkm_mmu *, u64 offset, u64 length, u64 mm_offset,
struct lock_class_key *, struct nvkm_vm **);
void (*map_pgt)(struct nvkm_gpuobj *pgd, u32 pde,
struct nvkm_memory *pgt[2]);
void (*map)(struct nvkm_vma *, struct nvkm_memory *,
struct nvkm_mem *, u32 pte, u32 cnt,
u64 phys, u64 delta);
void (*map_sg)(struct nvkm_vma *, struct nvkm_memory *,
struct nvkm_mem *, u32 pte, u32 cnt, dma_addr_t *);
void (*unmap)(struct nvkm_vma *, struct nvkm_memory *pgt,
u32 pte, u32 cnt);
void (*flush)(struct nvkm_vm *);
};
int nvkm_vm_create(struct nvkm_mmu *, u64, u64, u64, u32,
struct lock_class_key *, struct nvkm_vm **);
#endif