mirror of https://gitee.com/openkylin/linux.git
dmaengine: dw: fix a typo for bitfields of CTL_LO
The offset of SINC should be 9, not 7, here fix this typo. Signed-off-by: Jie Yang <yang.jie@intel.com> Acked-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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@ -150,7 +150,7 @@ enum dw_dma_msize {
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#define DWC_CTLL_DST_INC (0<<7) /* DAR update/not */
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#define DWC_CTLL_DST_INC (0<<7) /* DAR update/not */
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#define DWC_CTLL_DST_DEC (1<<7)
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#define DWC_CTLL_DST_DEC (1<<7)
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#define DWC_CTLL_DST_FIX (2<<7)
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#define DWC_CTLL_DST_FIX (2<<7)
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#define DWC_CTLL_SRC_INC (0<<7) /* SAR update/not */
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#define DWC_CTLL_SRC_INC (0<<9) /* SAR update/not */
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#define DWC_CTLL_SRC_DEC (1<<9)
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#define DWC_CTLL_SRC_DEC (1<<9)
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#define DWC_CTLL_SRC_FIX (2<<9)
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#define DWC_CTLL_SRC_FIX (2<<9)
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#define DWC_CTLL_DST_MSIZE(n) ((n)<<11) /* burst, #elements */
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#define DWC_CTLL_DST_MSIZE(n) ((n)<<11) /* burst, #elements */
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