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clk: intel: Improve locking in the driver 

Remove/reduce unnecessary spin locking of the code.

Signed-off-by: Rahul Tanwar <rahul.tanwar@linux.intel.com>
Link: https://lore.kernel.org/r/79c0f5f9f5bc512a7e2b5f3c91f6341f28b5854c.1594880946.git.rahul.tanwar@linux.intel.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Rahul Tanwar 2020-07-16 14:30:31 +08:00 committed by Stephen Boyd
parent 8529fc0aaa
commit c9e28fe649
1 changed files with 5 additions and 12 deletions
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17
drivers/clk/x86/clk-cgu.c
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@ -420,18 +420,14 @@ lgm_clk_ddiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
{ {
struct lgm_clk_ddiv *ddiv = to_lgm_clk_ddiv(hw); struct lgm_clk_ddiv *ddiv = to_lgm_clk_ddiv(hw);
unsigned int div0, div1, exdiv; unsigned int div0, div1, exdiv;
unsigned long flags;
u64 prate; u64 prate;
spin_lock_irqsave(&ddiv->lock, flags);
div0 = lgm_get_clk_val(ddiv->membase, ddiv->reg, div0 = lgm_get_clk_val(ddiv->membase, ddiv->reg,
ddiv->shift0, ddiv->width0) + 1; ddiv->shift0, ddiv->width0) + 1;
div1 = lgm_get_clk_val(ddiv->membase, ddiv->reg, div1 = lgm_get_clk_val(ddiv->membase, ddiv->reg,
ddiv->shift1, ddiv->width1) + 1; ddiv->shift1, ddiv->width1) + 1;
exdiv = lgm_get_clk_val(ddiv->membase, ddiv->reg, exdiv = lgm_get_clk_val(ddiv->membase, ddiv->reg,
ddiv->shift2, ddiv->width2); ddiv->shift2, ddiv->width2);
spin_unlock_irqrestore(&ddiv->lock, flags);
prate = (u64)parent_rate; prate = (u64)parent_rate;
do_div(prate, div0); do_div(prate, div0);
do_div(prate, div1); do_div(prate, div1);
@ -548,24 +544,21 @@ lgm_clk_ddiv_round_rate(struct clk_hw *hw, unsigned long rate,
div = div * 2; div = div * 2;
div = DIV_ROUND_CLOSEST_ULL((u64)div, 5); div = DIV_ROUND_CLOSEST_ULL((u64)div, 5);
} }
if (div <= 0) {
spin_unlock_irqrestore(&ddiv->lock, flags); spin_unlock_irqrestore(&ddiv->lock, flags);
if (div <= 0)
return *prate; return *prate;
}
if (lgm_clk_get_ddiv_val(div, &ddiv1, &ddiv2) != 0) { if (lgm_clk_get_ddiv_val(div, &ddiv1, &ddiv2) != 0)
if (lgm_clk_get_ddiv_val(div + 1, &ddiv1, &ddiv2) != 0) { if (lgm_clk_get_ddiv_val(div + 1, &ddiv1, &ddiv2) != 0)
spin_unlock_irqrestore(&ddiv->lock, flags);
return -EINVAL; return -EINVAL;
}
}
rate64 = *prate; rate64 = *prate;
do_div(rate64, ddiv1); do_div(rate64, ddiv1);
do_div(rate64, ddiv2); do_div(rate64, ddiv2);
/* if predivide bit is enabled, modify rounded rate by factor of 2.5 */ /* if predivide bit is enabled, modify rounded rate by factor of 2.5 */
spin_lock_irqsave(&ddiv->lock, flags);
if (lgm_get_clk_val(ddiv->membase, ddiv->reg, ddiv->shift2, 1)) { if (lgm_get_clk_val(ddiv->membase, ddiv->reg, ddiv->shift2, 1)) {
rate64 = rate64 * 2; rate64 = rate64 * 2;
rate64 = DIV_ROUND_CLOSEST_ULL(rate64, 5); rate64 = DIV_ROUND_CLOSEST_ULL(rate64, 5);