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drm/i915: Always write both TILEOFF and LINOFF plane registers 

Reduce the clutter in the sprite update functions by writing
both TILEOFF and LINOFF registers unconditionally. We already
did this for primary planes so might as well do it for the
sprites too.

There is no harm in writing both registers. Which one gets
used depends on the tilimg mode selected in the plane control
registers.

It might even make sense to clear the register that won't
get used. That could make register dumps a little easier to
parse. But I'm not sure it's worth the extra hassle.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181108150955.23948-1-ville.syrjala@linux.intel.com
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> #irc
This commit is contained in:
Ville Syrjälä 2018-11-08 17:09:55 +02:00
parent 6bd36e0822
commit ca0026790e
1 changed files with 7 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
drivers/gpu/drm/i915/intel_sprite.c
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@ -789,7 +789,6 @@ vlv_update_plane(struct intel_plane *plane,
const struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
const struct drm_framebuffer *fb = plane_state->base.fb;
enum pipe pipe = plane->pipe;
enum plane_id plane_id = plane->id;
u32 sprctl = plane_state->ctl;
@ -826,9 +825,7 @@ vlv_update_plane(struct intel_plane *plane,
plane_state->color_plane[0].stride);
I915_WRITE_FW(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x);
if (fb->modifier == I915_FORMAT_MOD_X_TILED)
I915_WRITE_FW(SPTILEOFF(pipe, plane_id), (y << 16) | x);
else
I915_WRITE_FW(SPLINOFF(pipe, plane_id), linear_offset);
I915_WRITE_FW(SPCONSTALPHA(pipe, plane_id), 0);
@ -947,7 +944,6 @@ ivb_update_plane(struct intel_plane *plane,
const struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
const struct drm_framebuffer *fb = plane_state->base.fb;
enum pipe pipe = plane->pipe;
u32 sprctl = plane_state->ctl, sprscale = 0;
u32 sprsurf_offset = plane_state->color_plane[0].offset;
@ -987,12 +983,12 @@ ivb_update_plane(struct intel_plane *plane,
/* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
* register */
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
I915_WRITE_FW(SPROFFSET(pipe), (y << 16) | x);
else if (fb->modifier == I915_FORMAT_MOD_X_TILED)
} else {
I915_WRITE_FW(SPRTILEOFF(pipe), (y << 16) | x);
else
I915_WRITE_FW(SPRLINOFF(pipe), linear_offset);
}
I915_WRITE_FW(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
if (IS_IVYBRIDGE(dev_priv))
@ -1116,7 +1112,6 @@ g4x_update_plane(struct intel_plane *plane,
const struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
const struct drm_framebuffer *fb = plane_state->base.fb;
enum pipe pipe = plane->pipe;
u32 dvscntr = plane_state->ctl, dvsscale = 0;
u32 dvssurf_offset = plane_state->color_plane[0].offset;
@ -1154,9 +1149,7 @@ g4x_update_plane(struct intel_plane *plane,
I915_WRITE_FW(DVSSTRIDE(pipe), plane_state->color_plane[0].stride);
I915_WRITE_FW(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
if (fb->modifier == I915_FORMAT_MOD_X_TILED)
I915_WRITE_FW(DVSTILEOFF(pipe), (y << 16) | x);
else
I915_WRITE_FW(DVSLINOFF(pipe), linear_offset);
I915_WRITE_FW(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);