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x86/ioapic: Refactor the delay logic in timer_irq_works() 

timer_irq_works() is used to detects the timer IRQs. It calls mdelay(10) to
delay ten ticks and check whether the timer IRQ work or not.

mdelay() depends on the loops_per_jiffy which is set up in
calibrate_delay(), but the delay calibration depends on a working timer
interrupt, which causes a chicken and egg problem.

The correct solution is to set up the interrupt mode and making sure that
the timer interrupt is delivered correctly before invoking calibrate_delay().
That means that mdelay() cannot be used in timer_irq_works(). 

Provide helper functions to make a rough delay estimate which is good enough
to prove that the timer interrupt is working. Either use TSC or a simple
delay loop and assume that 4GHz is the maximum CPU frequency to base the
delay calculation on.

Signed-off-by: Dou Liyang <douly.fnst@cn.fujitsu.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: yinghai@kernel.org
Cc: bhe@redhat.com
Link: https://lkml.kernel.org/r/1505293975-26005-9-git-send-email-douly.fnst@cn.fujitsu.com
This commit is contained in:
Dou Liyang 2017-09-13 17:12:51 +08:00 committed by Thomas Gleixner
parent 0c759131ae
commit ca7c6076ba
1 changed files with 43 additions and 2 deletions
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45
arch/x86/kernel/apic/io_apic.c
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@ -1585,6 +1585,43 @@ static int __init notimercheck(char *s)
} }
__setup("no_timer_check", notimercheck); __setup("no_timer_check", notimercheck);
static void __init delay_with_tsc(void)
{
unsigned long long start, now;
unsigned long end = jiffies + 4;
start = rdtsc();
/*
* We don't know the TSC frequency yet, but waiting for
* 40000000000/HZ TSC cycles is safe:
* 4 GHz == 10 jiffies
* 1 GHz == 40 jiffies
*/
do {
rep_nop();
now = rdtsc();
} while ((now - start) < 40000000000UL / HZ &&
time_before_eq(jiffies, end));
}
static void __init delay_without_tsc(void)
{
unsigned long end = jiffies + 4;
int band = 1;
/*
* We don't know any frequency yet, but waiting for
* 40940000000/HZ cycles is safe:
* 4 GHz == 10 jiffies
* 1 GHz == 40 jiffies
* 1 << 1 + 1 << 2 +...+ 1 << 11 = 4094
*/
do {
__delay(((1U << band++) * 10000000UL) / HZ);
} while (band < 12 && time_before_eq(jiffies, end));
}
/* /*
* There is a nasty bug in some older SMP boards, their mptable lies * There is a nasty bug in some older SMP boards, their mptable lies
* about the timer IRQ. We do the following to work around the situation: * about the timer IRQ. We do the following to work around the situation:
@ -1603,8 +1640,12 @@ static int __init timer_irq_works(void)
local_save_flags(flags); local_save_flags(flags);
local_irq_enable(); local_irq_enable();
/* Let ten ticks pass... */
mdelay((10 * 1000) / HZ); if (boot_cpu_has(X86_FEATURE_TSC))
delay_with_tsc();
else
delay_without_tsc();
local_irq_restore(flags); local_irq_restore(flags);
/* /*