openkylin
/
linux
mirror of https://gitee.com/openkylin/linux.git
9
0
Fork 0
Code Issues Projects Releases Wiki Activity

ARM: shmobile: r8a7791 dtsi: Change to using clock-indices 

With the addition of clock-indices in commit 8e33f91a0b ("clk:
shmobile: clk-mstp: change to using clock-indices"), we can change the
DTSes to use the generic property instead of the deprecated
vendor-specific property.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
[geert: Extracted r8a7791-specific part, rebased, reworded]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Ben Dooks 2014-11-10 19:49:38 +01:00 committed by Simon Horman
parent b54010af0f
commit cb0bf85123
1 changed files with 12 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
arch/arm/boot/dts/r8a7791.dtsi
View File

@ -1062,7 +1062,7 @@ mstp0_clks: mstp0_clks@e6150130 {
reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
clocks = <&mp_clk>; clocks = <&mp_clk>;
#clock-cells = <1>; #clock-cells = <1>;
renesas,clock-indices = <R8A7791_CLK_MSIOF0>; clock-indices = <R8A7791_CLK_MSIOF0>;
clock-output-names = "msiof0"; clock-output-names = "msiof0";
}; };
mstp1_clks: mstp1_clks@e6150134 { mstp1_clks: mstp1_clks@e6150134 {
@ -1073,7 +1073,7 @@ mstp1_clks: mstp1_clks@e6150134 {
<&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>,
<&zs_clk>; <&zs_clk>;
#clock-cells = <1>; #clock-cells = <1>;
renesas,clock-indices = < clock-indices = <
R8A7791_CLK_VCP0 R8A7791_CLK_VPC0 R8A7791_CLK_JPU R8A7791_CLK_VCP0 R8A7791_CLK_VPC0 R8A7791_CLK_JPU
R8A7791_CLK_SSP1 R8A7791_CLK_TMU1 R8A7791_CLK_3DG R8A7791_CLK_SSP1 R8A7791_CLK_TMU1 R8A7791_CLK_3DG
R8A7791_CLK_2DDMAC R8A7791_CLK_FDP1_1 R8A7791_CLK_FDP1_0 R8A7791_CLK_2DDMAC R8A7791_CLK_FDP1_1 R8A7791_CLK_FDP1_0
@ -1093,7 +1093,7 @@ mstp2_clks: mstp2_clks@e6150138 {
<&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
<&zs_clk>, <&zs_clk>; <&zs_clk>, <&zs_clk>;
#clock-cells = <1>; #clock-cells = <1>;
renesas,clock-indices = < clock-indices = <
R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0 R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0
R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1 R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
@ -1111,7 +1111,7 @@ mstp3_clks: mstp3_clks@e615013c {
<&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>, <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
<&hp_clk>, <&hp_clk>; <&hp_clk>, <&hp_clk>;
#clock-cells = <1>; #clock-cells = <1>;
renesas,clock-indices = < clock-indices = <
R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0 R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0
R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1 R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1
R8A7791_CLK_SSUSB R8A7791_CLK_CMT1 R8A7791_CLK_SSUSB R8A7791_CLK_CMT1
@ -1127,8 +1127,10 @@ mstp5_clks: mstp5_clks@e6150144 {
reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>, <&p_clk>; clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>, <&p_clk>;
#clock-cells = <1>; #clock-cells = <1>;
renesas,clock-indices = <R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1 clock-indices = <
R8A7791_CLK_THERMAL R8A7791_CLK_PWM>; R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1
R8A7791_CLK_THERMAL R8A7791_CLK_PWM
>;
clock-output-names = "audmac0", "audmac1", "thermal", "pwm"; clock-output-names = "audmac0", "audmac1", "thermal", "pwm";
}; };
mstp7_clks: mstp7_clks@e615014c { mstp7_clks: mstp7_clks@e615014c {
@ -1138,7 +1140,7 @@ mstp7_clks: mstp7_clks@e615014c {
<&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
<&zx_clk>, <&zx_clk>, <&zx_clk>; <&zx_clk>, <&zx_clk>, <&zx_clk>;
#clock-cells = <1>; #clock-cells = <1>;
renesas,clock-indices = < clock-indices = <
R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5 R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0 R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0
R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1 R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1
@ -1155,7 +1157,7 @@ mstp8_clks: mstp8_clks@e6150990 {
clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, <&zs_clk>, clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, <&zs_clk>,
<&zs_clk>; <&zs_clk>;
#clock-cells = <1>; #clock-cells = <1>;
renesas,clock-indices = < clock-indices = <
R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0 R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0
R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0 R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0
>; >;
@ -1171,7 +1173,7 @@ mstp9_clks: mstp9_clks@e6150994 {
<&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>, <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
<&hp_clk>, <&hp_clk>; <&hp_clk>, <&hp_clk>;
#clock-cells = <1>; #clock-cells = <1>;
renesas,clock-indices = < clock-indices = <
R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4 R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4
R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0 R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0
R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5 R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5
@ -1221,7 +1223,7 @@ mstp11_clks: mstp11_clks@e615099c {
reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>; clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
#clock-cells = <1>; #clock-cells = <1>;
renesas,clock-indices = < clock-indices = <
R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5 R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5
>; >;
clock-output-names = "scifa3", "scifa4", "scifa5"; clock-output-names = "scifa3", "scifa4", "scifa5";