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drm/nouveau/tmr: cosmetic changes 

This is purely preparation for upcoming commits, there should be no
code changes here.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2015-08-20 14:54:07 +10:00
parent da06b46b72
commit cb8bb9cedb
13 changed files with 119 additions and 120 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/gpu/drm/nouveau/dispnv04/dac.c
View File

@ -66,7 +66,7 @@ int nv04_dac_output_offset(struct drm_encoder *encoder)
static int sample_load_twice(struct drm_device *dev, bool sense[2])
{
struct nvif_device *device = &nouveau_drm(dev)->device;
struct nvkm_timer *ptimer = nvxx_timer(device);
struct nvkm_timer *tmr = nvxx_timer(device);
int i;
for (i = 0; i < 2; i++) {
@ -80,15 +80,15 @@ static int sample_load_twice(struct drm_device *dev, bool sense[2])
* use a 10ms timeout (guards against crtc being inactive, in
* which case blank state would never change)
*/
if (!nvkm_timer_wait_eq(ptimer, 10000000,
if (!nvkm_timer_wait_eq(tmr, 10000000,
NV_PRMCIO_INP0__COLOR,
0x00000001, 0x00000000))
return -EBUSY;
if (!nvkm_timer_wait_eq(ptimer, 10000000,
if (!nvkm_timer_wait_eq(tmr, 10000000,
NV_PRMCIO_INP0__COLOR,
0x00000001, 0x00000001))
return -EBUSY;
if (!nvkm_timer_wait_eq(ptimer, 10000000,
if (!nvkm_timer_wait_eq(tmr, 10000000,
NV_PRMCIO_INP0__COLOR,
0x00000001, 0x00000000))
return -EBUSY;

6
drivers/gpu/drm/nouveau/dispnv04/hw.c
View File

@ -661,7 +661,7 @@ nv_load_state_ext(struct drm_device *dev, int head,
{
struct nouveau_drm *drm = nouveau_drm(dev);
struct nvif_device *device = &drm->device;
struct nvkm_timer *ptimer = nvxx_timer(device);
struct nvkm_timer *tmr = nvxx_timer(device);
struct nv04_crtc_reg *regp = &state->crtc_reg[head];
uint32_t reg900;
int i;
@ -741,8 +741,8 @@ nv_load_state_ext(struct drm_device *dev, int head,
if (drm->device.info.family < NV_DEVICE_INFO_V0_KELVIN) {
/* Not waiting for vertical retrace before modifying
CRE_53/CRE_54 causes lockups. */
nvkm_timer_wait_eq(ptimer, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x8);
nvkm_timer_wait_eq(ptimer, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x0);
nvkm_timer_wait_eq(tmr, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x8);
nvkm_timer_wait_eq(tmr, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x0);
}
wr_cio_state(dev, head, regp, NV_CIO_CRE_42);

8
drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h
View File

@ -31,7 +31,7 @@ void nvkm_timer_alarm_cancel(void *, struct nvkm_alarm *);
nvkm_timer_wait_cb((o), NV_WAIT_DEFAULT, (c), (d))
struct nvkm_timer {
struct nvkm_subdev base;
struct nvkm_subdev subdev;
u64 (*read)(struct nvkm_timer *);
void (*alarm)(struct nvkm_timer *, u64 time, struct nvkm_alarm *);
void (*alarm_cancel)(struct nvkm_timer *, struct nvkm_alarm *);
@ -47,11 +47,11 @@ nvkm_timer(void *obj)
nvkm_subdev_create_((p), (e), (o), 0, "PTIMER", "timer", \
sizeof(**d), (void **)d)
#define nvkm_timer_destroy(p) \
nvkm_subdev_destroy(&(p)->base)
nvkm_subdev_destroy(&(p)->subdev)
#define nvkm_timer_init(p) \
nvkm_subdev_init(&(p)->base)
nvkm_subdev_init(&(p)->subdev)
#define nvkm_timer_fini(p,s) \
nvkm_subdev_fini(&(p)->base, (s))
nvkm_subdev_fini(&(p)->subdev, (s))
int nvkm_timer_create_(struct nvkm_object *, struct nvkm_engine *,
struct nvkm_oclass *, int size, void **);

4
drivers/gpu/drm/nouveau/nouveau_abi16.c
View File

@ -164,7 +164,7 @@ nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS)
struct nouveau_cli *cli = nouveau_cli(file_priv);
struct nouveau_drm *drm = nouveau_drm(dev);
struct nvif_device *device = &drm->device;
struct nvkm_timer *ptimer = nvxx_timer(device);
struct nvkm_timer *tmr = nvxx_timer(device);
struct nvkm_gr *gr = nvxx_gr(device);
struct drm_nouveau_getparam *getparam = data;
@ -206,7 +206,7 @@ nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS)
getparam->value = 0; /* deprecated */
break;
case NOUVEAU_GETPARAM_PTIMER_TIME:
getparam->value = ptimer->read(ptimer);
getparam->value = tmr->read(tmr);
break;
case NOUVEAU_GETPARAM_HAS_BO_USAGE:
getparam->value = 1;

6
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
View File

@ -237,7 +237,7 @@ nvkm_pgr_vstatus_print(struct nv50_gr_priv *priv, int r,
static int
g84_gr_tlb_flush(struct nvkm_engine *engine)
{
struct nvkm_timer *ptimer = nvkm_timer(engine);
struct nvkm_timer *tmr = nvkm_timer(engine);
struct nv50_gr_priv *priv = (void *)engine;
bool idle, timeout = false;
unsigned long flags;
@ -247,7 +247,7 @@ g84_gr_tlb_flush(struct nvkm_engine *engine)
spin_lock_irqsave(&priv->lock, flags);
nv_mask(priv, 0x400500, 0x00000001, 0x00000000);
start = ptimer->read(ptimer);
start = tmr->read(tmr);
do {
idle = true;
@ -266,7 +266,7 @@ g84_gr_tlb_flush(struct nvkm_engine *engine)
idle = false;
}
} while (!idle &&
!(timeout = ptimer->read(ptimer) - start > 2000000000));
!(timeout = tmr->read(tmr) - start > 2000000000));
if (timeout) {
nv_error(priv, "PGRAPH TLB flush idle timeout fail\n");

8
drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c
View File

@ -83,7 +83,7 @@ static void
nvkm_therm_update(struct nvkm_therm *obj, int mode)
{
struct nvkm_therm_priv *therm = container_of(obj, typeof(*therm), base);
struct nvkm_timer *ptimer = nvkm_timer(therm);
struct nvkm_timer *tmr = nvkm_timer(therm);
unsigned long flags;
bool immd = true;
bool poll = true;
@ -96,7 +96,7 @@ nvkm_therm_update(struct nvkm_therm *obj, int mode)
switch (mode) {
case NVKM_THERM_CTRL_MANUAL:
ptimer->alarm_cancel(ptimer, &therm->alarm);
tmr->alarm_cancel(tmr, &therm->alarm);
duty = nvkm_therm_fan_get(&therm->base);
if (duty < 0)
duty = 100;
@ -120,12 +120,12 @@ nvkm_therm_update(struct nvkm_therm *obj, int mode)
break;
case NVKM_THERM_CTRL_NONE:
default:
ptimer->alarm_cancel(ptimer, &therm->alarm);
tmr->alarm_cancel(tmr, &therm->alarm);
poll = false;
}
if (list_empty(&therm->alarm.head) && poll)
ptimer->alarm(ptimer, 1000000000ULL, &therm->alarm);
tmr->alarm(tmr, 1000000000ULL, &therm->alarm);
spin_unlock_irqrestore(&therm->lock, flags);
if (duty >= 0) {

18
drivers/gpu/drm/nouveau/nvkm/subdev/therm/fan.c
View File

@ -32,7 +32,7 @@ static int
nvkm_fan_update(struct nvkm_fan *fan, bool immediate, int target)
{
struct nvkm_therm_priv *therm = (void *)fan->parent;
struct nvkm_timer *ptimer = nvkm_timer(therm);
struct nvkm_timer *tmr = nvkm_timer(therm);
unsigned long flags;
int ret = 0;
int duty;
@ -94,7 +94,7 @@ nvkm_fan_update(struct nvkm_fan *fan, bool immediate, int target)
else
delay = bump_period;
ptimer->alarm(ptimer, delay * 1000 * 1000, &fan->alarm);
tmr->alarm(tmr, delay * 1000 * 1000, &fan->alarm);
}
return ret;
@ -125,7 +125,7 @@ int
nvkm_therm_fan_sense(struct nvkm_therm *obj)
{
struct nvkm_therm_priv *therm = container_of(obj, typeof(*therm), base);
struct nvkm_timer *ptimer = nvkm_timer(therm);
struct nvkm_timer *tmr = nvkm_timer(therm);
struct nvkm_gpio *gpio = nvkm_gpio(therm);
u32 cycles, cur, prev;
u64 start, end, tach;
@ -137,7 +137,7 @@ nvkm_therm_fan_sense(struct nvkm_therm *obj)
* When the fan spins, it changes the value of GPIO FAN_SENSE.
* We get 4 changes (0 -> 1 -> 0 -> 1) per complete rotation.
*/
start = ptimer->read(ptimer);
start = tmr->read(tmr);
prev = gpio->get(gpio, 0, therm->fan->tach.func, therm->fan->tach.line);
cycles = 0;
do {
@ -146,12 +146,12 @@ nvkm_therm_fan_sense(struct nvkm_therm *obj)
cur = gpio->get(gpio, 0, therm->fan->tach.func, therm->fan->tach.line);
if (prev != cur) {
if (!start)
start = ptimer->read(ptimer);
start = tmr->read(tmr);
cycles++;
prev = cur;
}
} while (cycles < 5 && ptimer->read(ptimer) - start < 250000000);
end = ptimer->read(ptimer);
} while (cycles < 5 && tmr->read(tmr) - start < 250000000);
end = tmr->read(tmr);
if (cycles == 5) {
tach = (u64)60000000000ULL;
@ -217,10 +217,10 @@ int
nvkm_therm_fan_fini(struct nvkm_therm *obj, bool suspend)
{
struct nvkm_therm_priv *therm = container_of(obj, typeof(*therm), base);
struct nvkm_timer *ptimer = nvkm_timer(therm);
struct nvkm_timer *tmr = nvkm_timer(therm);
if (suspend)
ptimer->alarm_cancel(ptimer, &therm->fan->alarm);
tmr->alarm_cancel(tmr, &therm->fan->alarm);
return 0;
}

4
drivers/gpu/drm/nouveau/nvkm/subdev/therm/fantog.c
View File

@ -39,7 +39,7 @@ static void
nvkm_fantog_update(struct nvkm_fantog *fan, int percent)
{
struct nvkm_therm_priv *therm = (void *)fan->base.parent;
struct nvkm_timer *ptimer = nvkm_timer(therm);
struct nvkm_timer *tmr = nvkm_timer(therm);
struct nvkm_gpio *gpio = nvkm_gpio(therm);
unsigned long flags;
int duty;
@ -56,7 +56,7 @@ nvkm_fantog_update(struct nvkm_fantog *fan, int percent)
u64 next_change = (percent * fan->period_us) / 100;
if (!duty)
next_change = fan->period_us - next_change;
ptimer->alarm(ptimer, next_change * 1000, &fan->alarm);
tmr->alarm(tmr, next_change * 1000, &fan->alarm);
}
spin_unlock_irqrestore(&fan->lock, flags);
}

8
drivers/gpu/drm/nouveau/nvkm/subdev/therm/temp.c
View File

@ -169,7 +169,7 @@ alarm_timer_callback(struct nvkm_alarm *alarm)
struct nvkm_therm_priv *therm =
container_of(alarm, struct nvkm_therm_priv, sensor.therm_poll_alarm);
struct nvbios_therm_sensor *sensor = &therm->bios_sensor;
struct nvkm_timer *ptimer = nvkm_timer(therm);
struct nvkm_timer *tmr = nvkm_timer(therm);
unsigned long flags;
spin_lock_irqsave(&therm->sensor.alarm_program_lock, flags);
@ -191,7 +191,7 @@ alarm_timer_callback(struct nvkm_alarm *alarm)
/* schedule the next poll in one second */
if (therm->base.temp_get(&therm->base) >= 0 && list_empty(&alarm->head))
ptimer->alarm(ptimer, 1000000000ULL, alarm);
tmr->alarm(tmr, 1000000000ULL, alarm);
}
void
@ -223,10 +223,10 @@ int
nvkm_therm_sensor_fini(struct nvkm_therm *obj, bool suspend)
{
struct nvkm_therm_priv *therm = container_of(obj, typeof(*therm), base);
struct nvkm_timer *ptimer = nvkm_timer(therm);
struct nvkm_timer *tmr = nvkm_timer(therm);
if (suspend)
ptimer->alarm_cancel(ptimer, &therm->sensor.therm_poll_alarm);
tmr->alarm_cancel(tmr, &therm->sensor.therm_poll_alarm);
return 0;
}

8
drivers/gpu/drm/nouveau/nvkm/subdev/timer/base.c
View File

@ -81,13 +81,13 @@ nvkm_timer_wait_cb(void *obj, u64 nsec, bool (*func)(void *), void *data)
void
nvkm_timer_alarm(void *obj, u32 nsec, struct nvkm_alarm *alarm)
{
struct nvkm_timer *ptimer = nvkm_timer(obj);
ptimer->alarm(ptimer, nsec, alarm);
struct nvkm_timer *tmr = nvkm_timer(obj);
tmr->alarm(tmr, nsec, alarm);
}
void
nvkm_timer_alarm_cancel(void *obj, struct nvkm_alarm *alarm)
{
struct nvkm_timer *ptimer = nvkm_timer(obj);
ptimer->alarm_cancel(ptimer, alarm);
struct nvkm_timer *tmr = nvkm_timer(obj);
tmr->alarm_cancel(tmr, alarm);
}

16
drivers/gpu/drm/nouveau/nvkm/subdev/timer/gk20a.c
View File

@ -26,21 +26,21 @@
static int
gk20a_timer_init(struct nvkm_object *object)
{
struct nv04_timer_priv *priv = (void *)object;
u32 hi = upper_32_bits(priv->suspend_time);
u32 lo = lower_32_bits(priv->suspend_time);
struct nv04_timer *tmr = (void *)object;
u32 hi = upper_32_bits(tmr->suspend_time);
u32 lo = lower_32_bits(tmr->suspend_time);
int ret;
ret = nvkm_timer_init(&priv->base);
ret = nvkm_timer_init(&tmr->base);
if (ret)
return ret;
nv_debug(priv, "time low : 0x%08x\n", lo);
nv_debug(priv, "time high : 0x%08x\n", hi);
nv_debug(tmr, "time low : 0x%08x\n", lo);
nv_debug(tmr, "time high : 0x%08x\n", hi);
/* restore the time before suspend */
nv_wr32(priv, NV04_PTIMER_TIME_1, hi);
nv_wr32(priv, NV04_PTIMER_TIME_0, lo);
nv_wr32(tmr, NV04_PTIMER_TIME_1, hi);
nv_wr32(tmr, NV04_PTIMER_TIME_0, lo);
return 0;
}

143
drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c
View File

@ -24,43 +24,42 @@
#include "nv04.h"
static u64
nv04_timer_read(struct nvkm_timer *ptimer)
nv04_timer_read(struct nvkm_timer *tmr)
{
struct nv04_timer_priv *priv = (void *)ptimer;
u32 hi, lo;
do {
hi = nv_rd32(priv, NV04_PTIMER_TIME_1);
lo = nv_rd32(priv, NV04_PTIMER_TIME_0);
} while (hi != nv_rd32(priv, NV04_PTIMER_TIME_1));
hi = nv_rd32(tmr, NV04_PTIMER_TIME_1);
lo = nv_rd32(tmr, NV04_PTIMER_TIME_0);
} while (hi != nv_rd32(tmr, NV04_PTIMER_TIME_1));
return ((u64)hi << 32 | lo);
}
static void
nv04_timer_alarm_trigger(struct nvkm_timer *ptimer)
nv04_timer_alarm_trigger(struct nvkm_timer *obj)
{
struct nv04_timer_priv *priv = (void *)ptimer;
struct nv04_timer *tmr = container_of(obj, typeof(*tmr), base);
struct nvkm_alarm *alarm, *atemp;
unsigned long flags;
LIST_HEAD(exec);
/* move any due alarms off the pending list */
spin_lock_irqsave(&priv->lock, flags);
list_for_each_entry_safe(alarm, atemp, &priv->alarms, head) {
if (alarm->timestamp <= ptimer->read(ptimer))
spin_lock_irqsave(&tmr->lock, flags);
list_for_each_entry_safe(alarm, atemp, &tmr->alarms, head) {
if (alarm->timestamp <= tmr->base.read(&tmr->base))
list_move_tail(&alarm->head, &exec);
}
/* reschedule interrupt for next alarm time */
if (!list_empty(&priv->alarms)) {
alarm = list_first_entry(&priv->alarms, typeof(*alarm), head);
nv_wr32(priv, NV04_PTIMER_ALARM_0, alarm->timestamp);
nv_wr32(priv, NV04_PTIMER_INTR_EN_0, 0x00000001);
if (!list_empty(&tmr->alarms)) {
alarm = list_first_entry(&tmr->alarms, typeof(*alarm), head);
nv_wr32(tmr, NV04_PTIMER_ALARM_0, alarm->timestamp);
nv_wr32(tmr, NV04_PTIMER_INTR_EN_0, 0x00000001);
} else {
nv_wr32(priv, NV04_PTIMER_INTR_EN_0, 0x00000000);
nv_wr32(tmr, NV04_PTIMER_INTR_EN_0, 0x00000000);
}
spin_unlock_irqrestore(&priv->lock, flags);
spin_unlock_irqrestore(&tmr->lock, flags);
/* execute any pending alarm handlers */
list_for_each_entry_safe(alarm, atemp, &exec, head) {
@ -70,79 +69,79 @@ nv04_timer_alarm_trigger(struct nvkm_timer *ptimer)
}
static void
nv04_timer_alarm(struct nvkm_timer *ptimer, u64 time, struct nvkm_alarm *alarm)
nv04_timer_alarm(struct nvkm_timer *obj, u64 time, struct nvkm_alarm *alarm)
{
struct nv04_timer_priv *priv = (void *)ptimer;
struct nv04_timer *tmr = container_of(obj, typeof(*tmr), base);
struct nvkm_alarm *list;
unsigned long flags;
alarm->timestamp = ptimer->read(ptimer) + time;
alarm->timestamp = tmr->base.read(&tmr->base) + time;
/* append new alarm to list, in soonest-alarm-first order */
spin_lock_irqsave(&priv->lock, flags);
spin_lock_irqsave(&tmr->lock, flags);
if (!time) {
if (!list_empty(&alarm->head))
list_del(&alarm->head);
} else {
list_for_each_entry(list, &priv->alarms, head) {
list_for_each_entry(list, &tmr->alarms, head) {
if (list->timestamp > alarm->timestamp)
break;
}
list_add_tail(&alarm->head, &list->head);
}
spin_unlock_irqrestore(&priv->lock, flags);
spin_unlock_irqrestore(&tmr->lock, flags);
/* process pending alarms */
nv04_timer_alarm_trigger(ptimer);
nv04_timer_alarm_trigger(&tmr->base);
}
static void
nv04_timer_alarm_cancel(struct nvkm_timer *ptimer, struct nvkm_alarm *alarm)
nv04_timer_alarm_cancel(struct nvkm_timer *obj, struct nvkm_alarm *alarm)
{
struct nv04_timer_priv *priv = (void *)ptimer;
struct nv04_timer *tmr = container_of(obj, typeof(*tmr), base);
unsigned long flags;
spin_lock_irqsave(&priv->lock, flags);
spin_lock_irqsave(&tmr->lock, flags);
list_del_init(&alarm->head);
spin_unlock_irqrestore(&priv->lock, flags);
spin_unlock_irqrestore(&tmr->lock, flags);
}
static void
nv04_timer_intr(struct nvkm_subdev *subdev)
{
struct nv04_timer_priv *priv = (void *)subdev;
u32 stat = nv_rd32(priv, NV04_PTIMER_INTR_0);
struct nv04_timer *tmr = (void *)subdev;
u32 stat = nv_rd32(tmr, NV04_PTIMER_INTR_0);
if (stat & 0x00000001) {
nv04_timer_alarm_trigger(&priv->base);
nv_wr32(priv, NV04_PTIMER_INTR_0, 0x00000001);
nv04_timer_alarm_trigger(&tmr->base);
nv_wr32(tmr, NV04_PTIMER_INTR_0, 0x00000001);
stat &= ~0x00000001;
}
if (stat) {
nv_error(priv, "unknown stat 0x%08x\n", stat);
nv_wr32(priv, NV04_PTIMER_INTR_0, stat);
nv_error(tmr, "unknown stat 0x%08x\n", stat);
nv_wr32(tmr, NV04_PTIMER_INTR_0, stat);
}
}
int
nv04_timer_fini(struct nvkm_object *object, bool suspend)
{
struct nv04_timer_priv *priv = (void *)object;
struct nv04_timer *tmr = (void *)object;
if (suspend)
priv->suspend_time = nv04_timer_read(&priv->base);
nv_wr32(priv, NV04_PTIMER_INTR_EN_0, 0x00000000);
return nvkm_timer_fini(&priv->base, suspend);
tmr->suspend_time = nv04_timer_read(&tmr->base);
nv_wr32(tmr, NV04_PTIMER_INTR_EN_0, 0x00000000);
return nvkm_timer_fini(&tmr->base, suspend);
}
static int
nv04_timer_init(struct nvkm_object *object)
{
struct nvkm_device *device = nv_device(object);
struct nv04_timer_priv *priv = (void *)object;
struct nv04_timer *tmr = (void *)object;
u32 m = 1, f, n, d, lo, hi;
int ret;
ret = nvkm_timer_init(&priv->base);
ret = nvkm_timer_init(&tmr->base);
if (ret)
return ret;
@ -167,15 +166,15 @@ nv04_timer_init(struct nvkm_object *object)
m++;
}
nv_wr32(priv, 0x009220, m - 1);
nv_wr32(tmr, 0x009220, m - 1);
}
if (!n) {
nv_warn(priv, "unknown input clock freq\n");
if (!nv_rd32(priv, NV04_PTIMER_NUMERATOR) ||
!nv_rd32(priv, NV04_PTIMER_DENOMINATOR)) {
nv_wr32(priv, NV04_PTIMER_NUMERATOR, 1);
nv_wr32(priv, NV04_PTIMER_DENOMINATOR, 1);
nv_warn(tmr, "unknown input clock freq\n");
if (!nv_rd32(tmr, NV04_PTIMER_NUMERATOR) ||
!nv_rd32(tmr, NV04_PTIMER_DENOMINATOR)) {
nv_wr32(tmr, NV04_PTIMER_NUMERATOR, 1);
nv_wr32(tmr, NV04_PTIMER_DENOMINATOR, 1);
}
return 0;
}
@ -197,31 +196,31 @@ nv04_timer_init(struct nvkm_object *object)
}
/* restore the time before suspend */
lo = priv->suspend_time;
hi = (priv->suspend_time >> 32);
lo = tmr->suspend_time;
hi = (tmr->suspend_time >> 32);
nv_debug(priv, "input frequency : %dHz\n", f);
nv_debug(priv, "input multiplier: %d\n", m);
nv_debug(priv, "numerator : 0x%08x\n", n);
nv_debug(priv, "denominator : 0x%08x\n", d);
nv_debug(priv, "timer frequency : %dHz\n", (f * m) * d / n);
nv_debug(priv, "time low : 0x%08x\n", lo);
nv_debug(priv, "time high : 0x%08x\n", hi);
nv_debug(tmr, "input frequency : %dHz\n", f);
nv_debug(tmr, "input multiplier: %d\n", m);
nv_debug(tmr, "numerator : 0x%08x\n", n);
nv_debug(tmr, "denominator : 0x%08x\n", d);
nv_debug(tmr, "timer frequency : %dHz\n", (f * m) * d / n);
nv_debug(tmr, "time low : 0x%08x\n", lo);
nv_debug(tmr, "time high : 0x%08x\n", hi);
nv_wr32(priv, NV04_PTIMER_NUMERATOR, n);
nv_wr32(priv, NV04_PTIMER_DENOMINATOR, d);
nv_wr32(priv, NV04_PTIMER_INTR_0, 0xffffffff);
nv_wr32(priv, NV04_PTIMER_INTR_EN_0, 0x00000000);
nv_wr32(priv, NV04_PTIMER_TIME_1, hi);
nv_wr32(priv, NV04_PTIMER_TIME_0, lo);
nv_wr32(tmr, NV04_PTIMER_NUMERATOR, n);
nv_wr32(tmr, NV04_PTIMER_DENOMINATOR, d);
nv_wr32(tmr, NV04_PTIMER_INTR_0, 0xffffffff);
nv_wr32(tmr, NV04_PTIMER_INTR_EN_0, 0x00000000);
nv_wr32(tmr, NV04_PTIMER_TIME_1, hi);
nv_wr32(tmr, NV04_PTIMER_TIME_0, lo);
return 0;
}
void
nv04_timer_dtor(struct nvkm_object *object)
{
struct nv04_timer_priv *priv = (void *)object;
return nvkm_timer_destroy(&priv->base);
struct nv04_timer *tmr = (void *)object;
return nvkm_timer_destroy(&tmr->base);
}
int
@ -229,22 +228,22 @@ nv04_timer_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
struct nv04_timer_priv *priv;
struct nv04_timer *tmr;
int ret;
ret = nvkm_timer_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
ret = nvkm_timer_create(parent, engine, oclass, &tmr);
*pobject = nv_object(tmr);
if (ret)
return ret;
priv->base.base.intr = nv04_timer_intr;
priv->base.read = nv04_timer_read;
priv->base.alarm = nv04_timer_alarm;
priv->base.alarm_cancel = nv04_timer_alarm_cancel;
priv->suspend_time = 0;
tmr->base.subdev.intr = nv04_timer_intr;
tmr->base.read = nv04_timer_read;
tmr->base.alarm = nv04_timer_alarm;
tmr->base.alarm_cancel = nv04_timer_alarm_cancel;
tmr->suspend_time = 0;
INIT_LIST_HEAD(&priv->alarms);
spin_lock_init(&priv->lock);
INIT_LIST_HEAD(&tmr->alarms);
spin_lock_init(&tmr->lock);
return 0;
}

2
drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.h
View File

@ -10,7 +10,7 @@
#define NV04_PTIMER_TIME_1 0x009410
#define NV04_PTIMER_ALARM_0 0x009420
struct nv04_timer_priv {
struct nv04_timer {
struct nvkm_timer base;
struct list_head alarms;
spinlock_t lock;