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drm/i915: make A0 wa's applied to A1 

Since A1 chips use the same GPU as A0, they need all the
same wa's in the i915 driver. Update some conditionals
to do this.

Signed-off-by: Tim Gore <tim.gore@intel.com>
Reviewed-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1445856538-5417-1-git-send-email-tim.gore@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Tim Gore 2015-10-26 10:48:58 +00:00 committed by Jani Nikula
parent 8b10c0cf21
commit cbdc12a9fc
4 changed files with 8 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/i915/intel_guc_loader.c
View File

@ -309,7 +309,7 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
/* WaDisableMinuteIaClockGating:skl,bxt */ /* WaDisableMinuteIaClockGating:skl,bxt */
if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) || if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
IS_BXT_REVID(dev, 0, BXT_REVID_A0)) { IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) & I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) &
~GUC_ENABLE_MIA_CLOCK_GATING)); ~GUC_ENABLE_MIA_CLOCK_GATING));
} }

8
drivers/gpu/drm/i915/intel_lrc.c
View File

@ -285,7 +285,7 @@ static bool disable_lite_restore_wa(struct intel_engine_cs *ring)
struct drm_device *dev = ring->dev; struct drm_device *dev = ring->dev;
return (IS_SKL_REVID(dev, 0, SKL_REVID_B0) || return (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
IS_BXT_REVID(dev, 0, BXT_REVID_A0)) && IS_BXT_REVID(dev, 0, BXT_REVID_A1)) &&
(ring->id == VCS || ring->id == VCS2); (ring->id == VCS || ring->id == VCS2);
} }
@ -1313,7 +1313,7 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *ring,
/* WaDisableCtxRestoreArbitration:skl,bxt */ /* WaDisableCtxRestoreArbitration:skl,bxt */
if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) || if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
IS_BXT_REVID(dev, 0, BXT_REVID_A0)) IS_BXT_REVID(dev, 0, BXT_REVID_A1))
wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE); wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
/* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */ /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
@ -1339,7 +1339,7 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *ring,
/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */ /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) || if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
IS_BXT_REVID(dev, 0, BXT_REVID_A0)) { IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
wa_ctx_emit(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0); wa_ctx_emit(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
wa_ctx_emit(batch, index, wa_ctx_emit(batch, index,
@ -1349,7 +1349,7 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *ring,
/* WaDisableCtxRestoreArbitration:skl,bxt */ /* WaDisableCtxRestoreArbitration:skl,bxt */
if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) || if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
IS_BXT_REVID(dev, 0, BXT_REVID_A0)) IS_BXT_REVID(dev, 0, BXT_REVID_A1))
wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE); wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END); wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);

2
drivers/gpu/drm/i915/intel_pm.c
View File

@ -4687,7 +4687,7 @@ static void gen9_enable_rc6(struct drm_device *dev)
"on" : "off"); "on" : "off");
/* WaRsUseTimeoutMode */ /* WaRsUseTimeoutMode */
if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) || if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
IS_BXT_REVID(dev, 0, BXT_REVID_A0)) { IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */ I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
GEN7_RC_CTL_TO_MODE | GEN7_RC_CTL_TO_MODE |

4
drivers/gpu/drm/i915/intel_ringbuffer.c
View File

@ -1097,11 +1097,11 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring)
/* WaStoreMultiplePTEenable:bxt */ /* WaStoreMultiplePTEenable:bxt */
/* This is a requirement according to Hardware specification */ /* This is a requirement according to Hardware specification */
if (IS_BXT_REVID(dev, 0, BXT_REVID_A0)) if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF); I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
/* WaSetClckGatingDisableMedia:bxt */ /* WaSetClckGatingDisableMedia:bxt */
if (IS_BXT_REVID(dev, 0, BXT_REVID_A0)) { if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) & I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE)); ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
} }