mirror of https://gitee.com/openkylin/linux.git
clk: meson: axg: migrate to the new parent description method
This clock controller use the string comparison method to describe parent relation between the clocks, which is not optimized. Migrate to the new way by using .parent_hws where possible (ie. when all clocks are local to the controller) and use .parent_data otherwise. Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
This commit is contained in:
Alexandre Mergnat
Jerome Brunet
parent
0dea3f3599
commit
cc132d113d
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@ -14,7 +14,6 @@
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include "clk-input.h"
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#include "clk-regmap.h"
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#include "clk-pll.h"
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#include "clk-mpll.h"
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@ -59,7 +58,9 @@ static struct clk_regmap axg_fixed_pll_dco = {
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.hw.init = &(struct clk_init_data){
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.name = "fixed_pll_dco",
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.ops = &meson_clk_pll_ro_ops,
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.parent_names = (const char *[]){ IN_PREFIX "xtal" },
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.parent_data = &(const struct clk_parent_data) {
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.fw_name = "xtal",
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},
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.num_parents = 1,
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},
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};
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@ -74,7 +75,9 @@ static struct clk_regmap axg_fixed_pll = {
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.hw.init = &(struct clk_init_data){
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.name = "fixed_pll",
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.ops = &clk_regmap_divider_ro_ops,
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.parent_names = (const char *[]){ "fixed_pll_dco" },
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.parent_hws = (const struct clk_hw *[]) {
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&axg_fixed_pll_dco.hw
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},
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.num_parents = 1,
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/*
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* This clock won't ever change at runtime so
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@ -114,7 +117,9 @@ static struct clk_regmap axg_sys_pll_dco = {
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.hw.init = &(struct clk_init_data){
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.name = "sys_pll_dco",
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.ops = &meson_clk_pll_ro_ops,
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.parent_names = (const char *[]){ IN_PREFIX "xtal" },
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.parent_data = &(const struct clk_parent_data) {
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.fw_name = "xtal",
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},
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.num_parents = 1,
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},
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};
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@ -129,7 +134,9 @@ static struct clk_regmap axg_sys_pll = {
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.hw.init = &(struct clk_init_data){
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.name = "sys_pll",
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.ops = &clk_regmap_divider_ro_ops,
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.parent_names = (const char *[]){ "sys_pll_dco" },
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.parent_hws = (const struct clk_hw *[]) {
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&axg_sys_pll_dco.hw
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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@ -215,7 +222,9 @@ static struct clk_regmap axg_gp0_pll_dco = {
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.hw.init = &(struct clk_init_data){
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.name = "gp0_pll_dco",
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.ops = &meson_clk_pll_ops,
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.parent_names = (const char *[]){ IN_PREFIX "xtal" },
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.parent_data = &(const struct clk_parent_data) {
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.fw_name = "xtal",
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},
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.num_parents = 1,
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},
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};
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@ -230,7 +239,9 @@ static struct clk_regmap axg_gp0_pll = {
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.hw.init = &(struct clk_init_data){
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.name = "gp0_pll",
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.ops = &clk_regmap_divider_ops,
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.parent_names = (const char *[]){ "gp0_pll_dco" },
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.parent_hws = (const struct clk_hw *[]) {
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&axg_gp0_pll_dco.hw
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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@ -284,7 +295,9 @@ static struct clk_regmap axg_hifi_pll_dco = {
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.hw.init = &(struct clk_init_data){
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.name = "hifi_pll_dco",
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.ops = &meson_clk_pll_ops,
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.parent_names = (const char *[]){ IN_PREFIX "xtal" },
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.parent_data = &(const struct clk_parent_data) {
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.fw_name = "xtal",
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},
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.num_parents = 1,
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},
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};
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@ -299,7 +312,9 @@ static struct clk_regmap axg_hifi_pll = {
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.hw.init = &(struct clk_init_data){
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.name = "hifi_pll",
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.ops = &clk_regmap_divider_ops,
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.parent_names = (const char *[]){ "hifi_pll_dco" },
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.parent_hws = (const struct clk_hw *[]) {
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&axg_hifi_pll_dco.hw
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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@ -311,7 +326,7 @@ static struct clk_fixed_factor axg_fclk_div2_div = {
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.hw.init = &(struct clk_init_data){
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.name = "fclk_div2_div",
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.ops = &clk_fixed_factor_ops,
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.parent_names = (const char *[]){ "fixed_pll" },
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.parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw },
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.num_parents = 1,
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},
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};
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@ -324,7 +339,9 @@ static struct clk_regmap axg_fclk_div2 = {
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.hw.init = &(struct clk_init_data){
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.name = "fclk_div2",
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.ops = &clk_regmap_gate_ops,
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.parent_names = (const char *[]){ "fclk_div2_div" },
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.parent_hws = (const struct clk_hw *[]) {
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&axg_fclk_div2_div.hw
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},
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.num_parents = 1,
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.flags = CLK_IS_CRITICAL,
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},
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@ -336,7 +353,7 @@ static struct clk_fixed_factor axg_fclk_div3_div = {
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.hw.init = &(struct clk_init_data){
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.name = "fclk_div3_div",
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.ops = &clk_fixed_factor_ops,
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.parent_names = (const char *[]){ "fixed_pll" },
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.parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw },
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.num_parents = 1,
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},
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};
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@ -349,7 +366,9 @@ static struct clk_regmap axg_fclk_div3 = {
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.hw.init = &(struct clk_init_data){
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.name = "fclk_div3",
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.ops = &clk_regmap_gate_ops,
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.parent_names = (const char *[]){ "fclk_div3_div" },
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.parent_hws = (const struct clk_hw *[]) {
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&axg_fclk_div3_div.hw
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},
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.num_parents = 1,
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/*
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* FIXME:
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@ -372,7 +391,7 @@ static struct clk_fixed_factor axg_fclk_div4_div = {
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.hw.init = &(struct clk_init_data){
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.name = "fclk_div4_div",
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.ops = &clk_fixed_factor_ops,
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.parent_names = (const char *[]){ "fixed_pll" },
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.parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw },
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.num_parents = 1,
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},
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};
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@ -385,7 +404,9 @@ static struct clk_regmap axg_fclk_div4 = {
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.hw.init = &(struct clk_init_data){
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.name = "fclk_div4",
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.ops = &clk_regmap_gate_ops,
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.parent_names = (const char *[]){ "fclk_div4_div" },
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.parent_hws = (const struct clk_hw *[]) {
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&axg_fclk_div4_div.hw
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},
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.num_parents = 1,
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},
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};
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@ -396,7 +417,7 @@ static struct clk_fixed_factor axg_fclk_div5_div = {
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.hw.init = &(struct clk_init_data){
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.name = "fclk_div5_div",
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.ops = &clk_fixed_factor_ops,
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.parent_names = (const char *[]){ "fixed_pll" },
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.parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw },
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.num_parents = 1,
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},
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};
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@ -409,7 +430,9 @@ static struct clk_regmap axg_fclk_div5 = {
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.hw.init = &(struct clk_init_data){
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.name = "fclk_div5",
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.ops = &clk_regmap_gate_ops,
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.parent_names = (const char *[]){ "fclk_div5_div" },
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.parent_hws = (const struct clk_hw *[]) {
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&axg_fclk_div5_div.hw
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},
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.num_parents = 1,
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},
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};
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@ -420,7 +443,9 @@ static struct clk_fixed_factor axg_fclk_div7_div = {
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.hw.init = &(struct clk_init_data){
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.name = "fclk_div7_div",
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.ops = &clk_fixed_factor_ops,
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.parent_names = (const char *[]){ "fixed_pll" },
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.parent_hws = (const struct clk_hw *[]) {
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&axg_fixed_pll.hw
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},
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.num_parents = 1,
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},
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};
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@ -433,7 +458,9 @@ static struct clk_regmap axg_fclk_div7 = {
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.hw.init = &(struct clk_init_data){
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.name = "fclk_div7",
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.ops = &clk_regmap_gate_ops,
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.parent_names = (const char *[]){ "fclk_div7_div" },
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.parent_hws = (const struct clk_hw *[]) {
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&axg_fclk_div7_div.hw
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},
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.num_parents = 1,
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},
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};
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@ -447,7 +474,9 @@ static struct clk_regmap axg_mpll_prediv = {
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.hw.init = &(struct clk_init_data){
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.name = "mpll_prediv",
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.ops = &clk_regmap_divider_ro_ops,
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.parent_names = (const char *[]){ "fixed_pll" },
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.parent_hws = (const struct clk_hw *[]) {
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&axg_fixed_pll.hw
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},
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.num_parents = 1,
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},
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};
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@ -480,7 +509,9 @@ static struct clk_regmap axg_mpll0_div = {
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.hw.init = &(struct clk_init_data){
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.name = "mpll0_div",
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.ops = &meson_clk_mpll_ops,
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.parent_names = (const char *[]){ "mpll_prediv" },
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.parent_hws = (const struct clk_hw *[]) {
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&axg_mpll_prediv.hw
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},
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.num_parents = 1,
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},
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};
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@ -493,7 +524,9 @@ static struct clk_regmap axg_mpll0 = {
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.hw.init = &(struct clk_init_data){
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.name = "mpll0",
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.ops = &clk_regmap_gate_ops,
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.parent_names = (const char *[]){ "mpll0_div" },
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.parent_hws = (const struct clk_hw *[]) {
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&axg_mpll0_div.hw
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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@ -527,7 +560,9 @@ static struct clk_regmap axg_mpll1_div = {
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.hw.init = &(struct clk_init_data){
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.name = "mpll1_div",
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.ops = &meson_clk_mpll_ops,
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.parent_names = (const char *[]){ "mpll_prediv" },
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.parent_hws = (const struct clk_hw *[]) {
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&axg_mpll_prediv.hw
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},
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.num_parents = 1,
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},
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};
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@ -540,7 +575,9 @@ static struct clk_regmap axg_mpll1 = {
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.hw.init = &(struct clk_init_data){
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.name = "mpll1",
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.ops = &clk_regmap_gate_ops,
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.parent_names = (const char *[]){ "mpll1_div" },
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.parent_hws = (const struct clk_hw *[]) {
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&axg_mpll1_div.hw
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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@ -579,7 +616,9 @@ static struct clk_regmap axg_mpll2_div = {
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.hw.init = &(struct clk_init_data){
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.name = "mpll2_div",
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.ops = &meson_clk_mpll_ops,
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.parent_names = (const char *[]){ "mpll_prediv" },
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.parent_hws = (const struct clk_hw *[]) {
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&axg_mpll_prediv.hw
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},
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.num_parents = 1,
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},
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};
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@ -592,7 +631,9 @@ static struct clk_regmap axg_mpll2 = {
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.hw.init = &(struct clk_init_data){
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.name = "mpll2",
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.ops = &clk_regmap_gate_ops,
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.parent_names = (const char *[]){ "mpll2_div" },
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.parent_hws = (const struct clk_hw *[]) {
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&axg_mpll2_div.hw
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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@ -626,7 +667,9 @@ static struct clk_regmap axg_mpll3_div = {
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.hw.init = &(struct clk_init_data){
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.name = "mpll3_div",
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.ops = &meson_clk_mpll_ops,
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.parent_names = (const char *[]){ "mpll_prediv" },
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.parent_hws = (const struct clk_hw *[]) {
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&axg_mpll_prediv.hw
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},
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.num_parents = 1,
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},
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};
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@ -639,7 +682,9 @@ static struct clk_regmap axg_mpll3 = {
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.hw.init = &(struct clk_init_data){
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.name = "mpll3",
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.ops = &clk_regmap_gate_ops,
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.parent_names = (const char *[]){ "mpll3_div" },
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.parent_hws = (const struct clk_hw *[]) {
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&axg_mpll3_div.hw
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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@ -702,7 +747,9 @@ static struct clk_regmap axg_pcie_pll_dco = {
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.hw.init = &(struct clk_init_data){
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.name = "pcie_pll_dco",
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.ops = &meson_clk_pll_ops,
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.parent_names = (const char *[]){ IN_PREFIX "xtal" },
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.parent_data = &(const struct clk_parent_data) {
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.fw_name = "xtal",
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},
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.num_parents = 1,
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},
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};
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@ -717,7 +764,9 @@ static struct clk_regmap axg_pcie_pll_od = {
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.hw.init = &(struct clk_init_data){
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.name = "pcie_pll_od",
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.ops = &clk_regmap_divider_ops,
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.parent_names = (const char *[]){ "pcie_pll_dco" },
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.parent_hws = (const struct clk_hw *[]) {
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&axg_pcie_pll_dco.hw
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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@ -733,7 +782,9 @@ static struct clk_regmap axg_pcie_pll = {
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.hw.init = &(struct clk_init_data){
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.name = "pcie_pll",
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.ops = &clk_regmap_divider_ops,
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.parent_names = (const char *[]){ "pcie_pll_od" },
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.parent_hws = (const struct clk_hw *[]) {
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&axg_pcie_pll_od.hw
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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@ -750,7 +801,7 @@ static struct clk_regmap axg_pcie_mux = {
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.hw.init = &(struct clk_init_data){
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.name = "pcie_mux",
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.ops = &clk_regmap_mux_ops,
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.parent_names = (const char *[]){ "pcie_pll" },
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.parent_hws = (const struct clk_hw *[]) { &axg_pcie_pll.hw },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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@ -767,7 +818,7 @@ static struct clk_regmap axg_pcie_ref = {
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.hw.init = &(struct clk_init_data){
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.name = "pcie_ref",
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.ops = &clk_regmap_mux_ops,
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.parent_names = (const char *[]){ "pcie_mux" },
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.parent_hws = (const struct clk_hw *[]) { &axg_pcie_mux.hw },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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@ -781,7 +832,7 @@ static struct clk_regmap axg_pcie_cml_en0 = {
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.hw.init = &(struct clk_init_data) {
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.name = "pcie_cml_en0",
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.ops = &clk_regmap_gate_ops,
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.parent_names = (const char *[]){ "pcie_ref" },
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.parent_hws = (const struct clk_hw *[]) { &axg_pcie_ref.hw },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -796,16 +847,21 @@ static struct clk_regmap axg_pcie_cml_en1 = {
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.hw.init = &(struct clk_init_data) {
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.name = "pcie_cml_en1",
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.ops = &clk_regmap_gate_ops,
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.parent_names = (const char *[]){ "pcie_ref" },
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.parent_hws = (const struct clk_hw *[]) { &axg_pcie_ref.hw },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };
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static const char * const clk81_parent_names[] = {
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IN_PREFIX "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",
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"fclk_div3", "fclk_div5"
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static const struct clk_parent_data clk81_parent_data[] = {
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{ .fw_name = "xtal", },
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{ .hw = &axg_fclk_div7.hw },
|
||||
{ .hw = &axg_mpll1.hw },
|
||||
{ .hw = &axg_mpll2.hw },
|
||||
{ .hw = &axg_fclk_div4.hw },
|
||||
{ .hw = &axg_fclk_div3.hw },
|
||||
{ .hw = &axg_fclk_div5.hw },
|
||||
};
|
||||
|
||||
static struct clk_regmap axg_mpeg_clk_sel = {
|
||||
|
|
@ -818,8 +874,8 @@ static struct clk_regmap axg_mpeg_clk_sel = {
|
|||
.hw.init = &(struct clk_init_data){
|
||||
.name = "mpeg_clk_sel",
|
||||
.ops = &clk_regmap_mux_ro_ops,
|
||||
.parent_names = clk81_parent_names,
|
||||
.num_parents = ARRAY_SIZE(clk81_parent_names),
|
||||
.parent_data = clk81_parent_data,
|
||||
.num_parents = ARRAY_SIZE(clk81_parent_data),
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -832,7 +888,9 @@ static struct clk_regmap axg_mpeg_clk_div = {
|
|||
.hw.init = &(struct clk_init_data){
|
||||
.name = "mpeg_clk_div",
|
||||
.ops = &clk_regmap_divider_ops,
|
||||
.parent_names = (const char *[]){ "mpeg_clk_sel" },
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&axg_mpeg_clk_sel.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
|
|
@ -846,15 +904,20 @@ static struct clk_regmap axg_clk81 = {
|
|||
.hw.init = &(struct clk_init_data){
|
||||
.name = "clk81",
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_names = (const char *[]){ "mpeg_clk_div" },
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&axg_mpeg_clk_div.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
|
||||
},
|
||||
};
|
||||
|
||||
static const char * const axg_sd_emmc_clk0_parent_names[] = {
|
||||
IN_PREFIX "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7",
|
||||
|
||||
static const struct clk_parent_data axg_sd_emmc_clk0_parent_data[] = {
|
||||
{ .fw_name = "xtal", },
|
||||
{ .hw = &axg_fclk_div2.hw },
|
||||
{ .hw = &axg_fclk_div3.hw },
|
||||
{ .hw = &axg_fclk_div5.hw },
|
||||
{ .hw = &axg_fclk_div7.hw },
|
||||
/*
|
||||
* Following these parent clocks, we should also have had mpll2, mpll3
|
||||
* and gp0_pll but these clocks are too precious to be used here. All
|
||||
|
|
@ -873,8 +936,8 @@ static struct clk_regmap axg_sd_emmc_b_clk0_sel = {
|
|||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "sd_emmc_b_clk0_sel",
|
||||
.ops = &clk_regmap_mux_ops,
|
||||
.parent_names = axg_sd_emmc_clk0_parent_names,
|
||||
.num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_names),
|
||||
.parent_data = axg_sd_emmc_clk0_parent_data,
|
||||
.num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_data),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
|
@ -889,7 +952,9 @@ static struct clk_regmap axg_sd_emmc_b_clk0_div = {
|
|||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "sd_emmc_b_clk0_div",
|
||||
.ops = &clk_regmap_divider_ops,
|
||||
.parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" },
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&axg_sd_emmc_b_clk0_sel.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
|
|
@ -903,7 +968,9 @@ static struct clk_regmap axg_sd_emmc_b_clk0 = {
|
|||
.hw.init = &(struct clk_init_data){
|
||||
.name = "sd_emmc_b_clk0",
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_names = (const char *[]){ "sd_emmc_b_clk0_div" },
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&axg_sd_emmc_b_clk0_div.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
|
|
@ -919,8 +986,8 @@ static struct clk_regmap axg_sd_emmc_c_clk0_sel = {
|
|||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "sd_emmc_c_clk0_sel",
|
||||
.ops = &clk_regmap_mux_ops,
|
||||
.parent_names = axg_sd_emmc_clk0_parent_names,
|
||||
.num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_names),
|
||||
.parent_data = axg_sd_emmc_clk0_parent_data,
|
||||
.num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_data),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
|
@ -935,7 +1002,9 @@ static struct clk_regmap axg_sd_emmc_c_clk0_div = {
|
|||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "sd_emmc_c_clk0_div",
|
||||
.ops = &clk_regmap_divider_ops,
|
||||
.parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" },
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&axg_sd_emmc_c_clk0_sel.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
|
|
@ -949,7 +1018,9 @@ static struct clk_regmap axg_sd_emmc_c_clk0 = {
|
|||
.hw.init = &(struct clk_init_data){
|
||||
.name = "sd_emmc_c_clk0",
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_names = (const char *[]){ "sd_emmc_c_clk0_div" },
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&axg_sd_emmc_c_clk0_div.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
|
|
@ -957,9 +1028,18 @@ static struct clk_regmap axg_sd_emmc_c_clk0 = {
|
|||
|
||||
static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8,
|
||||
9, 10, 11, 13, 14, };
|
||||
static const char * const gen_clk_parent_names[] = {
|
||||
IN_PREFIX "xtal", "hifi_pll", "mpll0", "mpll1", "mpll2", "mpll3",
|
||||
"fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7", "gp0_pll",
|
||||
static const struct clk_parent_data gen_clk_parent_data[] = {
|
||||
{ .fw_name = "xtal", },
|
||||
{ .hw = &axg_hifi_pll.hw },
|
||||
{ .hw = &axg_mpll0.hw },
|
||||
{ .hw = &axg_mpll1.hw },
|
||||
{ .hw = &axg_mpll2.hw },
|
||||
{ .hw = &axg_mpll3.hw },
|
||||
{ .hw = &axg_fclk_div4.hw },
|
||||
{ .hw = &axg_fclk_div3.hw },
|
||||
{ .hw = &axg_fclk_div5.hw },
|
||||
{ .hw = &axg_fclk_div7.hw },
|
||||
{ .hw = &axg_gp0_pll.hw },
|
||||
};
|
||||
|
||||
static struct clk_regmap axg_gen_clk_sel = {
|
||||
|
|
@ -978,8 +1058,8 @@ static struct clk_regmap axg_gen_clk_sel = {
|
|||
* hifi_pll, mpll0, mpll1, mpll2, mpll3, fdiv4,
|
||||
* fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll
|
||||
*/
|
||||
.parent_names = gen_clk_parent_names,
|
||||
.num_parents = ARRAY_SIZE(gen_clk_parent_names),
|
||||
.parent_data = gen_clk_parent_data,
|
||||
.num_parents = ARRAY_SIZE(gen_clk_parent_data),
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -992,7 +1072,9 @@ static struct clk_regmap axg_gen_clk_div = {
|
|||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gen_clk_div",
|
||||
.ops = &clk_regmap_divider_ops,
|
||||
.parent_names = (const char *[]){ "gen_clk_sel" },
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&axg_gen_clk_sel.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
|
|
@ -1006,7 +1088,9 @@ static struct clk_regmap axg_gen_clk = {
|
|||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gen_clk",
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_names = (const char *[]){ "gen_clk_div" },
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&axg_gen_clk_div.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
|
|
|
|||
Loading…
Reference in New Issue