mirror of https://gitee.com/openkylin/linux.git
phy: Add QMP phy based UFS phy support for sdm845
Add UFS PHY support to make SDM845 UFS work with common PHY framework. Signed-off-by: Can Guo <cang@codeaurora.org> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
This commit is contained in:
Can Guo
Kishon Vijay Abraham I
parent
6b04526812
commit
cc31cdbef9
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@ -156,6 +156,11 @@ static const unsigned int qmp_v3_usb3phy_regs_layout[] = {
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[QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
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};
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static const unsigned int sdm845_ufsphy_regs_layout[] = {
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[QPHY_START_CTRL] = 0x00,
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[QPHY_PCS_READY_STATUS] = 0x160,
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};
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static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
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QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
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@ -601,6 +606,83 @@ static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
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};
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static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
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/* Rate B */
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
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};
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static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
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QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
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QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
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};
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static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
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QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
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QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
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QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
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QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
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QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
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QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
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QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
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QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
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QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
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QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
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QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
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QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
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QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
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QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
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QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
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};
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static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
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};
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/* struct qmp_phy_cfg - per-PHY initialization config */
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struct qmp_phy_cfg {
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@ -654,6 +736,9 @@ struct qmp_phy_cfg {
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/* Register offset of secondary tx/rx lanes for USB DP combo PHY */
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unsigned int tx_b_lane_offset;
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unsigned int rx_b_lane_offset;
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/* true, if PCS block has no separate SW_RESET register */
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bool no_pcs_sw_reset;
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};
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/**
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@ -750,6 +835,10 @@ static const char * const qmp_v3_phy_clk_l[] = {
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"aux", "cfg_ahb", "ref", "com_aux",
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};
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static const char * const sdm845_ufs_phy_clk_l[] = {
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"ref", "ref_aux",
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};
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/* list of resets */
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static const char * const msm8996_pciephy_reset_l[] = {
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"phy", "common", "cfg",
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@ -919,6 +1008,35 @@ static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
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.pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
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};
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static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
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.type = PHY_TYPE_UFS,
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.nlanes = 2,
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.serdes_tbl = sdm845_ufsphy_serdes_tbl,
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.serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
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.tx_tbl = sdm845_ufsphy_tx_tbl,
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.tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
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.rx_tbl = sdm845_ufsphy_rx_tbl,
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.rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
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.pcs_tbl = sdm845_ufsphy_pcs_tbl,
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.pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
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.clk_list = sdm845_ufs_phy_clk_l,
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.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
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.vreg_list = qmp_phy_vreg_l,
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.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
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.regs = sdm845_ufsphy_regs_layout,
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.start_ctrl = SERDES_START,
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.pwrdn_ctrl = SW_PWRDN,
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.mask_pcs_ready = PCS_READY,
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.is_dual_lane_phy = true,
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.tx_b_lane_offset = 0x400,
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.rx_b_lane_offset = 0x400,
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.no_pcs_sw_reset = true,
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};
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static void qcom_qmp_phy_configure(void __iomem *base,
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const unsigned int *regs,
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const struct qmp_phy_init_tbl tbl[],
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@ -1130,6 +1248,14 @@ static int qcom_qmp_phy_init(struct phy *phy)
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qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
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/*
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* UFS PHY requires the deassert of software reset before serdes start.
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* For UFS PHYs that do not have software reset control bits, defer
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* starting serdes until the power on callback.
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*/
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if ((cfg->type == PHY_TYPE_UFS) && cfg->no_pcs_sw_reset)
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goto out;
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/*
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* Pull out PHY from POWER DOWN state.
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* This is active low enable signal to power-down PHY.
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@ -1159,6 +1285,7 @@ static int qcom_qmp_phy_init(struct phy *phy)
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}
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qmp->phy_initialized = true;
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out:
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return ret;
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err_pcs_ready:
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@ -1181,7 +1308,8 @@ static int qcom_qmp_phy_exit(struct phy *phy)
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clk_disable_unprepare(qphy->pipe_clk);
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/* PHY reset */
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qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
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if (!cfg->no_pcs_sw_reset)
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qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
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/* stop SerDes and Phy-Coding-Sublayer */
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qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
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@ -1199,6 +1327,44 @@ static int qcom_qmp_phy_exit(struct phy *phy)
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return 0;
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}
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static int qcom_qmp_phy_poweron(struct phy *phy)
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{
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struct qmp_phy *qphy = phy_get_drvdata(phy);
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struct qcom_qmp *qmp = qphy->qmp;
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const struct qmp_phy_cfg *cfg = qmp->cfg;
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void __iomem *pcs = qphy->pcs;
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void __iomem *status;
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unsigned int mask, val;
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int ret = 0;
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if (cfg->type != PHY_TYPE_UFS)
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return 0;
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/*
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* For UFS PHY that has not software reset control, serdes start
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* should only happen when UFS driver explicitly calls phy_power_on
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* after it deasserts software reset.
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*/
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if (cfg->no_pcs_sw_reset && !qmp->phy_initialized &&
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(qmp->init_count != 0)) {
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/* start SerDes and Phy-Coding-Sublayer */
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qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
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status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
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mask = cfg->mask_pcs_ready;
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ret = readl_poll_timeout(status, val, !(val & mask), 1,
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PHY_INIT_COMPLETE_TIMEOUT);
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if (ret) {
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dev_err(qmp->dev, "phy initialization timed-out\n");
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return ret;
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}
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qmp->phy_initialized = true;
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}
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return ret;
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}
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static int qcom_qmp_phy_set_mode(struct phy *phy, enum phy_mode mode)
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{
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struct qmp_phy *qphy = phy_get_drvdata(phy);
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@ -1428,6 +1594,7 @@ static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
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static const struct phy_ops qcom_qmp_phy_gen_ops = {
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.init = qcom_qmp_phy_init,
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.exit = qcom_qmp_phy_exit,
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.power_on = qcom_qmp_phy_poweron,
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.set_mode = qcom_qmp_phy_set_mode,
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.owner = THIS_MODULE,
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};
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@ -1530,6 +1697,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
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}, {
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.compatible = "qcom,sdm845-qmp-usb3-uni-phy",
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.data = &qmp_v3_usb3_uniphy_cfg,
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}, {
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.compatible = "qcom,sdm845-qmp-ufs-phy",
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.data = &sdm845_ufsphy_cfg,
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},
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{ },
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};
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@ -184,6 +184,8 @@
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#define QSERDES_V3_COM_VCO_TUNE2_MODE0 0x0f8
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#define QSERDES_V3_COM_VCO_TUNE1_MODE1 0x0fc
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#define QSERDES_V3_COM_VCO_TUNE2_MODE1 0x100
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#define QSERDES_V3_COM_VCO_TUNE_INITVAL1 0x104
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#define QSERDES_V3_COM_VCO_TUNE_INITVAL2 0x108
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#define QSERDES_V3_COM_VCO_TUNE_TIMER1 0x11c
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#define QSERDES_V3_COM_VCO_TUNE_TIMER2 0x120
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#define QSERDES_V3_COM_CLK_SELECT 0x138
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@ -211,8 +213,13 @@
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/* Only for QMP V3 PHY - RX registers */
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#define QSERDES_V3_RX_UCDR_SO_GAIN_HALF 0x00c
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#define QSERDES_V3_RX_UCDR_SO_GAIN 0x014
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#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF 0x024
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#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER 0x028
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#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN 0x02c
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#define QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN 0x030
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#define QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034
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#define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c
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#define QSERDES_V3_RX_UCDR_PI_CONTROLS 0x044
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#define QSERDES_V3_RX_RX_TERM_BW 0x07c
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#define QSERDES_V3_RX_VGA_CAL_CNTRL1 0x0bc
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#define QSERDES_V3_RX_VGA_CAL_CNTRL2 0x0c0
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@ -239,6 +246,8 @@
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#define QPHY_V3_PCS_TXMGN_V3 0x018
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#define QPHY_V3_PCS_TXMGN_V4 0x01c
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#define QPHY_V3_PCS_TXMGN_LS 0x020
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#define QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL 0x02c
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#define QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL 0x034
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#define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024
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#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0 0x028
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#define QPHY_V3_PCS_TXDEEMPH_M6DB_V1 0x02c
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@ -275,6 +284,12 @@
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#define QPHY_V3_PCS_FLL_CNT_VAL_L 0x0cc
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#define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL 0x0d0
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#define QPHY_V3_PCS_FLL_MAN_CODE 0x0d4
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#define QPHY_V3_PCS_RX_SYM_RESYNC_CTRL 0x134
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#define QPHY_V3_PCS_RX_MIN_HIBERN8_TIME 0x138
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#define QPHY_V3_PCS_RX_SIGDET_CTRL1 0x13c
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#define QPHY_V3_PCS_RX_SIGDET_CTRL2 0x140
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#define QPHY_V3_PCS_TX_MID_TERM_CTRL1 0x1bc
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#define QPHY_V3_PCS_MULTI_LANE_CTRL1 0x1c4
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#define QPHY_V3_PCS_RX_SIGDET_LVL 0x1d8
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#define QPHY_V3_PCS_REFGEN_REQ_CONFIG1 0x20c
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#define QPHY_V3_PCS_REFGEN_REQ_CONFIG2 0x210
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