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drm/i915: Add PSR2 selective update status registers and bits definitions 

This register contains how many blocks was sent in the past selective
updates.
Those registers are not kept set all the times but polling it after flip
can show the values corresponding to the last 8 frames.

v2: Improved macros(Dhinakaran)

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190117205548.28378-3-jose.souza@intel.com
This commit is contained in:
José Roberto de Souza 2019-01-17 12:55:47 -08:00
parent 47c6cd54ef
commit cc8853f57e
1 changed files with 9 additions and 0 deletions
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9
drivers/gpu/drm/i915/i915_reg.h
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@ -4272,6 +4272,15 @@ enum {
#define EDP_PSR2_STATUS_STATE_MASK (0xf << 28)
#define EDP_PSR2_STATUS_STATE_SHIFT 28
#define _PSR2_SU_STATUS_0 0x6F914
#define _PSR2_SU_STATUS_1 0x6F918
#define _PSR2_SU_STATUS_2 0x6F91C
#define _PSR2_SU_STATUS(index) _MMIO(_PICK_EVEN((index), _PSR2_SU_STATUS_0, _PSR2_SU_STATUS_1))
#define PSR2_SU_STATUS(frame) (_PSR2_SU_STATUS((frame) / 3))
#define PSR2_SU_STATUS_SHIFT(frame) (((frame) % 3) * 10)
#define PSR2_SU_STATUS_MASK(frame) (0x3ff << PSR2_SU_STATUS_SHIFT(frame))
#define PSR2_SU_STATUS_FRAMES 8
/* VGA port control */
#define ADPA _MMIO(0x61100)
#define PCH_ADPA _MMIO(0xe1100)