mirror of https://gitee.com/openkylin/linux.git
net: hns3: Add tc-based TM support for sriov enabled port
When sriov is enabled and TM is in tc-based mode, vf's TM parameters is not set in TM initialization process. This patch add the tc_based TM support for sriov enabled using the information in vport struct. Signed-off-by: Yunsheng Lin <linyunsheng@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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parent
0a5677d39e
commit
cc9bb43ab3
drivers/net/ethernet/hisilicon/hns3/hns3pf
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@ -388,13 +388,13 @@ static int hclge_tm_pri_schd_mode_cfg(struct hclge_dev *hdev, u8 pri_id)
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return hclge_cmd_send(&hdev->hw, &desc, 1);
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}
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static int hclge_tm_qs_schd_mode_cfg(struct hclge_dev *hdev, u16 qs_id)
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static int hclge_tm_qs_schd_mode_cfg(struct hclge_dev *hdev, u16 qs_id, u8 mode)
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{
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struct hclge_desc desc;
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hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_QS_SCH_MODE_CFG, false);
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if (hdev->tm_info.tc_info[qs_id].tc_sch_mode == HCLGE_SCH_MODE_DWRR)
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if (mode == HCLGE_SCH_MODE_DWRR)
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desc.data[1] = cpu_to_le32(HCLGE_TM_TX_SCHD_DWRR_MSK);
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else
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desc.data[1] = 0;
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@ -638,17 +638,18 @@ static int hclge_tm_pri_q_qs_cfg(struct hclge_dev *hdev)
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{
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struct hclge_vport *vport = hdev->vport;
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int ret;
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u32 i;
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u32 i, k;
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if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) {
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/* Cfg qs -> pri mapping, one by one mapping */
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for (k = 0; k < hdev->num_alloc_vport; k++)
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for (i = 0; i < hdev->tm_info.num_tc; i++) {
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ret = hclge_tm_qs_to_pri_map_cfg(hdev, i, i);
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ret = hclge_tm_qs_to_pri_map_cfg(
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hdev, vport[k].qs_offset + i, i);
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if (ret)
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return ret;
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}
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} else if (hdev->tx_sch_mode == HCLGE_FLAG_VNET_BASE_SCH_MODE) {
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int k;
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/* Cfg qs -> pri mapping, qs = tc, pri = vf, 8 qs -> 1 pri */
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for (k = 0; k < hdev->num_alloc_vport; k++)
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for (i = 0; i < HNAE3_MAX_TC; i++) {
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@ -797,10 +798,11 @@ static int hclge_tm_pri_shaper_cfg(struct hclge_dev *hdev)
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static int hclge_tm_pri_tc_base_dwrr_cfg(struct hclge_dev *hdev)
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{
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struct hclge_vport *vport = hdev->vport;
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struct hclge_pg_info *pg_info;
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u8 dwrr;
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int ret;
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u32 i;
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u32 i, k;
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for (i = 0; i < hdev->tm_info.num_tc; i++) {
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pg_info =
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@ -811,10 +813,14 @@ static int hclge_tm_pri_tc_base_dwrr_cfg(struct hclge_dev *hdev)
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if (ret)
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return ret;
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ret = hclge_tm_qs_weight_cfg(hdev, i, dwrr);
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for (k = 0; k < hdev->num_alloc_vport; k++) {
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ret = hclge_tm_qs_weight_cfg(
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hdev, vport[k].qs_offset + i,
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vport[k].dwrr);
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if (ret)
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return ret;
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}
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}
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return 0;
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}
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@ -944,7 +950,10 @@ static int hclge_tm_schd_mode_vnet_base_cfg(struct hclge_vport *vport)
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return ret;
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for (i = 0; i < kinfo->num_tc; i++) {
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ret = hclge_tm_qs_schd_mode_cfg(hdev, vport->qs_offset + i);
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u8 sch_mode = hdev->tm_info.tc_info[i].tc_sch_mode;
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ret = hclge_tm_qs_schd_mode_cfg(hdev, vport->qs_offset + i,
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sch_mode);
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if (ret)
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return ret;
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}
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@ -956,7 +965,7 @@ static int hclge_tm_lvl34_schd_mode_cfg(struct hclge_dev *hdev)
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{
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struct hclge_vport *vport = hdev->vport;
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int ret;
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u8 i;
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u8 i, k;
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if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) {
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for (i = 0; i < hdev->tm_info.num_tc; i++) {
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@ -964,10 +973,14 @@ static int hclge_tm_lvl34_schd_mode_cfg(struct hclge_dev *hdev)
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if (ret)
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return ret;
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ret = hclge_tm_qs_schd_mode_cfg(hdev, i);
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for (k = 0; k < hdev->num_alloc_vport; k++) {
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ret = hclge_tm_qs_schd_mode_cfg(
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hdev, vport[k].qs_offset + i,
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HCLGE_SCH_MODE_DWRR);
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if (ret)
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return ret;
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}
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}
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} else {
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for (i = 0; i < hdev->num_alloc_vport; i++) {
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ret = hclge_tm_schd_mode_vnet_base_cfg(vport);
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