mirror of https://gitee.com/openkylin/linux.git
drm/amdgpu: add EDC support for CZ (v3)
This adds EDC support for CZ. EDC = Error Correction and Detection This code properly initializes the EDC hardware and resets the error counts. This is done in late_init since it requires the IB pool which is not initialized during hw_init. v2: fix the IB size as noted by Felix, fix shader pgm register programming v3: use the IB for the shaders as suggested by Christian Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher
parent
aa5e24e5f8
commit
ccba7691a5
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@ -964,6 +964,322 @@ static int gfx_v8_0_mec_init(struct amdgpu_device *adev)
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return 0;
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}
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static const u32 vgpr_init_compute_shader[] =
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{
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0x7e000209, 0x7e020208,
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0x7e040207, 0x7e060206,
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0x7e080205, 0x7e0a0204,
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0x7e0c0203, 0x7e0e0202,
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0x7e100201, 0x7e120200,
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0x7e140209, 0x7e160208,
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0x7e180207, 0x7e1a0206,
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0x7e1c0205, 0x7e1e0204,
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0x7e200203, 0x7e220202,
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0x7e240201, 0x7e260200,
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0x7e280209, 0x7e2a0208,
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0x7e2c0207, 0x7e2e0206,
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0x7e300205, 0x7e320204,
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0x7e340203, 0x7e360202,
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0x7e380201, 0x7e3a0200,
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0x7e3c0209, 0x7e3e0208,
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0x7e400207, 0x7e420206,
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0x7e440205, 0x7e460204,
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0x7e480203, 0x7e4a0202,
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0x7e4c0201, 0x7e4e0200,
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0x7e500209, 0x7e520208,
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0x7e540207, 0x7e560206,
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0x7e580205, 0x7e5a0204,
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0x7e5c0203, 0x7e5e0202,
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0x7e600201, 0x7e620200,
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0x7e640209, 0x7e660208,
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0x7e680207, 0x7e6a0206,
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0x7e6c0205, 0x7e6e0204,
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0x7e700203, 0x7e720202,
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0x7e740201, 0x7e760200,
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0x7e780209, 0x7e7a0208,
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0x7e7c0207, 0x7e7e0206,
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0xbf8a0000, 0xbf810000,
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};
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static const u32 sgpr_init_compute_shader[] =
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{
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0xbe8a0100, 0xbe8c0102,
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0xbe8e0104, 0xbe900106,
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0xbe920108, 0xbe940100,
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0xbe960102, 0xbe980104,
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0xbe9a0106, 0xbe9c0108,
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0xbe9e0100, 0xbea00102,
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0xbea20104, 0xbea40106,
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0xbea60108, 0xbea80100,
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0xbeaa0102, 0xbeac0104,
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0xbeae0106, 0xbeb00108,
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0xbeb20100, 0xbeb40102,
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0xbeb60104, 0xbeb80106,
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0xbeba0108, 0xbebc0100,
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0xbebe0102, 0xbec00104,
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0xbec20106, 0xbec40108,
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0xbec60100, 0xbec80102,
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0xbee60004, 0xbee70005,
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0xbeea0006, 0xbeeb0007,
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0xbee80008, 0xbee90009,
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0xbefc0000, 0xbf8a0000,
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0xbf810000, 0x00000000,
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};
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static const u32 vgpr_init_regs[] =
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{
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mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xffffffff,
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mmCOMPUTE_RESOURCE_LIMITS, 0,
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mmCOMPUTE_NUM_THREAD_X, 256*4,
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mmCOMPUTE_NUM_THREAD_Y, 1,
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mmCOMPUTE_NUM_THREAD_Z, 1,
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mmCOMPUTE_PGM_RSRC2, 20,
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mmCOMPUTE_USER_DATA_0, 0xedcedc00,
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mmCOMPUTE_USER_DATA_1, 0xedcedc01,
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mmCOMPUTE_USER_DATA_2, 0xedcedc02,
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mmCOMPUTE_USER_DATA_3, 0xedcedc03,
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mmCOMPUTE_USER_DATA_4, 0xedcedc04,
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mmCOMPUTE_USER_DATA_5, 0xedcedc05,
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mmCOMPUTE_USER_DATA_6, 0xedcedc06,
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mmCOMPUTE_USER_DATA_7, 0xedcedc07,
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mmCOMPUTE_USER_DATA_8, 0xedcedc08,
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mmCOMPUTE_USER_DATA_9, 0xedcedc09,
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};
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static const u32 sgpr1_init_regs[] =
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{
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mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0x0f,
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mmCOMPUTE_RESOURCE_LIMITS, 0x1000000,
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mmCOMPUTE_NUM_THREAD_X, 256*5,
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mmCOMPUTE_NUM_THREAD_Y, 1,
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mmCOMPUTE_NUM_THREAD_Z, 1,
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mmCOMPUTE_PGM_RSRC2, 20,
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mmCOMPUTE_USER_DATA_0, 0xedcedc00,
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mmCOMPUTE_USER_DATA_1, 0xedcedc01,
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mmCOMPUTE_USER_DATA_2, 0xedcedc02,
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mmCOMPUTE_USER_DATA_3, 0xedcedc03,
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mmCOMPUTE_USER_DATA_4, 0xedcedc04,
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mmCOMPUTE_USER_DATA_5, 0xedcedc05,
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mmCOMPUTE_USER_DATA_6, 0xedcedc06,
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mmCOMPUTE_USER_DATA_7, 0xedcedc07,
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mmCOMPUTE_USER_DATA_8, 0xedcedc08,
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mmCOMPUTE_USER_DATA_9, 0xedcedc09,
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};
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static const u32 sgpr2_init_regs[] =
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{
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mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xf0,
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mmCOMPUTE_RESOURCE_LIMITS, 0x1000000,
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mmCOMPUTE_NUM_THREAD_X, 256*5,
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mmCOMPUTE_NUM_THREAD_Y, 1,
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mmCOMPUTE_NUM_THREAD_Z, 1,
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mmCOMPUTE_PGM_RSRC2, 20,
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mmCOMPUTE_USER_DATA_0, 0xedcedc00,
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mmCOMPUTE_USER_DATA_1, 0xedcedc01,
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mmCOMPUTE_USER_DATA_2, 0xedcedc02,
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mmCOMPUTE_USER_DATA_3, 0xedcedc03,
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mmCOMPUTE_USER_DATA_4, 0xedcedc04,
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mmCOMPUTE_USER_DATA_5, 0xedcedc05,
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mmCOMPUTE_USER_DATA_6, 0xedcedc06,
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mmCOMPUTE_USER_DATA_7, 0xedcedc07,
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mmCOMPUTE_USER_DATA_8, 0xedcedc08,
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mmCOMPUTE_USER_DATA_9, 0xedcedc09,
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};
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static const u32 sec_ded_counter_registers[] =
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{
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mmCPC_EDC_ATC_CNT,
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mmCPC_EDC_SCRATCH_CNT,
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mmCPC_EDC_UCODE_CNT,
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mmCPF_EDC_ATC_CNT,
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mmCPF_EDC_ROQ_CNT,
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mmCPF_EDC_TAG_CNT,
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mmCPG_EDC_ATC_CNT,
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mmCPG_EDC_DMA_CNT,
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mmCPG_EDC_TAG_CNT,
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mmDC_EDC_CSINVOC_CNT,
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mmDC_EDC_RESTORE_CNT,
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mmDC_EDC_STATE_CNT,
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mmGDS_EDC_CNT,
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mmGDS_EDC_GRBM_CNT,
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mmGDS_EDC_OA_DED,
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mmSPI_EDC_CNT,
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mmSQC_ATC_EDC_GATCL1_CNT,
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mmSQC_EDC_CNT,
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mmSQ_EDC_DED_CNT,
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mmSQ_EDC_INFO,
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mmSQ_EDC_SEC_CNT,
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mmTCC_EDC_CNT,
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mmTCP_ATC_EDC_GATCL1_CNT,
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mmTCP_EDC_CNT,
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mmTD_EDC_CNT
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};
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static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
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{
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struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
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struct amdgpu_ib ib;
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struct fence *f = NULL;
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int r, i;
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u32 tmp;
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unsigned total_size, vgpr_offset, sgpr_offset;
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u64 gpu_addr;
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/* only supported on CZ */
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if (adev->asic_type != CHIP_CARRIZO)
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return 0;
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/* bail if the compute ring is not ready */
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if (!ring->ready)
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return 0;
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tmp = RREG32(mmGB_EDC_MODE);
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WREG32(mmGB_EDC_MODE, 0);
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total_size =
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(((ARRAY_SIZE(vgpr_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
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total_size +=
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(((ARRAY_SIZE(sgpr1_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
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total_size +=
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(((ARRAY_SIZE(sgpr2_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
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total_size = ALIGN(total_size, 256);
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vgpr_offset = total_size;
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total_size += ALIGN(sizeof(vgpr_init_compute_shader), 256);
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sgpr_offset = total_size;
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total_size += sizeof(sgpr_init_compute_shader);
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/* allocate an indirect buffer to put the commands in */
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memset(&ib, 0, sizeof(ib));
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r = amdgpu_ib_get(ring, NULL, total_size, &ib);
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if (r) {
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DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
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return r;
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}
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/* load the compute shaders */
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for (i = 0; i < ARRAY_SIZE(vgpr_init_compute_shader); i++)
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ib.ptr[i + (vgpr_offset / 4)] = vgpr_init_compute_shader[i];
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for (i = 0; i < ARRAY_SIZE(sgpr_init_compute_shader); i++)
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ib.ptr[i + (sgpr_offset / 4)] = sgpr_init_compute_shader[i];
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/* init the ib length to 0 */
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ib.length_dw = 0;
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/* VGPR */
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/* write the register state for the compute dispatch */
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for (i = 0; i < ARRAY_SIZE(vgpr_init_regs); i += 2) {
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ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
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ib.ptr[ib.length_dw++] = vgpr_init_regs[i] - PACKET3_SET_SH_REG_START;
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ib.ptr[ib.length_dw++] = vgpr_init_regs[i + 1];
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}
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/* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
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gpu_addr = (ib.gpu_addr + (u64)vgpr_offset) >> 8;
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ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
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ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
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ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
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ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
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/* write dispatch packet */
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ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
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ib.ptr[ib.length_dw++] = 8; /* x */
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ib.ptr[ib.length_dw++] = 1; /* y */
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ib.ptr[ib.length_dw++] = 1; /* z */
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ib.ptr[ib.length_dw++] =
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REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
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/* write CS partial flush packet */
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ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
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ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
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/* SGPR1 */
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/* write the register state for the compute dispatch */
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for (i = 0; i < ARRAY_SIZE(sgpr1_init_regs); i += 2) {
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ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
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ib.ptr[ib.length_dw++] = sgpr1_init_regs[i] - PACKET3_SET_SH_REG_START;
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ib.ptr[ib.length_dw++] = sgpr1_init_regs[i + 1];
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}
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/* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
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gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
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ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
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ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
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ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
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ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
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/* write dispatch packet */
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ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
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ib.ptr[ib.length_dw++] = 8; /* x */
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ib.ptr[ib.length_dw++] = 1; /* y */
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ib.ptr[ib.length_dw++] = 1; /* z */
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ib.ptr[ib.length_dw++] =
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REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
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/* write CS partial flush packet */
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ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
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ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
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/* SGPR2 */
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/* write the register state for the compute dispatch */
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for (i = 0; i < ARRAY_SIZE(sgpr2_init_regs); i += 2) {
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ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
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ib.ptr[ib.length_dw++] = sgpr2_init_regs[i] - PACKET3_SET_SH_REG_START;
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ib.ptr[ib.length_dw++] = sgpr2_init_regs[i + 1];
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}
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/* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
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gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
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ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
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ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
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ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
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ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
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/* write dispatch packet */
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ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
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ib.ptr[ib.length_dw++] = 8; /* x */
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ib.ptr[ib.length_dw++] = 1; /* y */
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ib.ptr[ib.length_dw++] = 1; /* z */
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ib.ptr[ib.length_dw++] =
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REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
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/* write CS partial flush packet */
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ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
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ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
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/* shedule the ib on the ring */
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r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, &ib, 1, NULL,
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AMDGPU_FENCE_OWNER_UNDEFINED,
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&f);
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if (r) {
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DRM_ERROR("amdgpu: ib submit failed (%d).\n", r);
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goto fail;
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}
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/* wait for the GPU to finish processing the IB */
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r = fence_wait(f, false);
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if (r) {
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DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
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goto fail;
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}
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tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, DED_MODE, 2);
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tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, PROP_FED, 1);
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WREG32(mmGB_EDC_MODE, tmp);
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tmp = RREG32(mmCC_GC_EDC_CONFIG);
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tmp = REG_SET_FIELD(tmp, CC_GC_EDC_CONFIG, DIS_EDC, 0) | 1;
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WREG32(mmCC_GC_EDC_CONFIG, tmp);
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/* read back registers to clear the counters */
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for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++)
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RREG32(sec_ded_counter_registers[i]);
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fail:
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fence_put(f);
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amdgpu_ib_free(adev, &ib);
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return r;
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}
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static void gfx_v8_0_gpu_early_init(struct amdgpu_device *adev)
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{
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u32 gb_addr_config;
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@ -4458,6 +4774,19 @@ static int gfx_v8_0_early_init(void *handle)
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return 0;
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}
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static int gfx_v8_0_late_init(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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int r;
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/* requires IBs so do in late init after IB pool is initialized */
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r = gfx_v8_0_do_edc_gpr_workarounds(adev);
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if (r)
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return r;
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return 0;
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}
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static int gfx_v8_0_set_powergating_state(void *handle,
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enum amd_powergating_state state)
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{
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@ -4995,7 +5324,7 @@ static int gfx_v8_0_priv_inst_irq(struct amdgpu_device *adev,
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const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
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.early_init = gfx_v8_0_early_init,
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.late_init = NULL,
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.late_init = gfx_v8_0_late_init,
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.sw_init = gfx_v8_0_sw_init,
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.sw_fini = gfx_v8_0_sw_fini,
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.hw_init = gfx_v8_0_hw_init,
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