mirror of https://gitee.com/openkylin/linux.git
b43: Add parts of LP-PHY TX power control
This adds the initial parts of the LP-PHY TX power control. This also adds helper functions for bulk access of LP tables. Signed-off-by: Michael Buesch <mb@bu3sch.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Michael Buesch
John W. Linville
parent
7a94708060
commit
ce1a9ee33a
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@ -120,6 +120,9 @@
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#define B43_MMIO_IFSCTL 0x688 /* Interframe space control */
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#define B43_MMIO_IFSCTL_USE_EDCF 0x0004
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#define B43_MMIO_POWERUP_DELAY 0x6A8
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#define B43_MMIO_BTCOEX_CTL 0x6B4 /* Bluetooth Coexistence Control */
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#define B43_MMIO_BTCOEX_STAT 0x6B6 /* Bluetooth Coexistence Status */
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#define B43_MMIO_BTCOEX_TXCTL 0x6B8 /* Bluetooth Coexistence Transmit Control */
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/* SPROM boardflags_lo values */
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#define B43_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
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@ -23,6 +23,7 @@
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*/
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#include "b43.h"
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#include "main.h"
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#include "phy_lp.h"
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#include "phy_common.h"
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#include "tables_lpphy.h"
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@ -267,13 +268,185 @@ static void lpphy_radio_init(struct b43_wldev *dev)
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}
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}
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/* Read the TX power control mode from hardware. */
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static void lpphy_read_tx_pctl_mode_from_hardware(struct b43_wldev *dev)
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{
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struct b43_phy_lp *lpphy = dev->phy.lp;
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u16 ctl;
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ctl = b43_phy_read(dev, B43_LPPHY_TX_PWR_CTL_CMD);
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switch (ctl & B43_LPPHY_TX_PWR_CTL_CMD_MODE) {
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case B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF:
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lpphy->txpctl_mode = B43_LPPHY_TXPCTL_OFF;
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break;
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case B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW:
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lpphy->txpctl_mode = B43_LPPHY_TXPCTL_SW;
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break;
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case B43_LPPHY_TX_PWR_CTL_CMD_MODE_HW:
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lpphy->txpctl_mode = B43_LPPHY_TXPCTL_HW;
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break;
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default:
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lpphy->txpctl_mode = B43_LPPHY_TXPCTL_UNKNOWN;
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B43_WARN_ON(1);
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break;
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}
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}
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/* Set the TX power control mode in hardware. */
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static void lpphy_write_tx_pctl_mode_to_hardware(struct b43_wldev *dev)
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{
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struct b43_phy_lp *lpphy = dev->phy.lp;
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u16 ctl;
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switch (lpphy->txpctl_mode) {
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case B43_LPPHY_TXPCTL_OFF:
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ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF;
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break;
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case B43_LPPHY_TXPCTL_HW:
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ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_HW;
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break;
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case B43_LPPHY_TXPCTL_SW:
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ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW;
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break;
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default:
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ctl = 0;
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B43_WARN_ON(1);
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}
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b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
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(u16)~B43_LPPHY_TX_PWR_CTL_CMD_MODE, ctl);
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}
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static void lpphy_set_tx_power_control(struct b43_wldev *dev,
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enum b43_lpphy_txpctl_mode mode)
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{
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struct b43_phy_lp *lpphy = dev->phy.lp;
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enum b43_lpphy_txpctl_mode oldmode;
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oldmode = lpphy->txpctl_mode;
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lpphy_read_tx_pctl_mode_from_hardware(dev);
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if (lpphy->txpctl_mode == mode)
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return;
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lpphy->txpctl_mode = mode;
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if (oldmode == B43_LPPHY_TXPCTL_HW) {
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//TODO Update TX Power NPT
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//TODO Clear all TX Power offsets
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} else {
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if (mode == B43_LPPHY_TXPCTL_HW) {
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//TODO Recalculate target TX power
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b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
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0xFF80, lpphy->tssi_idx);
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b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM,
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0x8FFF, ((u16)lpphy->tssi_npt << 16));
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//TODO Set "TSSI Transmit Count" variable to total transmitted frame count
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//TODO Disable TX gain override
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lpphy->tx_pwr_idx_over = -1;
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}
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}
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if (dev->phy.rev >= 2) {
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if (mode == B43_LPPHY_TXPCTL_HW)
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b43_phy_maskset(dev, B43_PHY_OFDM(0xD0), 0xFD, 0x2);
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else
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b43_phy_maskset(dev, B43_PHY_OFDM(0xD0), 0xFD, 0);
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}
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lpphy_write_tx_pctl_mode_to_hardware(dev);
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}
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static void lpphy_set_tx_power_by_index(struct b43_wldev *dev, u8 index)
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{
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struct b43_phy_lp *lpphy = dev->phy.lp;
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lpphy->tx_pwr_idx_over = index;
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if (lpphy->txpctl_mode != B43_LPPHY_TXPCTL_OFF)
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lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_SW);
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//TODO
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}
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static void lpphy_btcoex_override(struct b43_wldev *dev)
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{
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b43_write16(dev, B43_MMIO_BTCOEX_CTL, 0x3);
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b43_write16(dev, B43_MMIO_BTCOEX_TXCTL, 0xFF);
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}
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static void lpphy_pr41573_workaround(struct b43_wldev *dev)
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{
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struct b43_phy_lp *lpphy = dev->phy.lp;
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u32 *saved_tab;
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const unsigned int saved_tab_size = 256;
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enum b43_lpphy_txpctl_mode txpctl_mode;
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s8 tx_pwr_idx_over;
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u16 tssi_npt, tssi_idx;
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saved_tab = kcalloc(saved_tab_size, sizeof(saved_tab[0]), GFP_KERNEL);
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if (!saved_tab) {
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b43err(dev->wl, "PR41573 failed. Out of memory!\n");
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return;
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}
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lpphy_read_tx_pctl_mode_from_hardware(dev);
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txpctl_mode = lpphy->txpctl_mode;
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tx_pwr_idx_over = lpphy->tx_pwr_idx_over;
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tssi_npt = lpphy->tssi_npt;
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tssi_idx = lpphy->tssi_idx;
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if (dev->phy.rev < 2) {
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b43_lptab_read_bulk(dev, B43_LPTAB32(10, 0x140),
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saved_tab_size, saved_tab);
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} else {
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b43_lptab_read_bulk(dev, B43_LPTAB32(7, 0x140),
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saved_tab_size, saved_tab);
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}
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//TODO
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kfree(saved_tab);
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}
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static void lpphy_calibration(struct b43_wldev *dev)
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{
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struct b43_phy_lp *lpphy = dev->phy.lp;
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enum b43_lpphy_txpctl_mode saved_pctl_mode;
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b43_mac_suspend(dev);
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lpphy_btcoex_override(dev);
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lpphy_read_tx_pctl_mode_from_hardware(dev);
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saved_pctl_mode = lpphy->txpctl_mode;
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lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF);
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//TODO Perform transmit power table I/Q LO calibration
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if ((dev->phy.rev == 0) && (saved_pctl_mode != B43_LPPHY_TXPCTL_OFF))
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lpphy_pr41573_workaround(dev);
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//TODO If a full calibration has not been performed on this channel yet, perform PAPD TX-power calibration
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lpphy_set_tx_power_control(dev, saved_pctl_mode);
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//TODO Perform I/Q calibration with a single control value set
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b43_mac_enable(dev);
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}
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/* Initialize TX power control */
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static void lpphy_tx_pctl_init(struct b43_wldev *dev)
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{
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if (0/*FIXME HWPCTL capable */) {
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//TODO
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} else { /* This device is only software TX power control capable. */
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if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
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//TODO
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} else {
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//TODO
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}
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//TODO set BB multiplier to 0x0096
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}
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}
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static int b43_lpphy_op_init(struct b43_wldev *dev)
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{
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/* TODO: band SPROM */
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lpphy_baseband_init(dev);
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lpphy_radio_init(dev);
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//TODO
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//TODO calibrate RC
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//TODO set channel
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lpphy_tx_pctl_init(dev);
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//TODO full calib
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return 0;
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}
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@ -247,6 +247,10 @@
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#define B43_LPPHY_FOURWIRE_CTL B43_PHY_OFDM(0xA2) /* fourwire Control */
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#define B43_LPPHY_CPA_TAILCOUNT_VAL B43_PHY_OFDM(0xA3) /* CPA TailCount Value */
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#define B43_LPPHY_TX_PWR_CTL_CMD B43_PHY_OFDM(0xA4) /* TX Power Control Cmd */
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#define B43_LPPHY_TX_PWR_CTL_CMD_MODE 0xE000 /* TX power control mode mask */
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#define B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF 0x0000 /* TX power control is OFF */
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#define B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW 0x8000 /* TX power control is SOFTWARE */
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#define B43_LPPHY_TX_PWR_CTL_CMD_MODE_HW 0xE000 /* TX power control is HARDWARE */
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#define B43_LPPHY_TX_PWR_CTL_NNUM B43_PHY_OFDM(0xA5) /* TX Power Control Nnum */
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#define B43_LPPHY_TX_PWR_CTL_IDLETSSI B43_PHY_OFDM(0xA6) /* TX Power Control IdleTssi */
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#define B43_LPPHY_TX_PWR_CTL_TARGETPWR B43_PHY_OFDM(0xA7) /* TX Power Control TargetPower */
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@ -802,7 +806,17 @@
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enum b43_lpphy_txpctl_mode {
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B43_LPPHY_TXPCTL_UNKNOWN = 0,
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B43_LPPHY_TXPCTL_OFF, /* TX power control is OFF */
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B43_LPPHY_TXPCTL_SW, /* TX power control is set to Software */
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B43_LPPHY_TXPCTL_HW, /* TX power control is set to Hardware */
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};
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struct b43_phy_lp {
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/* Current TX power control mode. */
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enum b43_lpphy_txpctl_mode txpctl_mode;
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/* Transmit isolation medium band */
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u8 tx_isolation_med_band; /* FIXME initial value? */
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/* Transmit isolation low band */
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@ -814,7 +828,7 @@ struct b43_phy_lp {
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u8 rx_pwr_offset; /* FIXME initial value? */
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/* TSSI transmit count */
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u16 tssi_tx_count; /* FIXME initial value? */
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u16 tssi_tx_count;
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/* TSSI index */
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u16 tssi_idx; /* FIXME initial value? */
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/* TSSI npt */
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@ -303,6 +303,36 @@ u32 b43_lptab_read(struct b43_wldev *dev, u32 offset)
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return value;
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}
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void b43_lptab_read_bulk(struct b43_wldev *dev, u32 offset,
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unsigned int nr_elements, void *_data)
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{
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u32 type, value;
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u8 *data = _data;
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unsigned int i;
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type = offset & B43_LPTAB_TYPEMASK;
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for (i = 0; i < nr_elements; i++) {
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value = b43_lptab_read(dev, offset);
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switch (type) {
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case B43_LPTAB_8BIT:
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*data = value;
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data++;
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break;
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case B43_LPTAB_16BIT:
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*((u16 *)data) = value;
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data += 2;
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break;
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case B43_LPTAB_32BIT:
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*((u32 *)data) = value;
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data += 4;
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break;
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default:
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B43_WARN_ON(1);
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}
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offset++;
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}
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}
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void b43_lptab_write(struct b43_wldev *dev, u32 offset, u32 value)
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{
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u32 type;
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@ -331,3 +361,34 @@ void b43_lptab_write(struct b43_wldev *dev, u32 offset, u32 value)
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B43_WARN_ON(1);
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}
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}
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void b43_lptab_write_bulk(struct b43_wldev *dev, u32 offset,
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unsigned int nr_elements, const void *_data)
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{
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u32 type, value;
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const u8 *data = _data;
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unsigned int i;
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type = offset & B43_LPTAB_TYPEMASK;
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for (i = 0; i < nr_elements; i++) {
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switch (type) {
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case B43_LPTAB_8BIT:
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value = *data;
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data++;
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break;
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case B43_LPTAB_16BIT:
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value = *((u16 *)data);
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data += 2;
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break;
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case B43_LPTAB_32BIT:
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value = *((u32 *)data);
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data += 4;
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break;
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default:
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B43_WARN_ON(1);
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value = 0;
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}
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b43_lptab_write(dev, offset, value);
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offset++;
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}
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}
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@ -17,6 +17,14 @@
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u32 b43_lptab_read(struct b43_wldev *dev, u32 offset);
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void b43_lptab_write(struct b43_wldev *dev, u32 offset, u32 value);
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/* Bulk table access. Note that these functions return the bulk data in
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* host endianness! The returned data is _not_ a bytearray, but an array
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* consisting of nr_elements of the data type. */
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void b43_lptab_read_bulk(struct b43_wldev *dev, u32 offset,
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unsigned int nr_elements, void *data);
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void b43_lptab_write_bulk(struct b43_wldev *dev, u32 offset,
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unsigned int nr_elements, const void *data);
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void b2062_upload_init_table(struct b43_wldev *dev);
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