mirror of https://gitee.com/openkylin/linux.git
pwm: jz4740: Use clocks from TCU driver
The ingenic-timer "TCU" driver provides us with clocks, that can be (un)gated, reparented or reclocked from devicetree, instead of having these settings hardcoded in this driver. The new code now uses a clk pointer per PWM (instead of a clk per pwm-chip before). So the pointer is stored in per-pwm data now. The calls to arch-specific timer code is replaced with standard clock API calls to start and stop each channel's clock. While this driver is devicetree-compatible, it is never (as of now) probed from devicetree, so this change does not introduce a ABI problem with current devicetree files. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Tested-by: Mathieu Malaterre <malat@debian.org> Tested-by: Artur Rojek <contact@artur-rojek.eu> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
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@ -235,6 +235,7 @@ config PWM_IMX_TPM
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config PWM_JZ4740
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tristate "Ingenic JZ47xx PWM support"
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depends on MACH_INGENIC
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depends on COMMON_CLK
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help
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Generic PWM framework driver for Ingenic JZ47xx based
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machines.
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@ -24,7 +24,6 @@
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struct jz4740_pwm_chip {
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struct pwm_chip chip;
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struct clk *clk;
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};
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static inline struct jz4740_pwm_chip *to_jz4740(struct pwm_chip *chip)
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@ -34,6 +33,11 @@ static inline struct jz4740_pwm_chip *to_jz4740(struct pwm_chip *chip)
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static int jz4740_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct jz4740_pwm_chip *jz = to_jz4740(chip);
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struct clk *clk;
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char name[16];
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int err;
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/*
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* Timers 0 and 1 are used for system tasks, so they are unavailable
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* for use as PWMs.
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@ -41,16 +45,33 @@ static int jz4740_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
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if (pwm->hwpwm < 2)
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return -EBUSY;
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jz4740_timer_start(pwm->hwpwm);
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snprintf(name, sizeof(name), "timer%u", pwm->hwpwm);
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clk = clk_get(chip->dev, name);
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if (IS_ERR(clk)) {
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if (PTR_ERR(clk) != -EPROBE_DEFER)
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dev_err(chip->dev, "Failed to get clock: %pe", clk);
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return PTR_ERR(clk);
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}
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err = clk_prepare_enable(clk);
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if (err < 0) {
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clk_put(clk);
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return err;
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}
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pwm_set_chip_data(pwm, clk);
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return 0;
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}
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static void jz4740_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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jz4740_timer_set_ctrl(pwm->hwpwm, 0);
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struct clk *clk = pwm_get_chip_data(pwm);
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jz4740_timer_stop(pwm->hwpwm);
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clk_disable_unprepare(clk);
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clk_put(clk);
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}
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static int jz4740_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
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@ -91,17 +112,22 @@ static int jz4740_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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const struct pwm_state *state)
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{
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struct jz4740_pwm_chip *jz4740 = to_jz4740(pwm->chip);
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struct clk *clk = pwm_get_chip_data(pwm),
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*parent_clk = clk_get_parent(clk);
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unsigned long rate, period, duty;
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unsigned long long tmp;
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unsigned long period, duty;
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unsigned int prescaler = 0;
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uint16_t ctrl;
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int err;
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tmp = (unsigned long long)clk_get_rate(jz4740->clk) * state->period;
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rate = clk_get_rate(parent_clk);
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tmp = (unsigned long long)rate * state->period;
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do_div(tmp, 1000000000);
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period = tmp;
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while (period > 0xffff && prescaler < 6) {
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period >>= 2;
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rate >>= 2;
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++prescaler;
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}
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@ -117,14 +143,18 @@ static int jz4740_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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jz4740_pwm_disable(chip, pwm);
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err = clk_set_rate(clk, rate);
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if (err) {
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dev_err(chip->dev, "Unable to set rate: %d", err);
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return err;
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}
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jz4740_timer_set_count(pwm->hwpwm, 0);
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jz4740_timer_set_duty(pwm->hwpwm, duty);
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jz4740_timer_set_period(pwm->hwpwm, period);
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ctrl = JZ_TIMER_CTRL_PRESCALER(prescaler) | JZ_TIMER_CTRL_SRC_EXT |
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JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN;
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jz4740_timer_set_ctrl(pwm->hwpwm, ctrl);
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ctrl = jz4740_timer_get_ctrl(pwm->hwpwm);
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ctrl |= JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN;
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switch (state->polarity) {
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case PWM_POLARITY_NORMAL:
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@ -158,10 +188,6 @@ static int jz4740_pwm_probe(struct platform_device *pdev)
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if (!jz4740)
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return -ENOMEM;
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jz4740->clk = devm_clk_get(&pdev->dev, "ext");
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if (IS_ERR(jz4740->clk))
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return PTR_ERR(jz4740->clk);
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jz4740->chip.dev = &pdev->dev;
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jz4740->chip.ops = &jz4740_pwm_ops;
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jz4740->chip.npwm = NUM_PWM;
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