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arm64: dts: renesas: r8a774b1: Add OPPs table for cpu devices 

This patch adds OPPs table for CA57{0,1} cpu devices.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Link: https://lore.kernel.org/r/1569250648-33857-2-git-send-email-biju.das@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Biju Das 2019-09-23 15:57:25 +01:00 committed by Geert Uytterhoeven
parent 65005e6a5b
commit ce21f29032
1 changed files with 24 additions and 0 deletions
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24
arch/arm64/boot/dts/renesas/r8a774b1.dtsi
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@ -45,6 +45,28 @@ can_clk: can {
clock-frequency = <0>;
};
cluster0_opp: opp_table0 {
compatible = "operating-points-v2";
opp-shared;
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <830000>;
clock-latency-ns = <300000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <830000>;
clock-latency-ns = <300000>;
};
opp-1500000000 {
opp-hz = /bits/ 64 <1500000000>;
opp-microvolt = <830000>;
clock-latency-ns = <300000>;
opp-suspend;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
@ -59,6 +81,7 @@ a57_0: cpu@0 {
#cooling-cells = <2>;
dynamic-power-coefficient = <854>;
clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
};
a57_1: cpu@1 {
@ -69,6 +92,7 @@ a57_1: cpu@1 {
next-level-cache = <&L2_CA57>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
};
L2_CA57: cache-controller-0 {