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drm/amd/pp: Change activity_target for performance optimization on Polaris 

And not support perDPM level optimization on Polaris, so
delete sclk activity_target array.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rex Zhu 2018-01-23 16:28:09 +08:00 committed by Alex Deucher
parent ef4bccbdbf
commit ce91b71c9a
5 changed files with 4 additions and 7 deletions
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2
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_dyn_defaults.h
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@ -50,6 +50,6 @@
#define SMU7_CGULVCONTROL_DFLT 0x00007450 #define SMU7_CGULVCONTROL_DFLT 0x00007450
#define SMU7_TARGETACTIVITY_DFLT 50 #define SMU7_TARGETACTIVITY_DFLT 50
#define SMU7_MCLK_TARGETACTIVITY_DFLT 10 #define SMU7_MCLK_TARGETACTIVITY_DFLT 10
#define SMU7_SCLK_TARGETACTIVITY_DFLT 30
#endif #endif

1
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
View File

@ -1485,6 +1485,7 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
data->dll_default_on = false; data->dll_default_on = false;
data->mclk_dpm0_activity_target = 0xa; data->mclk_dpm0_activity_target = 0xa;
data->mclk_activity_target = SMU7_MCLK_TARGETACTIVITY_DFLT; data->mclk_activity_target = SMU7_MCLK_TARGETACTIVITY_DFLT;
data->sclk_activity_target = SMU7_SCLK_TARGETACTIVITY_DFLT;
data->vddc_vddgfx_delta = 300; data->vddc_vddgfx_delta = 300;
data->static_screen_threshold = SMU7_STATICSCREENTHRESHOLD_DFLT; data->static_screen_threshold = SMU7_STATICSCREENTHRESHOLD_DFLT;
data->static_screen_threshold_unit = SMU7_STATICSCREENTHRESHOLDUNIT_DFLT; data->static_screen_threshold_unit = SMU7_STATICSCREENTHRESHOLDUNIT_DFLT;

1
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
View File

@ -290,6 +290,7 @@ struct smu7_hwmgr {
bool use_pcie_performance_levels; bool use_pcie_performance_levels;
bool use_pcie_power_saving_levels; bool use_pcie_power_saving_levels;
uint32_t mclk_activity_target; uint32_t mclk_activity_target;
uint16_t sclk_activity_target;
uint32_t mclk_dpm0_activity_target; uint32_t mclk_dpm0_activity_target;
uint32_t low_sclk_interrupt_threshold; uint32_t low_sclk_interrupt_threshold;
uint32_t last_mclk_dpm_enable_mask; uint32_t last_mclk_dpm_enable_mask;

6
drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
View File

@ -366,7 +366,6 @@ static bool polaris10_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
static int polaris10_smu_init(struct pp_hwmgr *hwmgr) static int polaris10_smu_init(struct pp_hwmgr *hwmgr)
{ {
struct polaris10_smumgr *smu_data; struct polaris10_smumgr *smu_data;
int i;
smu_data = kzalloc(sizeof(struct polaris10_smumgr), GFP_KERNEL); smu_data = kzalloc(sizeof(struct polaris10_smumgr), GFP_KERNEL);
if (smu_data == NULL) if (smu_data == NULL)
@ -377,9 +376,6 @@ static int polaris10_smu_init(struct pp_hwmgr *hwmgr)
if (smu7_init(hwmgr)) if (smu7_init(hwmgr))
return -EINVAL; return -EINVAL;
for (i = 0; i < SMU74_MAX_LEVELS_GRAPHICS; i++)
smu_data->activity_target[i] = PPPOLARIS10_TARGETACTIVITY_DFLT;
return 0; return 0;
} }
@ -1037,7 +1033,7 @@ static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
result = polaris10_populate_single_graphic_level(hwmgr, result = polaris10_populate_single_graphic_level(hwmgr,
dpm_table->sclk_table.dpm_levels[i].value, dpm_table->sclk_table.dpm_levels[i].value,
(uint16_t)smu_data->activity_target[i], hw_data->sclk_activity_target,
&(smu_data->smc_state_table.GraphicsLevel[i])); &(smu_data->smc_state_table.GraphicsLevel[i]));
if (result) if (result)
return result; return result;

1
drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.h
View File

@ -59,7 +59,6 @@ struct polaris10_smumgr {
struct SMU74_Discrete_PmFuses power_tune_table; struct SMU74_Discrete_PmFuses power_tune_table;
struct polaris10_range_table range_table[NUM_SCLK_RANGE]; struct polaris10_range_table range_table[NUM_SCLK_RANGE];
const struct polaris10_pt_defaults *power_tune_defaults; const struct polaris10_pt_defaults *power_tune_defaults;
uint32_t activity_target[SMU74_MAX_LEVELS_GRAPHICS];
uint32_t bif_sclk_table[SMU74_MAX_LEVELS_LINK]; uint32_t bif_sclk_table[SMU74_MAX_LEVELS_LINK];
}; };