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drm/i915: ValleyView watermark support 

Add support for ValleyView watermark handling.

v2: remove unused reg & bit definitions (Ben)

Acked-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Jesse Barnes 2012-03-28 13:39:22 -07:00 committed by Daniel Vetter
parent 70a3eb7a3e
commit ceb0424687
2 changed files with 71 additions and 0 deletions
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6
drivers/gpu/drm/i915/i915_reg.h
View File

@ -1043,6 +1043,9 @@
#define RAMCLK_GATE_D 0x6210 /* CRL only */ #define RAMCLK_GATE_D 0x6210 /* CRL only */
#define DEUC 0x6214 /* CRL only */ #define DEUC 0x6214 /* CRL only */
#define FW_BLC_SELF_VLV 0x6500
#define FW_CSPWRDWNEN (1<<15)
/* /*
* Palette regs * Palette regs
*/ */
@ -2495,6 +2498,7 @@
#define I915_FIFO_LINE_SIZE 64 #define I915_FIFO_LINE_SIZE 64
#define I830_FIFO_LINE_SIZE 32 #define I830_FIFO_LINE_SIZE 32
#define VALLEYVIEW_FIFO_SIZE 255
#define G4X_FIFO_SIZE 127 #define G4X_FIFO_SIZE 127
#define I965_FIFO_SIZE 512 #define I965_FIFO_SIZE 512
#define I945_FIFO_SIZE 127 #define I945_FIFO_SIZE 127
@ -2502,6 +2506,7 @@
#define I855GM_FIFO_SIZE 127 /* In cachelines */ #define I855GM_FIFO_SIZE 127 /* In cachelines */
#define I830_FIFO_SIZE 95 #define I830_FIFO_SIZE 95
#define VALLEYVIEW_MAX_WM 0xff
#define G4X_MAX_WM 0x3f #define G4X_MAX_WM 0x3f
#define I915_MAX_WM 0x3f #define I915_MAX_WM 0x3f
@ -2516,6 +2521,7 @@
#define PINEVIEW_CURSOR_DFT_WM 0 #define PINEVIEW_CURSOR_DFT_WM 0
#define PINEVIEW_CURSOR_GUARD_WM 5 #define PINEVIEW_CURSOR_GUARD_WM 5
#define VALLEYVIEW_CURSOR_MAX_WM 64
#define I965_CURSOR_FIFO 64 #define I965_CURSOR_FIFO 64
#define I965_CURSOR_MAX_WM 32 #define I965_CURSOR_MAX_WM 32
#define I965_CURSOR_DFT_WM 8 #define I965_CURSOR_DFT_WM 8

65
drivers/gpu/drm/i915/intel_display.c
View File

@ -3636,6 +3636,20 @@ static const struct intel_watermark_params g4x_cursor_wm_info = {
2, 2,
G4X_FIFO_LINE_SIZE, G4X_FIFO_LINE_SIZE,
}; };
static const struct intel_watermark_params valleyview_wm_info = {
VALLEYVIEW_FIFO_SIZE,
VALLEYVIEW_MAX_WM,
VALLEYVIEW_MAX_WM,
2,
G4X_FIFO_LINE_SIZE,
};
static const struct intel_watermark_params valleyview_cursor_wm_info = {
I965_CURSOR_FIFO,
VALLEYVIEW_CURSOR_MAX_WM,
I965_CURSOR_DFT_WM,
2,
G4X_FIFO_LINE_SIZE,
};
static const struct intel_watermark_params i965_cursor_wm_info = { static const struct intel_watermark_params i965_cursor_wm_info = {
I965_CURSOR_FIFO, I965_CURSOR_FIFO,
I965_CURSOR_MAX_WM, I965_CURSOR_MAX_WM,
@ -4160,6 +4174,55 @@ static bool g4x_compute_srwm(struct drm_device *dev,
#define single_plane_enabled(mask) is_power_of_2(mask) #define single_plane_enabled(mask) is_power_of_2(mask)
static void valleyview_update_wm(struct drm_device *dev)
{
static const int sr_latency_ns = 12000;
struct drm_i915_private *dev_priv = dev->dev_private;
int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
int plane_sr, cursor_sr;
unsigned int enabled = 0;
if (g4x_compute_wm0(dev, 0,
&valleyview_wm_info, latency_ns,
&valleyview_cursor_wm_info, latency_ns,
&planea_wm, &cursora_wm))
enabled |= 1;
if (g4x_compute_wm0(dev, 1,
&valleyview_wm_info, latency_ns,
&valleyview_cursor_wm_info, latency_ns,
&planeb_wm, &cursorb_wm))
enabled |= 2;
plane_sr = cursor_sr = 0;
if (single_plane_enabled(enabled) &&
g4x_compute_srwm(dev, ffs(enabled) - 1,
sr_latency_ns,
&valleyview_wm_info,
&valleyview_cursor_wm_info,
&plane_sr, &cursor_sr))
I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
else
I915_WRITE(FW_BLC_SELF_VLV,
I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
planea_wm, cursora_wm,
planeb_wm, cursorb_wm,
plane_sr, cursor_sr);
I915_WRITE(DSPFW1,
(plane_sr << DSPFW_SR_SHIFT) |
(cursorb_wm << DSPFW_CURSORB_SHIFT) |
(planeb_wm << DSPFW_PLANEB_SHIFT) |
planea_wm);
I915_WRITE(DSPFW2,
(I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
(cursora_wm << DSPFW_CURSORA_SHIFT));
I915_WRITE(DSPFW3,
(I915_READ(DSPFW3) | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)));
}
static void g4x_update_wm(struct drm_device *dev) static void g4x_update_wm(struct drm_device *dev)
{ {
static const int sr_latency_ns = 12000; static const int sr_latency_ns = 12000;
@ -9019,6 +9082,8 @@ static void intel_init_display(struct drm_device *dev)
dev_priv->display.write_eld = ironlake_write_eld; dev_priv->display.write_eld = ironlake_write_eld;
} else } else
dev_priv->display.update_wm = NULL; dev_priv->display.update_wm = NULL;
} else if (IS_VALLEYVIEW(dev)) {
dev_priv->display.update_wm = valleyview_update_wm;
} else if (IS_PINEVIEW(dev)) { } else if (IS_PINEVIEW(dev)) {
if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
dev_priv->is_ddr3, dev_priv->is_ddr3,