mirror of https://gitee.com/openkylin/linux.git
clk: ti: divider: Add the table parsing to get the best divider value
Currently the divider selection logic blindly divides the parent_rate by the clk rate and gives the divider value for the divider clocks which do not have the CLK_SET_RATE_PARENT flag set. Add the clk divider table parsing to get the closest divider available in the table provided via Device tree. The code is pretty much taken from: drivers/clk/clk-divider.c. and used here to fix up the best divider selection logic. Signed-off-by: Keerthy <j-keerthy@ti.com> Reported-by: Richard Woodruff <r-woodruff2@ti.com> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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@ -140,6 +140,35 @@ static bool _is_valid_div(struct clk_divider *divider, unsigned int div)
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return true;
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}
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static int _div_round_up(const struct clk_div_table *table,
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unsigned long parent_rate, unsigned long rate)
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{
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const struct clk_div_table *clkt;
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int up = INT_MAX;
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int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
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for (clkt = table; clkt->div; clkt++) {
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if (clkt->div == div)
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return clkt->div;
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else if (clkt->div < div)
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continue;
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if ((clkt->div - div) < (up - div))
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up = clkt->div;
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}
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return up;
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}
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static int _div_round(const struct clk_div_table *table,
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unsigned long parent_rate, unsigned long rate)
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{
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if (!table)
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return DIV_ROUND_UP(parent_rate, rate);
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return _div_round_up(table, parent_rate, rate);
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}
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static int ti_clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
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unsigned long *best_parent_rate)
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{
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@ -155,7 +184,7 @@ static int ti_clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
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if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
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parent_rate = *best_parent_rate;
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bestdiv = DIV_ROUND_UP(parent_rate, rate);
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bestdiv = _div_round(divider->table, parent_rate, rate);
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bestdiv = bestdiv == 0 ? 1 : bestdiv;
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bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
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return bestdiv;
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