mirror of https://gitee.com/openkylin/linux.git
The biggest change is fixing the jitter on the fractional clock-type
Rockchip socs experience with the default approximation. For that we introduce the ability to override it with a clock-specific approximation and use that to create the needed rate settings as described in the Rockchip soc manuals (same for all Rockchip socs). Apart from that we have support for the rk3126 clock controller which is similar to the rk3128 with some minimal differences and a lot of improvements and fixes for the rv1108 clock controller (missing clocks, some clock-ids, naming fixes, register fixes). -----BEGIN PGP SIGNATURE----- iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAlmcl8sQHGhlaWtvQHNu dGVjaC5kZQAKCRDzpnnJnNEdgeiBB/wIf5LHDu09HuOb1bjtYASMc//ve2ymhpd7 QsccJ0nteJTWnYQlrJUPYN8YhRVqPNrz7Fq8PkMMkzm89fQQ6lr5DxOy6olKTPM4 sGf+242eE3XttHjJxcshNPS98A56zBa9OgNC9sUsTex8r7NaJn+Gvlf0sXEgQRQi 5FprJf49/4rlHZypVMg1j+aMEWM8ZAmXLP3F77Qch+rfxE74POV9/HI7EEoSQ9MX TxwEewmM8IGXY9aVTvtADPmX31CgdOD3qm4giwGkBf2F8SajP8R63wi+BYpNfUTX +TrexLXEfeKEVtU+xPXsNYmEnAOW6sRvfyUnq4oA1hVSnFoexFA1 =Upwy -----END PGP SIGNATURE----- Merge tag 'v4.14-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull Rockchip clk driver updates from Heiko Stuebner: The biggest change is fixing the jitter on the fractional clock-type Rockchip socs experience with the default approximation. For that we introduce the ability to override it with a clock-specific approximation and use that to create the needed rate settings as described in the Rockchip soc manuals (same for all Rockchip socs). Apart from that we have support for the rk3126 clock controller which is similar to the rk3128 with some minimal differences and a lot of improvements and fixes for the rv1108 clock controller (missing clocks, some clock-ids, naming fixes, register fixes). * tag 'v4.14-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: fix the rv1108 clk_mac sel register description clk: rockchip: rename rv1108 macphy clock to mac clk: rockchip: add rv1108 ACLK_GMAC and PCLK_GMAC clocks clk: rockchip: add rk3228 SCLK_SDIO_SRC clk id clk: rockchip: add rv1108 ACLK_GAMC and PCLK_GMAC ID clk: rockchip: add rk3228 sclk_sdio_src ID clk: rockchip: add special approximation to fix up fractional clk's jitter clk: fractional-divider: allow overriding of approximation clk: rockchip: modify rk3128 clk driver to also support rk3126 dt-bindings: add documentation for rk3126 clock clk: rockchip: add some critical clocks for rv1108 SoC clk: rockchip: rename some of clks for rv1108 SoC clk: rockchip: fix up some clks describe error for rv1108 SoC clk: rockchip: support more clks for rv1108 clk: rockchip: fix up the pll clks error for rv1108 SoC clk: rockchip: support more rates for rv1108 cpuclk clk: rockchip: fix up indentation of some RV1108 clock-ids clk: rockchip: rename the clk id for HCLK_I2S1_2CH clk: rockchip: add more clk ids for rv1108
This commit is contained in:
Stephen Boyd
commit
cf657bb940
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@ -1,12 +1,14 @@
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* Rockchip RK3128 Clock and Reset Unit
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* Rockchip RK3126/RK3128 Clock and Reset Unit
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The RK3128 clock controller generates and supplies clock to various
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The RK3126/RK3128 clock controller generates and supplies clock to various
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controllers within the SoC and also implements a reset controller for SoC
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peripherals.
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Required Properties:
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- compatible: should be "rockchip,rk3128-cru"
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- compatible: should be "rockchip,rk3126-cru" or "rockchip,rk3128-cru"
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"rockchip,rk3126-cru" - controller compatible with RK3126 SoC.
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"rockchip,rk3128-cru" - controller compatible with RK3128 SoC.
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- reg: physical base address of the controller and length of memory mapped
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region.
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- #clock-cells: should be 1.
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@ -49,16 +49,12 @@ static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,
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return ret;
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}
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static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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static void clk_fd_general_approximation(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate,
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unsigned long *m, unsigned long *n)
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{
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struct clk_fractional_divider *fd = to_clk_fd(hw);
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unsigned long scale;
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unsigned long m, n;
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u64 ret;
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if (!rate || rate >= *parent_rate)
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return *parent_rate;
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/*
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* Get rate closer to *parent_rate to guarantee there is no overflow
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@ -71,7 +67,23 @@ static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate,
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rational_best_approximation(rate, *parent_rate,
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GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
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&m, &n);
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m, n);
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}
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static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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struct clk_fractional_divider *fd = to_clk_fd(hw);
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unsigned long m, n;
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u64 ret;
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if (!rate || rate >= *parent_rate)
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return *parent_rate;
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if (fd->approximation)
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fd->approximation(hw, rate, parent_rate, &m, &n);
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else
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clk_fd_general_approximation(hw, rate, parent_rate, &m, &n);
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ret = (u64)*parent_rate * m;
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do_div(ret, n);
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@ -201,7 +201,7 @@ static struct rockchip_clk_branch rk3128_uart2_fracmux __initdata =
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MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
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RK2928_CLKSEL_CON(15), 8, 2, MFLAGS);
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static struct rockchip_clk_branch rk3128_clk_branches[] __initdata = {
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static struct rockchip_clk_branch common_clk_branches[] __initdata = {
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/*
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* Clock-Architecture Diagram 1
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*/
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@ -459,10 +459,6 @@ static struct rockchip_clk_branch rk3128_clk_branches[] __initdata = {
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RK2928_CLKSEL_CON(2), 14, 2, MFLAGS, 8, 5, DFLAGS,
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RK2928_CLKGATE_CON(10), 15, GFLAGS),
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COMPOSITE(SCLK_SFC, "sclk_sfc", mux_sclk_sfc_src_p, 0,
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RK2928_CLKSEL_CON(11), 14, 2, MFLAGS, 8, 5, DFLAGS,
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RK2928_CLKGATE_CON(3), 15, GFLAGS),
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COMPOSITE_NOMUX(PCLK_PMU_PRE, "pclk_pmu_pre", "cpll", 0,
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RK2928_CLKSEL_CON(29), 8, 6, DFLAGS,
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RK2928_CLKGATE_CON(1), 0, GFLAGS),
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@ -495,7 +491,6 @@ static struct rockchip_clk_branch rk3128_clk_branches[] __initdata = {
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GATE(ACLK_DMAC, "aclk_dmac", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 1, GFLAGS),
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GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 15, GFLAGS),
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GATE(0, "aclk_cpu_to_peri", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 2, GFLAGS),
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GATE(HCLK_GPS, "hclk_gps", "aclk_peri", 0, RK2928_CLKGATE_CON(3), 14, GFLAGS),
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GATE(HCLK_I2S_8CH, "hclk_i2s_8ch", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS),
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GATE(0, "hclk_peri_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 0, GFLAGS),
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@ -541,7 +536,6 @@ static struct rockchip_clk_branch rk3128_clk_branches[] __initdata = {
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GATE(0, "hclk_rom", "hclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 6, GFLAGS),
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GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_cpu", 0, RK2928_CLKGATE_CON(3), 5, GFLAGS),
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GATE(PCLK_HDMI, "pclk_hdmi", "pclk_cpu", 0, RK2928_CLKGATE_CON(3), 8, GFLAGS),
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GATE(PCLK_ACODEC, "pclk_acodec", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 14, GFLAGS),
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GATE(0, "pclk_ddrupctl", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 7, GFLAGS),
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GATE(0, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS),
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@ -561,6 +555,21 @@ static struct rockchip_clk_branch rk3128_clk_branches[] __initdata = {
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MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3228_EMMC_CON1, 0),
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};
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static struct rockchip_clk_branch rk3126_clk_branches[] __initdata = {
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GATE(0, "pclk_stimer", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 15, GFLAGS),
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GATE(0, "pclk_s_efuse", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 14, GFLAGS),
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GATE(0, "pclk_sgrf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 8, GFLAGS),
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};
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static struct rockchip_clk_branch rk3128_clk_branches[] __initdata = {
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COMPOSITE(SCLK_SFC, "sclk_sfc", mux_sclk_sfc_src_p, 0,
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RK2928_CLKSEL_CON(11), 14, 2, MFLAGS, 8, 5, DFLAGS,
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RK2928_CLKGATE_CON(3), 15, GFLAGS),
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GATE(HCLK_GPS, "hclk_gps", "aclk_peri", 0, RK2928_CLKGATE_CON(3), 14, GFLAGS),
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GATE(PCLK_HDMI, "pclk_hdmi", "pclk_cpu", 0, RK2928_CLKGATE_CON(3), 8, GFLAGS),
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};
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static const char *const rk3128_critical_clocks[] __initconst = {
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"aclk_cpu",
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"hclk_cpu",
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@ -570,7 +579,7 @@ static const char *const rk3128_critical_clocks[] __initconst = {
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"pclk_peri",
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};
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static void __init rk3128_clk_init(struct device_node *np)
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static struct rockchip_clk_provider *__init rk3128_common_clk_init(struct device_node *np)
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{
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struct rockchip_clk_provider *ctx;
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void __iomem *reg_base;
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@ -578,23 +587,21 @@ static void __init rk3128_clk_init(struct device_node *np)
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reg_base = of_iomap(np, 0);
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if (!reg_base) {
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pr_err("%s: could not map cru region\n", __func__);
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return;
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return ERR_PTR(-ENOMEM);
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}
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ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
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if (IS_ERR(ctx)) {
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pr_err("%s: rockchip clk init failed\n", __func__);
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iounmap(reg_base);
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return;
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return ERR_PTR(-ENOMEM);
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}
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rockchip_clk_register_plls(ctx, rk3128_pll_clks,
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ARRAY_SIZE(rk3128_pll_clks),
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RK3128_GRF_SOC_STATUS0);
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rockchip_clk_register_branches(ctx, rk3128_clk_branches,
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ARRAY_SIZE(rk3128_clk_branches));
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rockchip_clk_protect_critical(rk3128_critical_clocks,
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ARRAY_SIZE(rk3128_critical_clocks));
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rockchip_clk_register_branches(ctx, common_clk_branches,
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ARRAY_SIZE(common_clk_branches));
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rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
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mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
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@ -606,6 +613,40 @@ static void __init rk3128_clk_init(struct device_node *np)
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rockchip_register_restart_notifier(ctx, RK2928_GLB_SRST_FST, NULL);
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return ctx;
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}
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static void __init rk3126_clk_init(struct device_node *np)
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{
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struct rockchip_clk_provider *ctx;
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ctx = rk3128_common_clk_init(np);
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if (IS_ERR(ctx))
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return;
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rockchip_clk_register_branches(ctx, rk3126_clk_branches,
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ARRAY_SIZE(rk3126_clk_branches));
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rockchip_clk_protect_critical(rk3128_critical_clocks,
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ARRAY_SIZE(rk3128_critical_clocks));
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rockchip_clk_of_add_provider(np, ctx);
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}
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CLK_OF_DECLARE(rk3126_cru, "rockchip,rk3126-cru", rk3126_clk_init);
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static void __init rk3128_clk_init(struct device_node *np)
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{
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struct rockchip_clk_provider *ctx;
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ctx = rk3128_common_clk_init(np);
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if (IS_ERR(ctx))
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return;
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rockchip_clk_register_branches(ctx, rk3128_clk_branches,
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ARRAY_SIZE(rk3128_clk_branches));
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rockchip_clk_protect_critical(rk3128_critical_clocks,
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ARRAY_SIZE(rk3128_critical_clocks));
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rockchip_clk_of_add_provider(np, ctx);
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}
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@ -391,7 +391,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
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RK2928_CLKSEL_CON(11), 8, 2, MFLAGS, 0, 8, DFLAGS,
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RK2928_CLKGATE_CON(2), 11, GFLAGS),
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COMPOSITE_NODIV(0, "sclk_sdio_src", mux_mmc_src_p, 0,
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COMPOSITE_NODIV(SCLK_SDIO_SRC, "sclk_sdio_src", mux_mmc_src_p, 0,
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RK2928_CLKSEL_CON(11), 10, 2, MFLAGS,
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RK2928_CLKGATE_CON(2), 13, GFLAGS),
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DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0,
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@ -93,9 +93,24 @@ static struct rockchip_pll_rate_table rv1108_pll_rates[] = {
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}
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static struct rockchip_cpuclk_rate_table rv1108_cpuclk_rates[] __initdata = {
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RV1108_CPUCLK_RATE(816000000, 4),
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RV1108_CPUCLK_RATE(600000000, 4),
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RV1108_CPUCLK_RATE(312000000, 4),
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RV1108_CPUCLK_RATE(1608000000, 7),
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RV1108_CPUCLK_RATE(1512000000, 7),
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RV1108_CPUCLK_RATE(1488000000, 5),
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RV1108_CPUCLK_RATE(1416000000, 5),
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RV1108_CPUCLK_RATE(1392000000, 5),
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RV1108_CPUCLK_RATE(1296000000, 5),
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RV1108_CPUCLK_RATE(1200000000, 5),
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RV1108_CPUCLK_RATE(1104000000, 5),
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RV1108_CPUCLK_RATE(1008000000, 5),
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RV1108_CPUCLK_RATE(912000000, 5),
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RV1108_CPUCLK_RATE(816000000, 3),
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RV1108_CPUCLK_RATE(696000000, 3),
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RV1108_CPUCLK_RATE(600000000, 3),
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RV1108_CPUCLK_RATE(500000000, 3),
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RV1108_CPUCLK_RATE(408000000, 1),
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RV1108_CPUCLK_RATE(312000000, 1),
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RV1108_CPUCLK_RATE(216000000, 1),
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RV1108_CPUCLK_RATE(96000000, 1),
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};
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static const struct rockchip_cpuclk_reg_data rv1108_cpuclk_data = {
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@ -105,7 +120,7 @@ static const struct rockchip_cpuclk_reg_data rv1108_cpuclk_data = {
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.mux_core_alt = 1,
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.mux_core_main = 0,
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.mux_core_shift = 8,
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.mux_core_mask = 0x1,
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.mux_core_mask = 0x3,
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};
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PNAME(mux_pll_p) = { "xin24m", "xin24m"};
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@ -114,30 +129,42 @@ PNAME(mux_armclk_p) = { "apll_core", "gpll_core", "dpll_core" };
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PNAME(mux_usb480m_pre_p) = { "usbphy", "xin24m" };
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PNAME(mux_hdmiphy_phy_p) = { "hdmiphy", "xin24m" };
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PNAME(mux_dclk_hdmiphy_pre_p) = { "dclk_hdmiphy_src_gpll", "dclk_hdmiphy_src_dpll" };
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PNAME(mux_pll_src_4plls_p) = { "dpll", "hdmiphy", "gpll", "usb480m" };
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PNAME(mux_pll_src_4plls_p) = { "dpll", "gpll", "hdmiphy", "usb480m" };
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PNAME(mux_pll_src_3plls_p) = { "apll", "gpll", "dpll" };
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PNAME(mux_pll_src_2plls_p) = { "dpll", "gpll" };
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PNAME(mux_pll_src_apll_gpll_p) = { "apll", "gpll" };
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PNAME(mux_aclk_peri_src_p) = { "aclk_peri_src_dpll", "aclk_peri_src_gpll" };
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PNAME(mux_aclk_peri_src_p) = { "aclk_peri_src_gpll", "aclk_peri_src_dpll" };
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PNAME(mux_aclk_bus_src_p) = { "aclk_bus_src_gpll", "aclk_bus_src_apll", "aclk_bus_src_dpll" };
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PNAME(mux_mmc_src_p) = { "dpll", "gpll", "xin24m", "usb480m" };
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PNAME(mux_pll_src_dpll_gpll_usb480m_p) = { "dpll", "gpll", "usb480m" };
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PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" };
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PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };
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PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" };
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PNAME(mux_sclk_macphy_p) = { "sclk_macphy_pre", "ext_gmac" };
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PNAME(mux_sclk_mac_p) = { "sclk_mac_pre", "ext_gmac" };
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PNAME(mux_i2s0_pre_p) = { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" };
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PNAME(mux_i2s_out_p) = { "i2s0_pre", "xin12m" };
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PNAME(mux_i2s1_p) = { "i2s1_src", "i2s1_frac", "xin12m" };
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PNAME(mux_i2s2_p) = { "i2s2_src", "i2s2_frac", "xin12m" };
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PNAME(mux_i2s1_p) = { "i2s1_src", "i2s1_frac", "dummy", "xin12m" };
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PNAME(mux_i2s2_p) = { "i2s2_src", "i2s2_frac", "dummy", "xin12m" };
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PNAME(mux_wifi_src_p) = { "gpll", "xin24m" };
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PNAME(mux_cifout_src_p) = { "hdmiphy", "gpll" };
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PNAME(mux_cifout_p) = { "sclk_cifout_src", "xin24m" };
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PNAME(mux_sclk_cif0_src_p) = { "pclk_vip", "clk_cif0_chn_out", "pclkin_cvbs2cif" };
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PNAME(mux_sclk_cif1_src_p) = { "pclk_vip", "clk_cif1_chn_out", "pclkin_cvbs2cif" };
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||||
PNAME(mux_sclk_cif2_src_p) = { "pclk_vip", "clk_cif2_chn_out", "pclkin_cvbs2cif" };
|
||||
PNAME(mux_sclk_cif3_src_p) = { "pclk_vip", "clk_cif3_chn_out", "pclkin_cvbs2cif" };
|
||||
PNAME(mux_dsp_src_p) = { "dpll", "gpll", "apll", "usb480m" };
|
||||
PNAME(mux_dclk_hdmiphy_p) = { "hdmiphy", "xin24m" };
|
||||
PNAME(mux_dclk_vop_p) = { "dclk_hdmiphy", "dclk_vop_src" };
|
||||
PNAME(mux_hdmi_cec_src_p) = { "dpll", "gpll", "xin24m" };
|
||||
PNAME(mux_cvbs_src_p) = { "apll", "io_cvbs_clkin", "hdmiphy", "gpll" };
|
||||
|
||||
static struct rockchip_pll_clock rv1108_pll_clks[] __initdata = {
|
||||
[apll] = PLL(pll_rk3399, PLL_APLL, "apll", mux_pll_p, 0, RV1108_PLL_CON(0),
|
||||
RV1108_PLL_CON(3), 8, 31, 0, rv1108_pll_rates),
|
||||
RV1108_PLL_CON(3), 8, 0, 0, rv1108_pll_rates),
|
||||
[dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RV1108_PLL_CON(8),
|
||||
RV1108_PLL_CON(11), 8, 31, 0, NULL),
|
||||
RV1108_PLL_CON(11), 8, 1, 0, NULL),
|
||||
[gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RV1108_PLL_CON(16),
|
||||
RV1108_PLL_CON(19), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rv1108_pll_rates),
|
||||
RV1108_PLL_CON(19), 8, 2, 0, rv1108_pll_rates),
|
||||
};
|
||||
|
||||
#define MFLAGS CLK_MUX_HIWORD_MASK
|
||||
|
|
@ -170,10 +197,10 @@ static struct rockchip_clk_branch rv1108_i2s2_fracmux __initdata =
|
|||
RV1108_CLKSEL_CON(7), 12, 2, MFLAGS);
|
||||
|
||||
static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = {
|
||||
MUX(0, "hdmi_phy", mux_hdmiphy_phy_p, CLK_SET_RATE_PARENT,
|
||||
RV1108_MISC_CON, 13, 2, MFLAGS),
|
||||
MUX(0, "hdmiphy", mux_hdmiphy_phy_p, CLK_SET_RATE_PARENT,
|
||||
RV1108_MISC_CON, 13, 1, MFLAGS),
|
||||
MUX(0, "usb480m", mux_usb480m_pre_p, CLK_SET_RATE_PARENT,
|
||||
RV1108_MISC_CON, 15, 2, MFLAGS),
|
||||
RV1108_MISC_CON, 15, 1, MFLAGS),
|
||||
/*
|
||||
* Clock-Architecture Diagram 2
|
||||
*/
|
||||
|
|
@ -197,50 +224,212 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = {
|
|||
RV1108_CLKGATE_CON(11), 1, GFLAGS),
|
||||
|
||||
/* PD_RKVENC */
|
||||
COMPOSITE(0, "aclk_rkvenc_pre", mux_pll_src_4plls_p, 0,
|
||||
RV1108_CLKSEL_CON(37), 6, 2, MFLAGS, 0, 5, DFLAGS,
|
||||
RV1108_CLKGATE_CON(8), 8, GFLAGS),
|
||||
FACTOR_GATE(0, "hclk_rkvenc_pre", "aclk_rkvenc_pre", 0, 1, 4,
|
||||
RV1108_CLKGATE_CON(8), 10, GFLAGS),
|
||||
COMPOSITE(SCLK_VENC_CORE, "clk_venc_core", mux_pll_src_4plls_p, 0,
|
||||
RV1108_CLKSEL_CON(37), 14, 2, MFLAGS, 8, 5, DFLAGS,
|
||||
RV1108_CLKGATE_CON(8), 9, GFLAGS),
|
||||
GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_pre", 0,
|
||||
RV1108_CLKGATE_CON(19), 8, GFLAGS),
|
||||
GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_rkvenc_pre", 0,
|
||||
RV1108_CLKGATE_CON(19), 9, GFLAGS),
|
||||
GATE(0, "aclk_rkvenc_niu", "aclk_rkvenc_pre", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(19), 11, GFLAGS),
|
||||
GATE(0, "hclk_rkvenc_niu", "hclk_rkvenc_pre", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(19), 10, GFLAGS),
|
||||
|
||||
/* PD_RKVDEC */
|
||||
COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core", mux_pll_src_4plls_p, 0,
|
||||
RV1108_CLKSEL_CON(36), 6, 2, MFLAGS, 0, 5, DFLAGS,
|
||||
RV1108_CLKGATE_CON(8), 2, GFLAGS),
|
||||
FACTOR_GATE(0, "hclk_rkvdec_pre", "sclk_hevc_core", 0, 1, 4,
|
||||
RV1108_CLKGATE_CON(8), 10, GFLAGS),
|
||||
COMPOSITE(SCLK_HEVC_CABAC, "clk_hevc_cabac", mux_pll_src_4plls_p, 0,
|
||||
RV1108_CLKSEL_CON(35), 14, 2, MFLAGS, 8, 5, DFLAGS,
|
||||
RV1108_CLKGATE_CON(8), 1, GFLAGS),
|
||||
|
||||
COMPOSITE(0, "aclk_rkvdec_pre", mux_pll_src_4plls_p, 0,
|
||||
RV1108_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS,
|
||||
RV1108_CLKGATE_CON(8), 0, GFLAGS),
|
||||
COMPOSITE(0, "aclk_vpu_pre", mux_pll_src_4plls_p, 0,
|
||||
RV1108_CLKSEL_CON(36), 14, 2, MFLAGS, 8, 5, DFLAGS,
|
||||
RV1108_CLKGATE_CON(8), 3, GFLAGS),
|
||||
GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 0,
|
||||
RV1108_CLKGATE_CON(19), 0, GFLAGS),
|
||||
GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0,
|
||||
RV1108_CLKGATE_CON(19), 1, GFLAGS),
|
||||
GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 0,
|
||||
RV1108_CLKGATE_CON(19), 2, GFLAGS),
|
||||
GATE(HCLK_VPU, "hclk_vpu", "hclk_rkvdec_pre", 0,
|
||||
RV1108_CLKGATE_CON(19), 3, GFLAGS),
|
||||
GATE(0, "aclk_rkvdec_niu", "aclk_rkvdec_pre", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(19), 4, GFLAGS),
|
||||
GATE(0, "hclk_rkvdec_niu", "hclk_rkvdec_pre", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(19), 5, GFLAGS),
|
||||
GATE(0, "aclk_vpu_niu", "aclk_vpu_pre", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(19), 6, GFLAGS),
|
||||
|
||||
/* PD_PMU_wrapper */
|
||||
COMPOSITE_NOMUX(0, "pmu_24m_ena", "gpll", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKSEL_CON(38), 0, 5, DFLAGS,
|
||||
RV1108_CLKGATE_CON(8), 12, GFLAGS),
|
||||
GATE(0, "pmu", "pmu_24m_ena", CLK_IGNORE_UNUSED,
|
||||
GATE(0, "pclk_pmu", "pmu_24m_ena", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(10), 0, GFLAGS),
|
||||
GATE(0, "intmem1", "pmu_24m_ena", CLK_IGNORE_UNUSED,
|
||||
GATE(0, "pclk_intmem1", "pmu_24m_ena", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(10), 1, GFLAGS),
|
||||
GATE(0, "gpio0_pmu", "pmu_24m_ena", CLK_IGNORE_UNUSED,
|
||||
GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pmu_24m_ena", 0,
|
||||
RV1108_CLKGATE_CON(10), 2, GFLAGS),
|
||||
GATE(0, "pmugrf", "pmu_24m_ena", CLK_IGNORE_UNUSED,
|
||||
GATE(0, "pclk_pmugrf", "pmu_24m_ena", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(10), 3, GFLAGS),
|
||||
GATE(0, "pmu_noc", "pmu_24m_ena", CLK_IGNORE_UNUSED,
|
||||
GATE(0, "pclk_pmu_niu", "pmu_24m_ena", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(10), 4, GFLAGS),
|
||||
GATE(0, "i2c0_pmu_pclk", "pmu_24m_ena", CLK_IGNORE_UNUSED,
|
||||
GATE(PCLK_I2C0_PMU, "pclk_i2c0_pmu", "pmu_24m_ena", 0,
|
||||
RV1108_CLKGATE_CON(10), 5, GFLAGS),
|
||||
GATE(0, "pwm0_pmu_pclk", "pmu_24m_ena", CLK_IGNORE_UNUSED,
|
||||
GATE(PCLK_PWM0_PMU, "pclk_pwm0_pmu", "pmu_24m_ena", 0,
|
||||
RV1108_CLKGATE_CON(10), 6, GFLAGS),
|
||||
COMPOSITE(0, "pwm0_pmu_clk", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED,
|
||||
COMPOSITE(SCLK_PWM0_PMU, "sclk_pwm0_pmu", mux_pll_src_2plls_p, 0,
|
||||
RV1108_CLKSEL_CON(12), 7, 1, MFLAGS, 0, 7, DFLAGS,
|
||||
RV1108_CLKGATE_CON(8), 15, GFLAGS),
|
||||
COMPOSITE(0, "i2c0_pmu_clk", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED,
|
||||
COMPOSITE(SCLK_I2C0_PMU, "sclk_i2c0_pmu", mux_pll_src_2plls_p, 0,
|
||||
RV1108_CLKSEL_CON(19), 7, 1, MFLAGS, 0, 7, DFLAGS,
|
||||
RV1108_CLKGATE_CON(8), 14, GFLAGS),
|
||||
GATE(0, "pvtm_pmu", "xin24m", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(8), 13, GFLAGS),
|
||||
|
||||
/*
|
||||
* Clock-Architecture Diagram 3
|
||||
*/
|
||||
COMPOSITE(SCLK_WIFI, "sclk_wifi", mux_wifi_src_p, 0,
|
||||
RV1108_CLKSEL_CON(28), 15, 1, MFLAGS, 8, 6, DFLAGS,
|
||||
RV1108_CLKGATE_CON(9), 8, GFLAGS),
|
||||
COMPOSITE_NODIV(0, "sclk_cifout_src", mux_cifout_src_p, 0,
|
||||
RV1108_CLKSEL_CON(40), 8, 1, MFLAGS,
|
||||
RV1108_CLKGATE_CON(9), 11, GFLAGS),
|
||||
COMPOSITE_NOGATE(SCLK_CIFOUT, "sclk_cifout", mux_cifout_p, 0,
|
||||
RV1108_CLKSEL_CON(40), 12, 1, MFLAGS, 0, 5, DFLAGS),
|
||||
COMPOSITE_NOMUX(SCLK_MIPI_CSI_OUT, "sclk_mipi_csi_out", "xin24m", 0,
|
||||
RV1108_CLKSEL_CON(41), 0, 5, DFLAGS,
|
||||
RV1108_CLKGATE_CON(9), 12, GFLAGS),
|
||||
|
||||
GATE(0, "pclk_acodecphy", "pclk_top_pre", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(14), 6, GFLAGS),
|
||||
GATE(0, "pclk_usbgrf", "pclk_top_pre", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(14), 14, GFLAGS),
|
||||
|
||||
GATE(ACLK_CIF0, "aclk_cif0", "aclk_vio1_pre", 0,
|
||||
RV1108_CLKGATE_CON(18), 10, GFLAGS),
|
||||
GATE(HCLK_CIF0, "hclk_cif0", "hclk_vio_pre", 0,
|
||||
RV1108_CLKGATE_CON(18), 10, GFLAGS),
|
||||
COMPOSITE_NODIV(SCLK_CIF0, "sclk_cif0", mux_sclk_cif0_src_p, 0,
|
||||
RV1108_CLKSEL_CON(31), 0, 2, MFLAGS,
|
||||
RV1108_CLKGATE_CON(7), 9, GFLAGS),
|
||||
GATE(ACLK_CIF1, "aclk_cif1", "aclk_vio1_pre", 0,
|
||||
RV1108_CLKGATE_CON(17), 6, GFLAGS),
|
||||
GATE(HCLK_CIF1, "hclk_cif1", "hclk_vio_pre", 0,
|
||||
RV1108_CLKGATE_CON(17), 7, GFLAGS),
|
||||
COMPOSITE_NODIV(SCLK_CIF1, "sclk_cif1", mux_sclk_cif1_src_p, 0,
|
||||
RV1108_CLKSEL_CON(31), 2, 2, MFLAGS,
|
||||
RV1108_CLKGATE_CON(7), 10, GFLAGS),
|
||||
GATE(ACLK_CIF2, "aclk_cif2", "aclk_vio1_pre", 0,
|
||||
RV1108_CLKGATE_CON(17), 8, GFLAGS),
|
||||
GATE(HCLK_CIF2, "hclk_cif2", "hclk_vio_pre", 0,
|
||||
RV1108_CLKGATE_CON(17), 9, GFLAGS),
|
||||
COMPOSITE_NODIV(SCLK_CIF2, "sclk_cif2", mux_sclk_cif2_src_p, 0,
|
||||
RV1108_CLKSEL_CON(31), 4, 2, MFLAGS,
|
||||
RV1108_CLKGATE_CON(7), 11, GFLAGS),
|
||||
GATE(ACLK_CIF3, "aclk_cif3", "aclk_vio1_pre", 0,
|
||||
RV1108_CLKGATE_CON(17), 10, GFLAGS),
|
||||
GATE(HCLK_CIF3, "hclk_cif3", "hclk_vio_pre", 0,
|
||||
RV1108_CLKGATE_CON(17), 11, GFLAGS),
|
||||
COMPOSITE_NODIV(SCLK_CIF3, "sclk_cif3", mux_sclk_cif3_src_p, 0,
|
||||
RV1108_CLKSEL_CON(31), 6, 2, MFLAGS,
|
||||
RV1108_CLKGATE_CON(7), 12, GFLAGS),
|
||||
GATE(0, "pclk_cif1to4", "pclk_vip", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(7), 8, GFLAGS),
|
||||
|
||||
/* PD_DSP_wrapper */
|
||||
COMPOSITE(SCLK_DSP, "sclk_dsp", mux_dsp_src_p, 0,
|
||||
RV1108_CLKSEL_CON(42), 8, 2, MFLAGS, 0, 5, DFLAGS,
|
||||
RV1108_CLKGATE_CON(9), 0, GFLAGS),
|
||||
GATE(0, "clk_dsp_sys_wd", "sclk_dsp", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(16), 0, GFLAGS),
|
||||
GATE(0, "clk_dsp_epp_wd", "sclk_dsp", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(16), 1, GFLAGS),
|
||||
GATE(0, "clk_dsp_edp_wd", "sclk_dsp", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(16), 2, GFLAGS),
|
||||
GATE(0, "clk_dsp_iop_wd", "sclk_dsp", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(16), 3, GFLAGS),
|
||||
GATE(0, "clk_dsp_free", "sclk_dsp", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(16), 13, GFLAGS),
|
||||
COMPOSITE_NOMUX(SCLK_DSP_IOP, "sclk_dsp_iop", "sclk_dsp", 0,
|
||||
RV1108_CLKSEL_CON(44), 0, 5, DFLAGS,
|
||||
RV1108_CLKGATE_CON(9), 1, GFLAGS),
|
||||
COMPOSITE_NOMUX(SCLK_DSP_EPP, "sclk_dsp_epp", "sclk_dsp", 0,
|
||||
RV1108_CLKSEL_CON(44), 8, 5, DFLAGS,
|
||||
RV1108_CLKGATE_CON(9), 2, GFLAGS),
|
||||
COMPOSITE_NOMUX(SCLK_DSP_EDP, "sclk_dsp_edp", "sclk_dsp", 0,
|
||||
RV1108_CLKSEL_CON(45), 0, 5, DFLAGS,
|
||||
RV1108_CLKGATE_CON(9), 3, GFLAGS),
|
||||
COMPOSITE_NOMUX(SCLK_DSP_EDAP, "sclk_dsp_edap", "sclk_dsp", 0,
|
||||
RV1108_CLKSEL_CON(45), 8, 5, DFLAGS,
|
||||
RV1108_CLKGATE_CON(9), 4, GFLAGS),
|
||||
GATE(0, "pclk_dsp_iop_niu", "sclk_dsp_iop", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(16), 4, GFLAGS),
|
||||
GATE(0, "aclk_dsp_epp_niu", "sclk_dsp_epp", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(16), 5, GFLAGS),
|
||||
GATE(0, "aclk_dsp_edp_niu", "sclk_dsp_edp", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(16), 6, GFLAGS),
|
||||
GATE(0, "pclk_dsp_dbg_niu", "sclk_dsp", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(16), 7, GFLAGS),
|
||||
GATE(0, "aclk_dsp_edap_niu", "sclk_dsp_edap", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(16), 14, GFLAGS),
|
||||
COMPOSITE_NOMUX(SCLK_DSP_PFM, "sclk_dsp_pfm", "sclk_dsp", 0,
|
||||
RV1108_CLKSEL_CON(43), 0, 5, DFLAGS,
|
||||
RV1108_CLKGATE_CON(9), 5, GFLAGS),
|
||||
COMPOSITE_NOMUX(PCLK_DSP_CFG, "pclk_dsp_cfg", "sclk_dsp", 0,
|
||||
RV1108_CLKSEL_CON(43), 8, 5, DFLAGS,
|
||||
RV1108_CLKGATE_CON(9), 6, GFLAGS),
|
||||
GATE(0, "pclk_dsp_cfg_niu", "pclk_dsp_cfg", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(16), 8, GFLAGS),
|
||||
GATE(0, "pclk_dsp_pfm_mon", "pclk_dsp_cfg", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(16), 9, GFLAGS),
|
||||
GATE(0, "pclk_intc", "pclk_dsp_cfg", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(16), 10, GFLAGS),
|
||||
GATE(0, "pclk_dsp_grf", "pclk_dsp_cfg", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(16), 11, GFLAGS),
|
||||
GATE(0, "pclk_mailbox", "pclk_dsp_cfg", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(16), 12, GFLAGS),
|
||||
GATE(0, "aclk_dsp_epp_perf", "sclk_dsp_epp", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(16), 15, GFLAGS),
|
||||
GATE(0, "aclk_dsp_edp_perf", "sclk_dsp_edp", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(11), 8, GFLAGS),
|
||||
|
||||
/*
|
||||
* Clock-Architecture Diagram 4
|
||||
*/
|
||||
COMPOSITE(0, "aclk_vio0_2wrap_occ", mux_pll_src_4plls_p, CLK_IGNORE_UNUSED,
|
||||
COMPOSITE(0, "aclk_vio0_pre", mux_pll_src_4plls_p, CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS,
|
||||
RV1108_CLKGATE_CON(6), 0, GFLAGS),
|
||||
GATE(0, "aclk_vio0_pre", "aclk_vio0_2wrap_occ", CLK_IGNORE_UNUSED,
|
||||
GATE(ACLK_VIO0, "aclk_vio0", "aclk_vio0_pre", 0,
|
||||
RV1108_CLKGATE_CON(17), 0, GFLAGS),
|
||||
COMPOSITE_NOMUX(0, "hclk_vio_pre", "aclk_vio0_pre", 0,
|
||||
RV1108_CLKSEL_CON(29), 0, 5, DFLAGS,
|
||||
RV1108_CLKGATE_CON(7), 2, GFLAGS),
|
||||
GATE(HCLK_VIO, "hclk_vio", "hclk_vio_pre", 0,
|
||||
RV1108_CLKGATE_CON(17), 2, GFLAGS),
|
||||
COMPOSITE_NOMUX(0, "pclk_vio_pre", "aclk_vio0_pre", 0,
|
||||
RV1108_CLKSEL_CON(29), 8, 5, DFLAGS,
|
||||
RV1108_CLKGATE_CON(7), 3, GFLAGS),
|
||||
GATE(PCLK_VIO, "pclk_vio", "pclk_vio_pre", 0,
|
||||
RV1108_CLKGATE_CON(17), 3, GFLAGS),
|
||||
COMPOSITE(0, "aclk_vio1_pre", mux_pll_src_4plls_p, CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKSEL_CON(28), 14, 2, MFLAGS, 8, 5, DFLAGS,
|
||||
RV1108_CLKGATE_CON(6), 1, GFLAGS),
|
||||
GATE(ACLK_VIO1, "aclk_vio1", "aclk_vio1_pre", 0,
|
||||
RV1108_CLKGATE_CON(17), 1, GFLAGS),
|
||||
|
||||
INVERTER(0, "pclk_vip", "ext_vip",
|
||||
RV1108_CLKSEL_CON(31), 8, IFLAGS),
|
||||
|
|
@ -252,8 +441,63 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = {
|
|||
RV1108_CLKGATE_CON(6), 5, GFLAGS),
|
||||
GATE(0, "dclk_hdmiphy_src_dpll", "dpll", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(6), 4, GFLAGS),
|
||||
COMPOSITE_NOGATE(0, "dclk_hdmiphy", mux_dclk_hdmiphy_pre_p, 0,
|
||||
RV1108_CLKSEL_CON(32), 6, 2, MFLAGS, 8, 6, DFLAGS),
|
||||
COMPOSITE_NOGATE(0, "dclk_hdmiphy_pre", mux_dclk_hdmiphy_pre_p, 0,
|
||||
RV1108_CLKSEL_CON(32), 6, 1, MFLAGS, 8, 6, DFLAGS),
|
||||
COMPOSITE_NOGATE(DCLK_VOP_SRC, "dclk_vop_src", mux_dclk_hdmiphy_pre_p, 0,
|
||||
RV1108_CLKSEL_CON(32), 6, 1, MFLAGS, 0, 6, DFLAGS),
|
||||
MUX(DCLK_HDMIPHY, "dclk_hdmiphy", mux_dclk_hdmiphy_p, CLK_SET_RATE_PARENT,
|
||||
RV1108_CLKSEL_CON(32), 15, 1, MFLAGS),
|
||||
MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, CLK_SET_RATE_PARENT,
|
||||
RV1108_CLKSEL_CON(32), 7, 1, MFLAGS),
|
||||
GATE(ACLK_VOP, "aclk_vop", "aclk_vio0_pre", 0,
|
||||
RV1108_CLKGATE_CON(18), 0, GFLAGS),
|
||||
GATE(HCLK_VOP, "hclk_vop", "hclk_vio_pre", 0,
|
||||
RV1108_CLKGATE_CON(18), 1, GFLAGS),
|
||||
GATE(ACLK_IEP, "aclk_iep", "aclk_vio0_pre", 0,
|
||||
RV1108_CLKGATE_CON(18), 2, GFLAGS),
|
||||
GATE(HCLK_IEP, "hclk_iep", "hclk_vio_pre", 0,
|
||||
RV1108_CLKGATE_CON(18), 3, GFLAGS),
|
||||
|
||||
GATE(ACLK_RGA, "aclk_rga", "aclk_vio1_pre", 0,
|
||||
RV1108_CLKGATE_CON(18), 4, GFLAGS),
|
||||
GATE(HCLK_RGA, "hclk_rga", "hclk_vio_pre", 0,
|
||||
RV1108_CLKGATE_CON(18), 5, GFLAGS),
|
||||
COMPOSITE(SCLK_RGA, "sclk_rga", mux_pll_src_4plls_p, 0,
|
||||
RV1108_CLKSEL_CON(33), 6, 2, MFLAGS, 0, 5, DFLAGS,
|
||||
RV1108_CLKGATE_CON(6), 6, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_CVBS_HOST, "sclk_cvbs_host", mux_cvbs_src_p, 0,
|
||||
RV1108_CLKSEL_CON(33), 13, 2, MFLAGS, 8, 5, DFLAGS,
|
||||
RV1108_CLKGATE_CON(6), 7, GFLAGS),
|
||||
FACTOR(0, "sclk_cvbs_27m", "sclk_cvbs_host", 0, 1, 2),
|
||||
|
||||
GATE(SCLK_HDMI_SFR, "sclk_hdmi_sfr", "xin24m", 0,
|
||||
RV1108_CLKGATE_CON(6), 8, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_HDMI_CEC, "sclk_hdmi_cec", mux_hdmi_cec_src_p, 0,
|
||||
RV1108_CLKSEL_CON(34), 14, 2, MFLAGS, 0, 14, DFLAGS,
|
||||
RV1108_CLKGATE_CON(6), 9, GFLAGS),
|
||||
GATE(PCLK_MIPI_DSI, "pclk_mipi_dsi", "pclk_vio_pre", 0,
|
||||
RV1108_CLKGATE_CON(18), 8, GFLAGS),
|
||||
GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "pclk_vio_pre", 0,
|
||||
RV1108_CLKGATE_CON(18), 9, GFLAGS),
|
||||
|
||||
GATE(ACLK_ISP, "aclk_isp", "aclk_vio1_pre", 0,
|
||||
RV1108_CLKGATE_CON(18), 12, GFLAGS),
|
||||
GATE(HCLK_ISP, "hclk_isp", "hclk_vio_pre", 0,
|
||||
RV1108_CLKGATE_CON(18), 11, GFLAGS),
|
||||
COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_4plls_p, 0,
|
||||
RV1108_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
|
||||
RV1108_CLKGATE_CON(6), 3, GFLAGS),
|
||||
|
||||
GATE(0, "clk_dsiphy24m", "xin24m", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(9), 10, GFLAGS),
|
||||
GATE(0, "pclk_vdacphy", "pclk_top_pre", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(14), 9, GFLAGS),
|
||||
GATE(0, "pclk_mipi_dsiphy", "pclk_top_pre", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(14), 11, GFLAGS),
|
||||
GATE(0, "pclk_mipi_csiphy", "pclk_top_pre", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(14), 12, GFLAGS),
|
||||
|
||||
/*
|
||||
* Clock-Architecture Diagram 5
|
||||
|
|
@ -261,10 +505,11 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = {
|
|||
|
||||
FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
|
||||
|
||||
COMPOSITE(0, "i2s0_src", mux_pll_src_2plls_p, 0,
|
||||
|
||||
COMPOSITE(SCLK_I2S0_SRC, "i2s0_src", mux_pll_src_2plls_p, 0,
|
||||
RV1108_CLKSEL_CON(5), 8, 1, MFLAGS, 0, 7, DFLAGS,
|
||||
RV1108_CLKGATE_CON(2), 0, GFLAGS),
|
||||
COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT,
|
||||
COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT,
|
||||
RV1108_CLKSEL_CON(8), 0,
|
||||
RV1108_CLKGATE_CON(2), 1, GFLAGS,
|
||||
&rv1108_i2s0_fracmux),
|
||||
|
|
@ -274,7 +519,7 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = {
|
|||
RV1108_CLKSEL_CON(5), 15, 1, MFLAGS,
|
||||
RV1108_CLKGATE_CON(2), 3, GFLAGS),
|
||||
|
||||
COMPOSITE(0, "i2s1_src", mux_pll_src_2plls_p, 0,
|
||||
COMPOSITE(SCLK_I2S1_SRC, "i2s1_src", mux_pll_src_2plls_p, 0,
|
||||
RV1108_CLKSEL_CON(6), 8, 1, MFLAGS, 0, 7, DFLAGS,
|
||||
RV1108_CLKGATE_CON(2), 4, GFLAGS),
|
||||
COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT,
|
||||
|
|
@ -284,7 +529,7 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = {
|
|||
GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
|
||||
RV1108_CLKGATE_CON(2), 6, GFLAGS),
|
||||
|
||||
COMPOSITE(0, "i2s2_src", mux_pll_src_2plls_p, 0,
|
||||
COMPOSITE(SCLK_I2S2_SRC, "i2s2_src", mux_pll_src_2plls_p, 0,
|
||||
RV1108_CLKSEL_CON(7), 8, 1, MFLAGS, 0, 7, DFLAGS,
|
||||
RV1108_CLKGATE_CON(3), 8, GFLAGS),
|
||||
COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT,
|
||||
|
|
@ -303,32 +548,53 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = {
|
|||
RV1108_CLKGATE_CON(1), 2, GFLAGS),
|
||||
COMPOSITE_NOGATE(ACLK_PRE, "aclk_bus_pre", mux_aclk_bus_src_p, 0,
|
||||
RV1108_CLKSEL_CON(2), 8, 2, MFLAGS, 0, 5, DFLAGS),
|
||||
COMPOSITE_NOMUX(0, "hclk_bus_pre", "aclk_bus_2wrap_occ", 0,
|
||||
COMPOSITE_NOMUX(HCLK_BUS, "hclk_bus_pre", "aclk_bus_pre", 0,
|
||||
RV1108_CLKSEL_CON(3), 0, 5, DFLAGS,
|
||||
RV1108_CLKGATE_CON(1), 4, GFLAGS),
|
||||
COMPOSITE_NOMUX(0, "pclken_bus", "aclk_bus_2wrap_occ", 0,
|
||||
COMPOSITE_NOMUX(0, "pclk_bus_pre", "aclk_bus_pre", 0,
|
||||
RV1108_CLKSEL_CON(3), 8, 5, DFLAGS,
|
||||
RV1108_CLKGATE_CON(1), 5, GFLAGS),
|
||||
GATE(0, "pclk_bus_pre", "pclken_bus", CLK_IGNORE_UNUSED,
|
||||
GATE(PCLK_BUS, "pclk_bus", "pclk_bus_pre", 0,
|
||||
RV1108_CLKGATE_CON(1), 6, GFLAGS),
|
||||
GATE(0, "pclk_top_pre", "pclken_bus", CLK_IGNORE_UNUSED,
|
||||
GATE(0, "pclk_top_pre", "pclk_bus_pre", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(1), 7, GFLAGS),
|
||||
GATE(0, "pclk_ddr_pre", "pclken_bus", CLK_IGNORE_UNUSED,
|
||||
GATE(0, "pclk_ddr_pre", "pclk_bus_pre", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(1), 8, GFLAGS),
|
||||
GATE(0, "clk_timer0", "mux_pll_p", CLK_IGNORE_UNUSED,
|
||||
GATE(SCLK_TIMER0, "clk_timer0", "xin24m", 0,
|
||||
RV1108_CLKGATE_CON(1), 9, GFLAGS),
|
||||
GATE(0, "clk_timer1", "mux_pll_p", CLK_IGNORE_UNUSED,
|
||||
GATE(SCLK_TIMER1, "clk_timer1", "xin24m", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(1), 10, GFLAGS),
|
||||
GATE(0, "pclk_timer", "pclk_bus_pre", CLK_IGNORE_UNUSED,
|
||||
GATE(PCLK_TIMER, "pclk_timer", "pclk_bus_pre", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(13), 4, GFLAGS),
|
||||
|
||||
COMPOSITE(0, "uart0_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
|
||||
GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_bus_pre", 0,
|
||||
RV1108_CLKGATE_CON(12), 7, GFLAGS),
|
||||
GATE(HCLK_I2S1_2CH, "hclk_i2s1_2ch", "hclk_bus_pre", 0,
|
||||
RV1108_CLKGATE_CON(12), 8, GFLAGS),
|
||||
GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_bus_pre", 0,
|
||||
RV1108_CLKGATE_CON(12), 9, GFLAGS),
|
||||
|
||||
GATE(HCLK_CRYPTO_MST, "hclk_crypto_mst", "hclk_bus_pre", 0,
|
||||
RV1108_CLKGATE_CON(12), 10, GFLAGS),
|
||||
GATE(HCLK_CRYPTO_SLV, "hclk_crypto_slv", "hclk_bus_pre", 0,
|
||||
RV1108_CLKGATE_CON(12), 11, GFLAGS),
|
||||
COMPOSITE(SCLK_CRYPTO, "sclk_crypto", mux_pll_src_2plls_p, 0,
|
||||
RV1108_CLKSEL_CON(11), 7, 1, MFLAGS, 0, 5, DFLAGS,
|
||||
RV1108_CLKGATE_CON(2), 12, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_SPI, "sclk_spi", mux_pll_src_2plls_p, 0,
|
||||
RV1108_CLKSEL_CON(11), 15, 1, MFLAGS, 8, 5, DFLAGS,
|
||||
RV1108_CLKGATE_CON(3), 0, GFLAGS),
|
||||
GATE(PCLK_SPI, "pclk_spi", "pclk_bus_pre", 0,
|
||||
RV1108_CLKGATE_CON(13), 5, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_UART0_SRC, "uart0_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKSEL_CON(13), 12, 2, MFLAGS, 0, 7, DFLAGS,
|
||||
RV1108_CLKGATE_CON(3), 1, GFLAGS),
|
||||
COMPOSITE(0, "uart1_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
|
||||
COMPOSITE(SCLK_UART1_SRC, "uart1_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKSEL_CON(14), 12, 2, MFLAGS, 0, 7, DFLAGS,
|
||||
RV1108_CLKGATE_CON(3), 3, GFLAGS),
|
||||
COMPOSITE(0, "uart21_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
|
||||
COMPOSITE(SCLK_UART2_SRC, "uart2_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKSEL_CON(15), 12, 2, MFLAGS, 0, 7, DFLAGS,
|
||||
RV1108_CLKGATE_CON(3), 5, GFLAGS),
|
||||
|
||||
|
|
@ -344,44 +610,58 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = {
|
|||
RV1108_CLKSEL_CON(18), 0,
|
||||
RV1108_CLKGATE_CON(3), 6, GFLAGS,
|
||||
&rv1108_uart2_fracmux),
|
||||
GATE(PCLK_UART0, "pclk_uart0", "pclk_bus_pre", CLK_IGNORE_UNUSED,
|
||||
GATE(PCLK_UART0, "pclk_uart0", "pclk_bus_pre", 0,
|
||||
RV1108_CLKGATE_CON(13), 10, GFLAGS),
|
||||
GATE(PCLK_UART1, "pclk_uart1", "pclk_bus_pre", CLK_IGNORE_UNUSED,
|
||||
GATE(PCLK_UART1, "pclk_uart1", "pclk_bus_pre", 0,
|
||||
RV1108_CLKGATE_CON(13), 11, GFLAGS),
|
||||
GATE(PCLK_UART2, "pclk_uart2", "pclk_bus_pre", CLK_IGNORE_UNUSED,
|
||||
GATE(PCLK_UART2, "pclk_uart2", "pclk_bus_pre", 0,
|
||||
RV1108_CLKGATE_CON(13), 12, GFLAGS),
|
||||
|
||||
COMPOSITE(0, "clk_i2c1", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKSEL_CON(19), 15, 2, MFLAGS, 8, 7, DFLAGS,
|
||||
COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_pll_src_2plls_p, 0,
|
||||
RV1108_CLKSEL_CON(19), 15, 1, MFLAGS, 8, 7, DFLAGS,
|
||||
RV1108_CLKGATE_CON(3), 7, GFLAGS),
|
||||
COMPOSITE(0, "clk_i2c2", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKSEL_CON(20), 7, 2, MFLAGS, 0, 7, DFLAGS,
|
||||
COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_pll_src_2plls_p, 0,
|
||||
RV1108_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 7, DFLAGS,
|
||||
RV1108_CLKGATE_CON(3), 8, GFLAGS),
|
||||
COMPOSITE(0, "clk_i2c3", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKSEL_CON(20), 15, 2, MFLAGS, 8, 7, DFLAGS,
|
||||
COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_pll_src_2plls_p, 0,
|
||||
RV1108_CLKSEL_CON(20), 15, 1, MFLAGS, 8, 7, DFLAGS,
|
||||
RV1108_CLKGATE_CON(3), 9, GFLAGS),
|
||||
GATE(0, "pclk_i2c1", "pclk_bus_pre", CLK_IGNORE_UNUSED,
|
||||
GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus_pre", 0,
|
||||
RV1108_CLKGATE_CON(13), 0, GFLAGS),
|
||||
GATE(0, "pclk_i2c2", "pclk_bus_pre", CLK_IGNORE_UNUSED,
|
||||
GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus_pre", 0,
|
||||
RV1108_CLKGATE_CON(13), 1, GFLAGS),
|
||||
GATE(0, "pclk_i2c3", "pclk_bus_pre", CLK_IGNORE_UNUSED,
|
||||
GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus_pre", 0,
|
||||
RV1108_CLKGATE_CON(13), 2, GFLAGS),
|
||||
COMPOSITE(0, "clk_pwm1", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED,
|
||||
COMPOSITE(SCLK_PWM, "clk_pwm", mux_pll_src_2plls_p, 0,
|
||||
RV1108_CLKSEL_CON(12), 15, 2, MFLAGS, 8, 7, DFLAGS,
|
||||
RV1108_CLKGATE_CON(3), 10, GFLAGS),
|
||||
GATE(0, "pclk_pwm1", "pclk_bus_pre", CLK_IGNORE_UNUSED,
|
||||
GATE(PCLK_PWM, "pclk_pwm", "pclk_bus_pre", 0,
|
||||
RV1108_CLKGATE_CON(13), 6, GFLAGS),
|
||||
GATE(0, "pclk_wdt", "pclk_bus_pre", CLK_IGNORE_UNUSED,
|
||||
GATE(PCLK_WDT, "pclk_wdt", "pclk_bus_pre", 0,
|
||||
RV1108_CLKGATE_CON(13), 3, GFLAGS),
|
||||
GATE(0, "pclk_gpio1", "pclk_bus_pre", CLK_IGNORE_UNUSED,
|
||||
GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus_pre", 0,
|
||||
RV1108_CLKGATE_CON(13), 7, GFLAGS),
|
||||
GATE(0, "pclk_gpio2", "pclk_bus_pre", CLK_IGNORE_UNUSED,
|
||||
GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus_pre", 0,
|
||||
RV1108_CLKGATE_CON(13), 8, GFLAGS),
|
||||
GATE(0, "pclk_gpio3", "pclk_bus_pre", CLK_IGNORE_UNUSED,
|
||||
GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus_pre", 0,
|
||||
RV1108_CLKGATE_CON(13), 9, GFLAGS),
|
||||
|
||||
GATE(0, "pclk_grf", "pclk_bus_pre", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(14), 0, GFLAGS),
|
||||
GATE(PCLK_EFUSE0, "pclk_efuse0", "pclk_bus_pre", 0,
|
||||
RV1108_CLKGATE_CON(12), 12, GFLAGS),
|
||||
GATE(PCLK_EFUSE1, "pclk_efuse1", "pclk_bus_pre", 0,
|
||||
RV1108_CLKGATE_CON(12), 13, GFLAGS),
|
||||
GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus_pre", 0,
|
||||
RV1108_CLKGATE_CON(13), 13, GFLAGS),
|
||||
COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin24m", 0,
|
||||
RV1108_CLKSEL_CON(21), 0, 10, DFLAGS,
|
||||
RV1108_CLKGATE_CON(3), 11, GFLAGS),
|
||||
GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus_pre", 0,
|
||||
RV1108_CLKGATE_CON(13), 14, GFLAGS),
|
||||
COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0,
|
||||
RV1108_CLKSEL_CON(22), 0, 10, DFLAGS,
|
||||
RV1108_CLKGATE_CON(3), 12, GFLAGS),
|
||||
|
||||
GATE(ACLK_DMAC, "aclk_dmac", "aclk_bus_pre", 0,
|
||||
RV1108_CLKGATE_CON(12), 2, GFLAGS),
|
||||
|
|
@ -397,18 +677,24 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = {
|
|||
RV1108_CLKGATE_CON(0), 9, GFLAGS),
|
||||
GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(0), 10, GFLAGS),
|
||||
COMPOSITE(0, "ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
|
||||
COMPOSITE_NOGATE(0, "clk_ddrphy_src", mux_ddrphy_p, CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKSEL_CON(4), 8, 2, MFLAGS, 0, 3,
|
||||
DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
|
||||
DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
|
||||
FACTOR(0, "clk_ddr", "clk_ddrphy_src", 0, 1, 2),
|
||||
GATE(0, "clk_ddrphy4x", "clk_ddr", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(10), 9, GFLAGS),
|
||||
GATE(0, "ddrupctl", "ddrphy_pre", CLK_IGNORE_UNUSED,
|
||||
GATE(0, "pclk_ddrupctl", "pclk_ddr_pre", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(12), 4, GFLAGS),
|
||||
GATE(0, "ddrc", "ddrphy", CLK_IGNORE_UNUSED,
|
||||
GATE(0, "nclk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(12), 5, GFLAGS),
|
||||
GATE(0, "ddrmon", "ddrphy_pre", CLK_IGNORE_UNUSED,
|
||||
GATE(0, "pclk_ddrmon", "pclk_ddr_pre", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(12), 6, GFLAGS),
|
||||
GATE(0, "timer_clk", "xin24m", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(0), 11, GFLAGS),
|
||||
GATE(0, "pclk_mschniu", "pclk_ddr_pre", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(14), 2, GFLAGS),
|
||||
GATE(0, "pclk_ddrphy", "pclk_ddr_pre", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(14), 4, GFLAGS),
|
||||
|
||||
/*
|
||||
* Clock-Architecture Diagram 6
|
||||
|
|
@ -418,23 +704,23 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = {
|
|||
COMPOSITE_NOMUX(0, "pclk_periph_pre", "gpll", 0,
|
||||
RV1108_CLKSEL_CON(23), 10, 5, DFLAGS,
|
||||
RV1108_CLKGATE_CON(4), 5, GFLAGS),
|
||||
GATE(0, "pclk_periph", "pclk_periph_pre", CLK_IGNORE_UNUSED,
|
||||
GATE(PCLK_PERI, "pclk_periph", "pclk_periph_pre", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(15), 13, GFLAGS),
|
||||
COMPOSITE_NOMUX(0, "hclk_periph_pre", "gpll", 0,
|
||||
RV1108_CLKSEL_CON(23), 5, 5, DFLAGS,
|
||||
RV1108_CLKGATE_CON(4), 4, GFLAGS),
|
||||
GATE(0, "hclk_periph", "hclk_periph_pre", CLK_IGNORE_UNUSED,
|
||||
GATE(HCLK_PERI, "hclk_periph", "hclk_periph_pre", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(15), 12, GFLAGS),
|
||||
|
||||
GATE(0, "aclk_peri_src_dpll", "dpll", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(4), 1, GFLAGS),
|
||||
GATE(0, "aclk_peri_src_gpll", "gpll", CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKGATE_CON(4), 2, GFLAGS),
|
||||
COMPOSITE(0, "aclk_periph", mux_aclk_peri_src_p, CLK_IGNORE_UNUSED,
|
||||
RV1108_CLKSEL_CON(23), 15, 2, MFLAGS, 0, 5, DFLAGS,
|
||||
COMPOSITE(ACLK_PERI, "aclk_periph", mux_aclk_peri_src_p, 0,
|
||||
RV1108_CLKSEL_CON(23), 15, 1, MFLAGS, 0, 5, DFLAGS,
|
||||
RV1108_CLKGATE_CON(15), 11, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0,
|
||||
COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
|
||||
RV1108_CLKSEL_CON(25), 8, 2, MFLAGS, 0, 8, DFLAGS,
|
||||
RV1108_CLKGATE_CON(5), 0, GFLAGS),
|
||||
|
||||
|
|
@ -454,23 +740,31 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = {
|
|||
GATE(HCLK_EMMC, "hclk_emmc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 2, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_2plls_p, 0,
|
||||
RV1108_CLKSEL_CON(27), 14, 2, MFLAGS, 8, 5, DFLAGS,
|
||||
RV1108_CLKSEL_CON(27), 14, 1, MFLAGS, 8, 5, DFLAGS,
|
||||
RV1108_CLKGATE_CON(5), 3, GFLAGS),
|
||||
GATE(HCLK_NANDC, "hclk_nandc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 3, GFLAGS),
|
||||
|
||||
GATE(HCLK_HOST0, "hclk_host0", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 6, GFLAGS),
|
||||
GATE(0, "hclk_host0_arb", "hclk_periph", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(15), 7, GFLAGS),
|
||||
GATE(HCLK_OTG, "hclk_otg", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 8, GFLAGS),
|
||||
GATE(0, "hclk_otg_pmu", "hclk_periph", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(15), 9, GFLAGS),
|
||||
GATE(SCLK_USBPHY, "clk_usbphy", "xin24m", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(5), 5, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_2plls_p, 0,
|
||||
RV1108_CLKSEL_CON(27), 7, 2, MFLAGS, 0, 7, DFLAGS,
|
||||
RV1108_CLKSEL_CON(27), 7, 1, MFLAGS, 0, 7, DFLAGS,
|
||||
RV1108_CLKGATE_CON(5), 4, GFLAGS),
|
||||
GATE(HCLK_SFC, "hclk_sfc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 10, GFLAGS),
|
||||
|
||||
COMPOSITE(0, "sclk_macphy_pre", mux_pll_src_apll_gpll_p, 0,
|
||||
RV1108_CLKSEL_CON(24), 12, 2, MFLAGS, 0, 5, DFLAGS,
|
||||
COMPOSITE(SCLK_MAC_PRE, "sclk_mac_pre", mux_pll_src_apll_gpll_p, 0,
|
||||
RV1108_CLKSEL_CON(24), 12, 1, MFLAGS, 0, 5, DFLAGS,
|
||||
RV1108_CLKGATE_CON(4), 10, GFLAGS),
|
||||
MUX(0, "sclk_macphy", mux_sclk_macphy_p, CLK_SET_RATE_PARENT,
|
||||
RV1108_CLKSEL_CON(24), 8, 2, MFLAGS),
|
||||
GATE(0, "sclk_macphy_rx", "sclk_macphy", 0, RV1108_CLKGATE_CON(4), 8, GFLAGS),
|
||||
GATE(0, "sclk_mac_ref", "sclk_macphy", 0, RV1108_CLKGATE_CON(4), 6, GFLAGS),
|
||||
GATE(0, "sclk_mac_refout", "sclk_macphy", 0, RV1108_CLKGATE_CON(4), 7, GFLAGS),
|
||||
MUX(SCLK_MAC, "sclk_mac", mux_sclk_mac_p, CLK_SET_RATE_PARENT,
|
||||
RV1108_CLKSEL_CON(24), 8, 1, MFLAGS),
|
||||
GATE(SCLK_MAC_RX, "sclk_mac_rx", "sclk_mac", 0, RV1108_CLKGATE_CON(4), 8, GFLAGS),
|
||||
GATE(SCLK_MAC_REF, "sclk_mac_ref", "sclk_mac", 0, RV1108_CLKGATE_CON(4), 6, GFLAGS),
|
||||
GATE(SCLK_MAC_REFOUT, "sclk_mac_refout", "sclk_mac", 0, RV1108_CLKGATE_CON(4), 7, GFLAGS),
|
||||
GATE(ACLK_GMAC, "aclk_gmac", "aclk_periph", 0, RV1108_CLKGATE_CON(15), 4, GFLAGS),
|
||||
GATE(PCLK_GMAC, "pclk_gmac", "pclk_periph", 0, RV1108_CLKGATE_CON(15), 5, GFLAGS),
|
||||
|
||||
MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RV1108_SDMMC_CON0, 1),
|
||||
MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RV1108_SDMMC_CON1, 1),
|
||||
|
|
@ -484,10 +778,16 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = {
|
|||
|
||||
static const char *const rv1108_critical_clocks[] __initconst = {
|
||||
"aclk_core",
|
||||
"aclk_bus_src_gpll",
|
||||
"aclk_bus",
|
||||
"hclk_bus",
|
||||
"pclk_bus",
|
||||
"aclk_periph",
|
||||
"hclk_periph",
|
||||
"pclk_periph",
|
||||
"nclk_ddrupctl",
|
||||
"pclk_ddrmon",
|
||||
"pclk_acodecphy",
|
||||
"pclk_pmu",
|
||||
};
|
||||
|
||||
static void __init rv1108_clk_init(struct device_node *np)
|
||||
|
|
|
|||
|
|
@ -29,6 +29,7 @@
|
|||
#include <linux/mfd/syscon.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/reboot.h>
|
||||
#include <linux/rational.h>
|
||||
#include "clk.h"
|
||||
|
||||
/**
|
||||
|
|
@ -164,6 +165,40 @@ static int rockchip_clk_frac_notifier_cb(struct notifier_block *nb,
|
|||
return notifier_from_errno(ret);
|
||||
}
|
||||
|
||||
/**
|
||||
* fractional divider must set that denominator is 20 times larger than
|
||||
* numerator to generate precise clock frequency.
|
||||
*/
|
||||
void rockchip_fractional_approximation(struct clk_hw *hw,
|
||||
unsigned long rate, unsigned long *parent_rate,
|
||||
unsigned long *m, unsigned long *n)
|
||||
{
|
||||
struct clk_fractional_divider *fd = to_clk_fd(hw);
|
||||
unsigned long p_rate, p_parent_rate;
|
||||
struct clk_hw *p_parent;
|
||||
unsigned long scale;
|
||||
|
||||
p_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
|
||||
if ((rate * 20 > p_rate) && (p_rate % rate != 0)) {
|
||||
p_parent = clk_hw_get_parent(clk_hw_get_parent(hw));
|
||||
p_parent_rate = clk_hw_get_rate(p_parent);
|
||||
*parent_rate = p_parent_rate;
|
||||
}
|
||||
|
||||
/*
|
||||
* Get rate closer to *parent_rate to guarantee there is no overflow
|
||||
* for m and n. In the result it will be the nearest rate left shifted
|
||||
* by (scale - fd->nwidth) bits.
|
||||
*/
|
||||
scale = fls_long(*parent_rate / rate - 1);
|
||||
if (scale > fd->nwidth)
|
||||
rate <<= scale - fd->nwidth;
|
||||
|
||||
rational_best_approximation(rate, *parent_rate,
|
||||
GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
|
||||
m, n);
|
||||
}
|
||||
|
||||
static struct clk *rockchip_clk_register_frac_branch(
|
||||
struct rockchip_clk_provider *ctx, const char *name,
|
||||
const char *const *parent_names, u8 num_parents,
|
||||
|
|
@ -210,6 +245,7 @@ static struct clk *rockchip_clk_register_frac_branch(
|
|||
div->nwidth = 16;
|
||||
div->nmask = GENMASK(div->nwidth - 1, 0) << div->nshift;
|
||||
div->lock = lock;
|
||||
div->approximation = rockchip_fractional_approximation;
|
||||
div_ops = &clk_fractional_divider_ops;
|
||||
|
||||
clk = clk_register_composite(NULL, name, parent_names, num_parents,
|
||||
|
|
|
|||
|
|
@ -49,6 +49,7 @@
|
|||
#define SCLK_EMMC_DRV 117
|
||||
#define SCLK_SDMMC_SAMPLE 118
|
||||
#define SCLK_SDIO_SAMPLE 119
|
||||
#define SCLK_SDIO_SRC 120
|
||||
#define SCLK_EMMC_SAMPLE 121
|
||||
#define SCLK_VOP 122
|
||||
#define SCLK_HDMI_HDCP 123
|
||||
|
|
|
|||
|
|
@ -43,12 +43,74 @@
|
|||
#define SCLK_SDMMC_SAMPLE 84
|
||||
#define SCLK_SDIO_SAMPLE 85
|
||||
#define SCLK_EMMC_SAMPLE 86
|
||||
#define SCLK_VENC_CORE 87
|
||||
#define SCLK_HEVC_CORE 88
|
||||
#define SCLK_HEVC_CABAC 89
|
||||
#define SCLK_PWM0_PMU 90
|
||||
#define SCLK_I2C0_PMU 91
|
||||
#define SCLK_WIFI 92
|
||||
#define SCLK_CIFOUT 93
|
||||
#define SCLK_MIPI_CSI_OUT 94
|
||||
#define SCLK_CIF0 95
|
||||
#define SCLK_CIF1 96
|
||||
#define SCLK_CIF2 97
|
||||
#define SCLK_CIF3 98
|
||||
#define SCLK_DSP 99
|
||||
#define SCLK_DSP_IOP 100
|
||||
#define SCLK_DSP_EPP 101
|
||||
#define SCLK_DSP_EDP 102
|
||||
#define SCLK_DSP_EDAP 103
|
||||
#define SCLK_CVBS_HOST 104
|
||||
#define SCLK_HDMI_SFR 105
|
||||
#define SCLK_HDMI_CEC 106
|
||||
#define SCLK_CRYPTO 107
|
||||
#define SCLK_SPI 108
|
||||
#define SCLK_SARADC 109
|
||||
#define SCLK_TSADC 110
|
||||
#define SCLK_MAC_PRE 111
|
||||
#define SCLK_MAC 112
|
||||
#define SCLK_MAC_RX 113
|
||||
#define SCLK_MAC_REF 114
|
||||
#define SCLK_MAC_REFOUT 115
|
||||
#define SCLK_DSP_PFM 116
|
||||
#define SCLK_RGA 117
|
||||
#define SCLK_I2C1 118
|
||||
#define SCLK_I2C2 119
|
||||
#define SCLK_I2C3 120
|
||||
#define SCLK_PWM 121
|
||||
#define SCLK_ISP 122
|
||||
#define SCLK_USBPHY 123
|
||||
#define SCLK_I2S0_SRC 124
|
||||
#define SCLK_I2S1_SRC 125
|
||||
#define SCLK_I2S2_SRC 126
|
||||
#define SCLK_UART0_SRC 127
|
||||
#define SCLK_UART1_SRC 128
|
||||
#define SCLK_UART2_SRC 129
|
||||
|
||||
#define DCLK_VOP_SRC 185
|
||||
#define DCLK_HDMIPHY 186
|
||||
#define DCLK_VOP 187
|
||||
|
||||
/* aclk gates */
|
||||
#define ACLK_DMAC 192
|
||||
#define ACLK_PRE 193
|
||||
#define ACLK_CORE 194
|
||||
#define ACLK_ENMCORE 195
|
||||
#define ACLK_RKVENC 196
|
||||
#define ACLK_RKVDEC 197
|
||||
#define ACLK_VPU 198
|
||||
#define ACLK_CIF0 199
|
||||
#define ACLK_VIO0 200
|
||||
#define ACLK_VIO1 201
|
||||
#define ACLK_VOP 202
|
||||
#define ACLK_IEP 203
|
||||
#define ACLK_RGA 204
|
||||
#define ACLK_ISP 205
|
||||
#define ACLK_CIF1 206
|
||||
#define ACLK_CIF2 207
|
||||
#define ACLK_CIF3 208
|
||||
#define ACLK_PERI 209
|
||||
#define ACLK_GMAC 210
|
||||
|
||||
/* pclk gates */
|
||||
#define PCLK_GPIO1 256
|
||||
|
|
@ -67,10 +129,24 @@
|
|||
#define PCLK_PWM 269
|
||||
#define PCLK_TIMER 270
|
||||
#define PCLK_PERI 271
|
||||
#define PCLK_GPIO0_PMU 272
|
||||
#define PCLK_I2C0_PMU 273
|
||||
#define PCLK_PWM0_PMU 274
|
||||
#define PCLK_ISP 275
|
||||
#define PCLK_VIO 276
|
||||
#define PCLK_MIPI_DSI 277
|
||||
#define PCLK_HDMI_CTRL 278
|
||||
#define PCLK_SARADC 279
|
||||
#define PCLK_DSP_CFG 280
|
||||
#define PCLK_BUS 281
|
||||
#define PCLK_EFUSE0 282
|
||||
#define PCLK_EFUSE1 283
|
||||
#define PCLK_WDT 284
|
||||
#define PCLK_GMAC 285
|
||||
|
||||
/* hclk gates */
|
||||
#define HCLK_I2S0_8CH 320
|
||||
#define HCLK_I2S1_8CH 321
|
||||
#define HCLK_I2S1_2CH 321
|
||||
#define HCLK_I2S2_2CH 322
|
||||
#define HCLK_NANDC 323
|
||||
#define HCLK_SDMMC 324
|
||||
|
|
@ -78,20 +154,37 @@
|
|||
#define HCLK_EMMC 326
|
||||
#define HCLK_PERI 327
|
||||
#define HCLK_SFC 328
|
||||
#define HCLK_RKVENC 329
|
||||
#define HCLK_RKVDEC 330
|
||||
#define HCLK_CIF0 331
|
||||
#define HCLK_VIO 332
|
||||
#define HCLK_VOP 333
|
||||
#define HCLK_IEP 334
|
||||
#define HCLK_RGA 335
|
||||
#define HCLK_ISP 336
|
||||
#define HCLK_CRYPTO_MST 337
|
||||
#define HCLK_CRYPTO_SLV 338
|
||||
#define HCLK_HOST0 339
|
||||
#define HCLK_OTG 340
|
||||
#define HCLK_CIF1 341
|
||||
#define HCLK_CIF2 342
|
||||
#define HCLK_CIF3 343
|
||||
#define HCLK_BUS 344
|
||||
#define HCLK_VPU 345
|
||||
|
||||
#define CLK_NR_CLKS (HCLK_SFC + 1)
|
||||
#define CLK_NR_CLKS (HCLK_VPU + 1)
|
||||
|
||||
/* reset id */
|
||||
#define SRST_CORE_PO_AD 0
|
||||
#define SRST_CORE_PO_AD 0
|
||||
#define SRST_CORE_AD 1
|
||||
#define SRST_L2_AD 2
|
||||
#define SRST_CPU_NIU_AD 3
|
||||
#define SRST_CPU_NIU_AD 3
|
||||
#define SRST_CORE_PO 4
|
||||
#define SRST_CORE 5
|
||||
#define SRST_L2 6
|
||||
#define SRST_L2 6
|
||||
#define SRST_CORE_DBG 8
|
||||
#define PRST_DBG 9
|
||||
#define RST_DAP 10
|
||||
#define RST_DAP 10
|
||||
#define PRST_DBG_NIU 11
|
||||
#define ARST_STRC_SYS_AD 15
|
||||
|
||||
|
|
@ -158,9 +251,9 @@
|
|||
#define HRST_SYSBUS 75
|
||||
#define PRST_USBGRF 76
|
||||
|
||||
#define ARST_PERIPH_NIU 80
|
||||
#define HRST_PERIPH_NIU 81
|
||||
#define PRST_PERIPH_NIU 82
|
||||
#define ARST_PERIPH_NIU 80
|
||||
#define HRST_PERIPH_NIU 81
|
||||
#define PRST_PERIPH_NIU 82
|
||||
#define HRST_PERIPH 83
|
||||
#define HRST_SDMMC 84
|
||||
#define HRST_SDIO 85
|
||||
|
|
@ -178,7 +271,7 @@
|
|||
#define HRST_HOST0_AUX 96
|
||||
#define HRST_HOST0_ARB 97
|
||||
#define SRST_HOST0_EHCIPHY 98
|
||||
#define SRST_HOST0_UTMI 99
|
||||
#define SRST_HOST0_UTMI 99
|
||||
#define SRST_USBPOR 100
|
||||
#define SRST_UTMI0 101
|
||||
#define SRST_UTMI1 102
|
||||
|
|
@ -225,21 +318,21 @@
|
|||
#define HRST_VPU_NIU 141
|
||||
#define ARST_VPU 142
|
||||
#define HRST_VPU 143
|
||||
#define ARST_RKVDEC_NIU 144
|
||||
#define HRST_RKVDEC_NIU 145
|
||||
#define ARST_RKVDEC_NIU 144
|
||||
#define HRST_RKVDEC_NIU 145
|
||||
#define ARST_RKVDEC 146
|
||||
#define HRST_RKVDEC 147
|
||||
#define SRST_RKVDEC_CABAC 148
|
||||
#define SRST_RKVDEC_CORE 149
|
||||
#define ARST_RKVENC_NIU 150
|
||||
#define HRST_RKVENC_NIU 151
|
||||
#define ARST_RKVENC_NIU 150
|
||||
#define HRST_RKVENC_NIU 151
|
||||
#define ARST_RKVENC 152
|
||||
#define HRST_RKVENC 153
|
||||
#define SRST_RKVENC_CORE 154
|
||||
|
||||
#define SRST_DSP_CORE 156
|
||||
#define SRST_DSP_SYS 157
|
||||
#define SRST_DSP_GLOBAL 158
|
||||
#define SRST_DSP_GLOBAL 158
|
||||
#define SRST_DSP_OECM 159
|
||||
#define PRST_DSP_IOP_NIU 160
|
||||
#define ARST_DSP_EPP_NIU 161
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|
@ -257,7 +350,7 @@
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#define SRST_PMU_I2C0 173
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#define PRST_PMU_I2C0 174
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#define PRST_PMU_GPIO0 175
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#define PRST_PMU_INTMEM 176
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#define PRST_PMU_INTMEM 176
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||||
#define PRST_PMU_PWM0 177
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#define SRST_PMU_PWM0 178
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#define PRST_PMU_GRF 179
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||||
|
|
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|||
|
|
@ -565,6 +565,9 @@ struct clk_fractional_divider {
|
|||
u8 nwidth;
|
||||
u32 nmask;
|
||||
u8 flags;
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||||
void (*approximation)(struct clk_hw *hw,
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||||
unsigned long rate, unsigned long *parent_rate,
|
||||
unsigned long *m, unsigned long *n);
|
||||
spinlock_t *lock;
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue