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clk: qcom: Enable clocks which needs to be always on for SDM845
There are certain clocks which needs to be always enabled for system operation. Add support for the same by adding 'CLK_IS_CRITICAL' flag for such clocks. Signed-off-by: Amit Nischal <anischal@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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ce397d215c
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@ -1103,6 +1103,7 @@ static struct clk_branch gcc_camera_ahb_clk = {
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_camera_ahb_clk",
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.flags = CLK_IS_CRITICAL,
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.ops = &clk_branch2_ops,
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},
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},
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@ -1129,6 +1130,7 @@ static struct clk_branch gcc_camera_xo_clk = {
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_camera_xo_clk",
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.flags = CLK_IS_CRITICAL,
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.ops = &clk_branch2_ops,
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},
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},
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@ -1270,6 +1272,7 @@ static struct clk_branch gcc_disp_ahb_clk = {
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_disp_ahb_clk",
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.flags = CLK_IS_CRITICAL,
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.ops = &clk_branch2_ops,
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},
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},
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@ -1328,6 +1331,7 @@ static struct clk_branch gcc_disp_xo_clk = {
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_disp_xo_clk",
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.flags = CLK_IS_CRITICAL,
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.ops = &clk_branch2_ops,
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},
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},
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@ -1397,6 +1401,7 @@ static struct clk_branch gcc_gpu_cfg_ahb_clk = {
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_gpu_cfg_ahb_clk",
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.flags = CLK_IS_CRITICAL,
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.ops = &clk_branch2_ops,
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},
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},
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@ -2985,6 +2990,7 @@ static struct clk_branch gcc_video_ahb_clk = {
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_video_ahb_clk",
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.flags = CLK_IS_CRITICAL,
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.ops = &clk_branch2_ops,
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},
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},
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@ -3011,6 +3017,7 @@ static struct clk_branch gcc_video_xo_clk = {
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_video_xo_clk",
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.flags = CLK_IS_CRITICAL,
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.ops = &clk_branch2_ops,
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},
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},
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@ -3049,6 +3056,36 @@ static struct clk_branch gcc_vs_ctrl_clk = {
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},
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};
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static struct clk_branch gcc_cpuss_dvm_bus_clk = {
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.halt_reg = 0x48190,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x48190,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_cpuss_dvm_bus_clk",
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.flags = CLK_IS_CRITICAL,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gcc_cpuss_gnoc_clk = {
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.halt_reg = 0x48004,
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.halt_check = BRANCH_HALT_VOTED,
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.hwcg_reg = 0x48004,
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.hwcg_bit = 1,
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.clkr = {
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.enable_reg = 0x52004,
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.enable_mask = BIT(22),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_cpuss_gnoc_clk",
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.flags = CLK_IS_CRITICAL,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct gdsc pcie_0_gdsc = {
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.gdscr = 0x6b004,
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.pd = {
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@ -3344,6 +3381,8 @@ static struct clk_regmap *gcc_sdm845_clocks[] = {
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[GPLL0] = &gpll0.clkr,
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[GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
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[GPLL4] = &gpll4.clkr,
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[GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr,
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[GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,
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};
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static const struct qcom_reset_map gcc_sdm845_resets[] = {
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@ -3433,10 +3472,6 @@ static int gcc_sdm845_probe(struct platform_device *pdev)
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regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3);
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regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
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/* Enable CPUSS clocks */
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regmap_update_bits(regmap, 0x48190, BIT(0), 0x1);
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regmap_update_bits(regmap, 0x52004, BIT(22), 0x1);
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return qcom_cc_really_probe(pdev, &gcc_sdm845_desc, regmap);
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}
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@ -192,6 +192,8 @@
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#define GCC_VS_CTRL_CLK_SRC 182
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#define GCC_VSENSOR_CLK_SRC 183
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#define GPLL4 184
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#define GCC_CPUSS_DVM_BUS_CLK 185
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#define GCC_CPUSS_GNOC_CLK 186
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/* GCC Resets */
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#define GCC_MMSS_BCR 0
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