mirror of https://gitee.com/openkylin/linux.git
drm/i915/dp: convert eDP checks to functions and document
Most of the PCH eDP checks are redundant, so document the functions in preparation for removing most of the calls. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Jesse Barnes
Chris Wilson
parent
e59f2bac15
commit
cfcb0fc9c2
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@ -42,9 +42,6 @@
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#define DP_LINK_CONFIGURATION_SIZE 9
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#define IS_eDP(i) ((i)->base.type == INTEL_OUTPUT_EDP)
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#define IS_PCH_eDP(i) ((i)->is_pch_edp)
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struct intel_dp {
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struct intel_encoder base;
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uint32_t output_reg;
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@ -62,6 +59,31 @@ struct intel_dp {
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uint8_t link_status[DP_LINK_STATUS_SIZE];
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};
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/**
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* is_edp - is the given port attached to an eDP panel (either CPU or PCH)
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* @intel_dp: DP struct
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*
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* If a CPU or PCH DP output is attached to an eDP panel, this function
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* will return true, and false otherwise.
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*/
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static bool is_edp(struct intel_dp *intel_dp)
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{
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return intel_dp->base.type == INTEL_OUTPUT_EDP;
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}
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/**
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* is_pch_edp - is the port on the PCH and attached to an eDP panel?
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* @intel_dp: DP struct
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*
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* Returns true if the given DP struct corresponds to a PCH DP port attached
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* to an eDP panel, false otherwise. Helpful for determining whether we
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* may need FDI resources for a given DP output or not.
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*/
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static bool is_pch_edp(struct intel_dp *intel_dp)
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{
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return intel_dp->is_pch_edp;
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}
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static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
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{
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return container_of(encoder, struct intel_dp, base.base);
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@ -138,7 +160,7 @@ intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pi
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp))
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if (is_edp(intel_dp) || is_pch_edp(intel_dp))
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return (pixel_clock * dev_priv->edp.bpp + 7) / 8;
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else
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return pixel_clock * 3;
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@ -160,7 +182,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
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int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
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int max_lanes = intel_dp_max_lane_count(intel_dp);
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if ((IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) &&
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if ((is_edp(intel_dp) || is_pch_edp(intel_dp)) &&
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dev_priv->panel_fixed_mode) {
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if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay)
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return MODE_PANEL;
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@ -171,7 +193,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
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/* only refuse the mode on non eDP since we have seen some wierd eDP panels
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which are outside spec tolerances but somehow work by magic */
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if (!IS_eDP(intel_dp) &&
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if (!is_edp(intel_dp) &&
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(intel_dp_link_required(connector->dev, intel_dp, mode->clock)
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> intel_dp_max_data_rate(max_link_clock, max_lanes)))
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return MODE_CLOCK_HIGH;
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@ -258,7 +280,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
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* Note that PCH attached eDP panels should use a 125MHz input
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* clock divider.
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*/
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if (IS_eDP(intel_dp) && !IS_PCH_eDP(intel_dp)) {
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if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
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if (IS_GEN6(dev))
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aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
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else
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@ -530,7 +552,7 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
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int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
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static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
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if ((IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) &&
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if ((is_edp(intel_dp) || is_pch_edp(intel_dp)) &&
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dev_priv->panel_fixed_mode) {
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intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode);
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intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
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@ -560,7 +582,7 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
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}
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}
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if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) {
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if (is_edp(intel_dp) || is_pch_edp(intel_dp)) {
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/* okay we failed just pick the highest */
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intel_dp->lane_count = max_lane_count;
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intel_dp->link_bw = bws[max_clock];
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@ -652,7 +674,7 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
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intel_dp = enc_to_intel_dp(encoder);
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if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
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lane_count = intel_dp->lane_count;
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if (IS_PCH_eDP(intel_dp))
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if (is_pch_edp(intel_dp))
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bpp = dev_priv->edp.bpp;
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break;
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}
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@ -720,7 +742,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
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if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
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intel_dp->DP |= DP_SYNC_VS_HIGH;
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if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp))
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if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
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intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
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else
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intel_dp->DP |= DP_LINK_TRAIN_OFF;
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@ -755,7 +777,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
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if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
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intel_dp->DP |= DP_PIPEB_SELECT;
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if (IS_eDP(intel_dp)) {
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if (is_edp(intel_dp)) {
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/* don't miss out required setting for eDP */
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intel_dp->DP |= DP_PLL_ENABLE;
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if (adjusted_mode->clock < 200000)
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@ -909,7 +931,7 @@ static void intel_dp_prepare(struct drm_encoder *encoder)
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struct drm_i915_private *dev_priv = dev->dev_private;
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uint32_t dp_reg = I915_READ(intel_dp->output_reg);
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if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) {
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if (is_edp(intel_dp) || is_pch_edp(intel_dp)) {
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ironlake_edp_panel_off(dev);
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ironlake_edp_backlight_off(dev);
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ironlake_edp_panel_vdd_on(dev);
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@ -926,12 +948,12 @@ static void intel_dp_commit(struct drm_encoder *encoder)
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intel_dp_start_link_train(intel_dp);
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if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp))
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if (is_edp(intel_dp) || is_pch_edp(intel_dp))
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ironlake_edp_panel_on(dev);
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intel_dp_complete_link_train(intel_dp);
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if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp))
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if (is_edp(intel_dp) || is_pch_edp(intel_dp))
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ironlake_edp_backlight_on(dev);
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intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
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}
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@ -945,21 +967,21 @@ intel_dp_dpms(struct drm_encoder *encoder, int mode)
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uint32_t dp_reg = I915_READ(intel_dp->output_reg);
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if (mode != DRM_MODE_DPMS_ON) {
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if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) {
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if (is_edp(intel_dp) || is_pch_edp(intel_dp)) {
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ironlake_edp_backlight_off(dev);
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ironlake_edp_panel_off(dev);
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}
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if (dp_reg & DP_PORT_EN)
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intel_dp_link_down(intel_dp);
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if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp))
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if (is_edp(intel_dp) || is_pch_edp(intel_dp))
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ironlake_edp_pll_off(encoder);
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} else {
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if (!(dp_reg & DP_PORT_EN)) {
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intel_dp_start_link_train(intel_dp);
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if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp))
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if (is_edp(intel_dp) || is_pch_edp(intel_dp))
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ironlake_edp_panel_on(dev);
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intel_dp_complete_link_train(intel_dp);
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if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp))
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if (is_edp(intel_dp) || is_pch_edp(intel_dp))
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ironlake_edp_backlight_on(dev);
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}
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}
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@ -1234,7 +1256,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
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DP_LINK_CONFIGURATION_SIZE);
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DP |= DP_PORT_EN;
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if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp))
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if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
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DP &= ~DP_LINK_TRAIN_MASK_CPT;
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else
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DP &= ~DP_LINK_TRAIN_MASK;
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@ -1245,7 +1267,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
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for (;;) {
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/* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
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uint32_t signal_levels;
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if (IS_GEN6(dev) && IS_eDP(intel_dp)) {
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if (IS_GEN6(dev) && is_edp(intel_dp)) {
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signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
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DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
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} else {
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@ -1253,7 +1275,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
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DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
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}
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if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp))
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if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
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reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
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else
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reg = DP | DP_LINK_TRAIN_PAT_1;
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@ -1312,7 +1334,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
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/* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
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uint32_t signal_levels;
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if (IS_GEN6(dev) && IS_eDP(intel_dp)) {
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if (IS_GEN6(dev) && is_edp(intel_dp)) {
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signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
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DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
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} else {
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@ -1320,7 +1342,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
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DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
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}
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if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp))
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if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
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reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
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else
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reg = DP | DP_LINK_TRAIN_PAT_2;
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@ -1348,7 +1370,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
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++tries;
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}
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if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp))
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if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
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reg = DP | DP_LINK_TRAIN_OFF_CPT;
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else
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reg = DP | DP_LINK_TRAIN_OFF;
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@ -1368,14 +1390,14 @@ intel_dp_link_down(struct intel_dp *intel_dp)
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DRM_DEBUG_KMS("\n");
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if (IS_eDP(intel_dp)) {
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if (is_edp(intel_dp)) {
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DP &= ~DP_PLL_ENABLE;
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I915_WRITE(intel_dp->output_reg, DP);
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POSTING_READ(intel_dp->output_reg);
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udelay(100);
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}
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if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp)) {
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if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) {
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DP &= ~DP_LINK_TRAIN_MASK_CPT;
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I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
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} else {
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@ -1386,7 +1408,7 @@ intel_dp_link_down(struct intel_dp *intel_dp)
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msleep(17);
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if (IS_eDP(intel_dp))
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if (is_edp(intel_dp))
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DP |= DP_LINK_TRAIN_OFF;
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I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
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POSTING_READ(intel_dp->output_reg);
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@ -1425,7 +1447,7 @@ ironlake_dp_detect(struct drm_connector *connector)
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enum drm_connector_status status;
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/* Panel needs power for AUX to work */
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if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp))
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if (is_edp(intel_dp) || is_pch_edp(intel_dp))
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ironlake_edp_panel_vdd_on(connector->dev);
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status = connector_status_disconnected;
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if (intel_dp_aux_native_read(intel_dp,
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@ -1437,7 +1459,7 @@ ironlake_dp_detect(struct drm_connector *connector)
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}
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DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", intel_dp->dpcd[0],
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intel_dp->dpcd[1], intel_dp->dpcd[2], intel_dp->dpcd[3]);
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if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp))
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if (is_edp(intel_dp) || is_pch_edp(intel_dp))
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ironlake_edp_panel_vdd_off(connector->dev);
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return status;
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}
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@ -1504,7 +1526,7 @@ static int intel_dp_get_modes(struct drm_connector *connector)
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ret = intel_ddc_get_modes(connector, &intel_dp->adapter);
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if (ret) {
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if ((IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) &&
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if ((is_edp(intel_dp) || is_pch_edp(intel_dp)) &&
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!dev_priv->panel_fixed_mode) {
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struct drm_display_mode *newmode;
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list_for_each_entry(newmode, &connector->probed_modes,
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@ -1521,7 +1543,7 @@ static int intel_dp_get_modes(struct drm_connector *connector)
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}
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/* if eDP has no EDID, try to use fixed panel mode from VBT */
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if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) {
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if (is_edp(intel_dp) || is_pch_edp(intel_dp)) {
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if (dev_priv->panel_fixed_mode != NULL) {
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struct drm_display_mode *mode;
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mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
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@ -1651,7 +1673,7 @@ intel_dp_init(struct drm_device *dev, int output_reg)
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if (intel_dpd_is_edp(dev))
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intel_dp->is_pch_edp = true;
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if (output_reg == DP_A || IS_PCH_eDP(intel_dp)) {
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if (output_reg == DP_A || is_pch_edp(intel_dp)) {
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type = DRM_MODE_CONNECTOR_eDP;
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intel_encoder->type = INTEL_OUTPUT_EDP;
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} else {
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@ -1672,7 +1694,7 @@ intel_dp_init(struct drm_device *dev, int output_reg)
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else if (output_reg == DP_D || output_reg == PCH_DP_D)
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intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
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if (IS_eDP(intel_dp))
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if (is_edp(intel_dp))
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intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
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intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
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@ -1719,7 +1741,7 @@ intel_dp_init(struct drm_device *dev, int output_reg)
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intel_encoder->hot_plug = intel_dp_hot_plug;
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if (output_reg == DP_A || IS_PCH_eDP(intel_dp)) {
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if (output_reg == DP_A || is_pch_edp(intel_dp)) {
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/* initialize panel mode from VBT if available for eDP */
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if (dev_priv->lfp_lvds_vbt_mode) {
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dev_priv->panel_fixed_mode =
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