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drm/amdgpu: move the GDS switch into vm flush as well 

After all it's an operation on the VMID.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
This commit is contained in:
Christian König 2016-03-01 13:34:49 +01:00 committed by Alex Deucher
parent 364beb2cc4
commit cffadc83c7
3 changed files with 21 additions and 14 deletions
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6
drivers/gpu/drm/amd/amdgpu/amdgpu.h
View File

@ -957,8 +957,10 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
struct amdgpu_sync *sync, struct fence *fence, struct amdgpu_sync *sync, struct fence *fence,
unsigned *vm_id, uint64_t *vm_pd_addr); unsigned *vm_id, uint64_t *vm_pd_addr);
void amdgpu_vm_flush(struct amdgpu_ring *ring, void amdgpu_vm_flush(struct amdgpu_ring *ring,
unsigned vmid, unsigned vm_id, uint64_t pd_addr,
uint64_t pd_addr); uint32_t gds_base, uint32_t gds_size,
uint32_t gws_base, uint32_t gws_size,
uint32_t oa_base, uint32_t oa_size);
uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr); uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr);
int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
struct amdgpu_vm *vm); struct amdgpu_vm *vm);

11
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
View File

@ -150,13 +150,10 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
if (vm) { if (vm) {
/* do context switch */ /* do context switch */
amdgpu_vm_flush(ring, ib->vm_id, ib->vm_pd_addr); amdgpu_vm_flush(ring, ib->vm_id, ib->vm_pd_addr,
ib->gds_base, ib->gds_size,
if (ring->funcs->emit_gds_switch) ib->gws_base, ib->gws_size,
amdgpu_ring_emit_gds_switch(ring, ib->vm_id, ib->oa_base, ib->oa_size);
ib->gds_base, ib->gds_size,
ib->gws_base, ib->gws_size,
ib->oa_base, ib->oa_size);
if (ring->funcs->emit_hdp_flush) if (ring->funcs->emit_hdp_flush)
amdgpu_ring_emit_hdp_flush(ring); amdgpu_ring_emit_hdp_flush(ring);

18
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
View File

@ -241,19 +241,27 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
* amdgpu_vm_flush - hardware flush the vm * amdgpu_vm_flush - hardware flush the vm
* *
* @ring: ring to use for flush * @ring: ring to use for flush
* @vmid: vmid number to use * @vm_id: vmid number to use
* @pd_addr: address of the page directory * @pd_addr: address of the page directory
* *
* Emit a VM flush when it is necessary. * Emit a VM flush when it is necessary.
*/ */
void amdgpu_vm_flush(struct amdgpu_ring *ring, void amdgpu_vm_flush(struct amdgpu_ring *ring,
unsigned vmid, unsigned vm_id, uint64_t pd_addr,
uint64_t pd_addr) uint32_t gds_base, uint32_t gds_size,
uint32_t gws_base, uint32_t gws_size,
uint32_t oa_base, uint32_t oa_size)
{ {
if (pd_addr != AMDGPU_VM_NO_FLUSH) { if (pd_addr != AMDGPU_VM_NO_FLUSH) {
trace_amdgpu_vm_flush(pd_addr, ring->idx, vmid); trace_amdgpu_vm_flush(pd_addr, ring->idx, vm_id);
amdgpu_ring_emit_vm_flush(ring, vmid, pd_addr); amdgpu_ring_emit_vm_flush(ring, vm_id, pd_addr);
} }
if (ring->funcs->emit_gds_switch)
amdgpu_ring_emit_gds_switch(ring, vm_id,
gds_base, gds_size,
gws_base, gws_size,
oa_base, oa_size);
} }
/** /**