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drm/i915: Clean up skl_program_scaler() 

Remove the "sizes are 0 based" stuff that is not even true for the
scaler.

v2: Rebase

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181101151736.20522-1-ville.syrjala@linux.intel.com
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
Ville Syrjälä 2018-11-01 17:17:36 +02:00
parent e69b348a7a
commit d0105af939
1 changed files with 5 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
drivers/gpu/drm/i915/intel_sprite.c
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@ -311,12 +311,11 @@ skl_plane_max_stride(struct intel_plane *plane,
} }
static void static void
skl_program_scaler(struct drm_i915_private *dev_priv, skl_program_scaler(struct intel_plane *plane,
struct intel_plane *plane,
const struct intel_crtc_state *crtc_state, const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state) const struct intel_plane_state *plane_state)
{ {
enum plane_id plane_id = plane->id; struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum pipe pipe = plane->pipe; enum pipe pipe = plane->pipe;
int scaler_id = plane_state->scaler_id; int scaler_id = plane_state->scaler_id;
const struct intel_scaler *scaler = const struct intel_scaler *scaler =
@ -328,10 +327,6 @@ skl_program_scaler(struct drm_i915_private *dev_priv,
u16 y_hphase, uv_rgb_hphase; u16 y_hphase, uv_rgb_hphase;
u16 y_vphase, uv_rgb_vphase; u16 y_vphase, uv_rgb_vphase;
/* Sizes are 0 based */
crtc_w--;
crtc_h--;
/* TODO: handle sub-pixel coordinates */ /* TODO: handle sub-pixel coordinates */
if (plane_state->base.fb->format->format == DRM_FORMAT_NV12 && if (plane_state->base.fb->format->format == DRM_FORMAT_NV12 &&
!icl_is_hdr_plane(plane)) { !icl_is_hdr_plane(plane)) {
@ -351,15 +346,14 @@ skl_program_scaler(struct drm_i915_private *dev_priv,
} }
I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id), I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id),
PS_SCALER_EN | PS_PLANE_SEL(plane_id) | scaler->mode); PS_SCALER_EN | PS_PLANE_SEL(plane->id) | scaler->mode);
I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0); I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
I915_WRITE_FW(SKL_PS_VPHASE(pipe, scaler_id), I915_WRITE_FW(SKL_PS_VPHASE(pipe, scaler_id),
PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase)); PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase));
I915_WRITE_FW(SKL_PS_HPHASE(pipe, scaler_id), I915_WRITE_FW(SKL_PS_HPHASE(pipe, scaler_id),
PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase)); PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase));
I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y); I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (crtc_w << 16) | crtc_h);
((crtc_w + 1) << 16)|(crtc_h + 1));
} }
/* Preoffset values for YUV to RGB Conversion */ /* Preoffset values for YUV to RGB Conversion */
@ -548,11 +542,9 @@ skl_program_plane(struct intel_plane *plane,
I915_WRITE_FW(PLANE_CUS_CTL(pipe, plane_id), cus_ctl); I915_WRITE_FW(PLANE_CUS_CTL(pipe, plane_id), cus_ctl);
} }
/* program plane scaler */
if (plane_state->scaler_id >= 0) { if (plane_state->scaler_id >= 0) {
if (!slave) if (!slave)
skl_program_scaler(dev_priv, plane, skl_program_scaler(plane, crtc_state, plane_state);
crtc_state, plane_state);
I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0); I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
} else { } else {