mirror of https://gitee.com/openkylin/linux.git
drm/amd/powerplay: use smu7 common functions and data on Polars10.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rex Zhu
Alex Deucher
parent
ac43f0800f
commit
d01ec3fb8c
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@ -23,8 +23,7 @@
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#ifndef _POLARIS10_PWRVIRUS_H
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#define _POLARIS10_PWRVIRUS_H
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#define mmSMC_IND_INDEX_11 0x01AC
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#define mmSMC_IND_DATA_11 0x01AD
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#define mmCP_HYP_MEC1_UCODE_ADDR 0xf81a
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#define mmCP_HYP_MEC1_UCODE_DATA 0xf81b
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#define mmCP_HYP_MEC2_UCODE_ADDR 0xf81c
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@ -47,6 +47,7 @@
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#include "dce/dce_10_0_sh_mask.h"
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#include "polaris10_pwrvirus.h"
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#include "smu7_ppsmc.h"
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#include "smu7_smumgr.h"
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#define POLARIS10_SMC_SIZE 0x20000
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#define VOLTAGE_VID_OFFSET_SCALE1 625
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@ -230,7 +231,7 @@ static int polaris10_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_of
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const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
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uint32_t temp;
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if (polaris10_read_smc_sram_dword(hwmgr->smumgr,
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if (smu7_read_smc_sram_dword(hwmgr->smumgr,
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fuse_table_offset +
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offsetof(SMU74_Discrete_PmFuses, TdcWaterfallCtl),
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(uint32_t *)&temp, SMC_RAM_END))
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@ -319,7 +320,7 @@ static int polaris10_populate_pm_fuses(struct pp_hwmgr *hwmgr)
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if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_PowerContainment)) {
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if (polaris10_read_smc_sram_dword(hwmgr->smumgr,
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if (smu7_read_smc_sram_dword(hwmgr->smumgr,
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SMU7_FIRMWARE_HEADER_LOCATION +
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offsetof(SMU74_Firmware_Header, PmFuseTable),
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&pm_fuse_table_offset, SMC_RAM_END))
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@ -367,7 +368,7 @@ static int polaris10_populate_pm_fuses(struct pp_hwmgr *hwmgr)
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"Attempt to populate BapmVddCBaseLeakage Hi and Lo "
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"Sidd Failed!", return -EINVAL);
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if (polaris10_copy_bytes_to_smc(hwmgr->smumgr, pm_fuse_table_offset,
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if (smu7_copy_bytes_to_smc(hwmgr->smumgr, pm_fuse_table_offset,
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(uint8_t *)&smu_data->power_tune_table,
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(sizeof(struct SMU74_Discrete_PmFuses) - 92), SMC_RAM_END))
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PP_ASSERT_WITH_CODE(false,
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@ -755,7 +756,7 @@ int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
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struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
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uint8_t pcie_entry_cnt = (uint8_t) hw_data->dpm_table.pcie_speed_table.count;
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int result = 0;
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uint32_t array = smu_data->dpm_table_start +
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uint32_t array = smu_data->smu7_data.dpm_table_start +
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offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
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uint32_t array_size = sizeof(struct SMU74_Discrete_GraphicsLevel) *
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SMU74_MAX_LEVELS_GRAPHICS;
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@ -833,7 +834,7 @@ int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
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levels[1].pcieDpmLevel = mid_pcie_level_enabled;
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}
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/* level count will send to smc once at init smc table and never change */
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result = polaris10_copy_bytes_to_smc(smumgr, array, (uint8_t *)levels,
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result = smu7_copy_bytes_to_smc(smumgr, array, (uint8_t *)levels,
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(uint32_t)array_size, SMC_RAM_END);
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return result;
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@ -901,7 +902,7 @@ int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
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struct smu7_dpm_table *dpm_table = &hw_data->dpm_table;
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int result;
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/* populate MCLK dpm table to SMU7 */
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uint32_t array = smu_data->dpm_table_start +
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uint32_t array = smu_data->smu7_data.dpm_table_start +
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offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
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uint32_t array_size = sizeof(SMU74_Discrete_MemoryLevel) *
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SMU74_MAX_LEVELS_MEMORY;
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@ -938,7 +939,7 @@ int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
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phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
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/* level count will send to smc once at init smc table and never change */
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result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
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result = smu7_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
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(uint32_t)array_size, SMC_RAM_END);
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return result;
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@ -1216,9 +1217,9 @@ static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
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}
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}
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result = polaris10_copy_bytes_to_smc(
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result = smu7_copy_bytes_to_smc(
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hwmgr->smumgr,
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smu_data->arb_table_start,
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smu_data->smu7_data.arb_table_start,
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(uint8_t *)&arb_regs,
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sizeof(SMU74_Discrete_MCArbDramTimingTable),
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SMC_RAM_END);
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@ -1463,7 +1464,7 @@ static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr,
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if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
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config = VR_SVI2_PLANE_2;
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table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
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cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, smu_data->soft_regs_start +
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cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, smu_data->smu7_data.soft_regs_start +
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offsetof(SMU74_SoftRegisters, AllowMvddSwitch), 0x1);
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} else {
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config = VR_STATIC_VOLTAGE;
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@ -1529,20 +1530,20 @@ static int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
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AVFS_SclkOffset.Sclk_Offset[i] = PP_HOST_TO_SMC_US((uint16_t)(sclk_table->entries[i].sclk_offset) / 100);
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}
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result = polaris10_read_smc_sram_dword(smumgr,
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result = smu7_read_smc_sram_dword(smumgr,
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SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsMeanNSigma),
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&tmp, SMC_RAM_END);
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polaris10_copy_bytes_to_smc(smumgr,
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smu7_copy_bytes_to_smc(smumgr,
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tmp,
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(uint8_t *)&AVFS_meanNsigma,
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sizeof(AVFS_meanNsigma_t),
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SMC_RAM_END);
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result = polaris10_read_smc_sram_dword(smumgr,
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result = smu7_read_smc_sram_dword(smumgr,
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SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsSclkOffsetTable),
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&tmp, SMC_RAM_END);
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polaris10_copy_bytes_to_smc(smumgr,
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smu7_copy_bytes_to_smc(smumgr,
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tmp,
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(uint8_t *)&AVFS_SclkOffset,
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sizeof(AVFS_Sclk_Offset_t),
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@ -1578,8 +1579,8 @@ static int polaris10_init_arb_table_index(struct pp_smumgr *smumgr)
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* In reality this field should not be in that structure
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* but in a soft register.
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*/
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result = polaris10_read_smc_sram_dword(smumgr,
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smu_data->arb_table_start, &tmp, SMC_RAM_END);
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result = smu7_read_smc_sram_dword(smumgr,
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smu_data->smu7_data.arb_table_start, &tmp, SMC_RAM_END);
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if (result)
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return result;
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@ -1587,8 +1588,8 @@ static int polaris10_init_arb_table_index(struct pp_smumgr *smumgr)
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tmp &= 0x00FFFFFF;
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tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
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return polaris10_write_smc_sram_dword(smumgr,
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smu_data->arb_table_start, tmp, SMC_RAM_END);
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return smu7_write_smc_sram_dword(smumgr,
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smu_data->smu7_data.arb_table_start, tmp, SMC_RAM_END);
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}
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static void polaris10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
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@ -1811,8 +1812,8 @@ int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
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CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
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/* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
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result = polaris10_copy_bytes_to_smc(hwmgr->smumgr,
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smu_data->dpm_table_start +
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result = smu7_copy_bytes_to_smc(hwmgr->smumgr,
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smu_data->smu7_data.dpm_table_start +
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offsetof(SMU74_Discrete_DpmTable, SystemFlags),
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(uint8_t *)&(table->SystemFlags),
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sizeof(SMU74_Discrete_DpmTable) - 3 * sizeof(SMU74_PIDController),
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@ -1884,7 +1885,7 @@ int polaris10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
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int res;
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uint64_t tmp64;
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if (smu_data->fan_table_start == 0) {
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if (smu_data->smu7_data.fan_table_start == 0) {
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phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_MicrocodeFanControl);
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return 0;
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@ -1950,7 +1951,7 @@ int polaris10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
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hwmgr->device, CGS_IND_REG__SMC,
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CG_MULT_THERMAL_CTRL, TEMP_SEL);
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res = polaris10_copy_bytes_to_smc(hwmgr->smumgr, smu_data->fan_table_start,
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res = smu7_copy_bytes_to_smc(hwmgr->smumgr, smu_data->smu7_data.fan_table_start,
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(uint8_t *)&fan_table, (uint32_t)sizeof(fan_table),
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SMC_RAM_END);
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@ -1986,7 +1987,7 @@ static int polaris10_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
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if (table_info->mm_dep_table->count > 0)
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smu_data->smc_state_table.UvdBootLevel =
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(uint8_t) (table_info->mm_dep_table->count - 1);
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mm_boot_level_offset = smu_data->dpm_table_start + offsetof(SMU74_Discrete_DpmTable,
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mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + offsetof(SMU74_Discrete_DpmTable,
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UvdBootLevel);
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mm_boot_level_offset /= 4;
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mm_boot_level_offset *= 4;
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@ -2021,7 +2022,7 @@ static int polaris10_update_vce_smc_table(struct pp_hwmgr *hwmgr)
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else
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smu_data->smc_state_table.VceBootLevel = 0;
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mm_boot_level_offset = smu_data->dpm_table_start +
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mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
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offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
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mm_boot_level_offset /= 4;
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mm_boot_level_offset *= 4;
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@ -2046,7 +2047,7 @@ static int polaris10_update_samu_smc_table(struct pp_hwmgr *hwmgr)
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smu_data->smc_state_table.SamuBootLevel = 0;
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mm_boot_level_offset = smu_data->dpm_table_start +
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mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
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offsetof(SMU74_Discrete_DpmTable, SamuBootLevel);
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mm_boot_level_offset /= 4;
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@ -2123,9 +2124,9 @@ int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
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CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
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result = polaris10_copy_bytes_to_smc(
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result = smu7_copy_bytes_to_smc(
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hwmgr->smumgr,
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smu_data->dpm_table_start +
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smu_data->smu7_data.dpm_table_start +
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offsetof(SMU74_Discrete_DpmTable,
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LowSclkInterruptThreshold),
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(uint8_t *)&low_sclk_interrupt_threshold,
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@ -2158,6 +2159,8 @@ uint32_t polaris10_get_offsetof(uint32_t type, uint32_t member)
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return offsetof(SMU74_SoftRegisters, PreVBlankGap);
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case VBlankTimeout:
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return offsetof(SMU74_SoftRegisters, VBlankTimeout);
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case UcodeLoadStatus:
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return offsetof(SMU74_SoftRegisters, UcodeLoadStatus);
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}
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case SMU_Discrete_DpmTable:
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switch (member) {
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@ -2215,55 +2218,55 @@ int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
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int result;
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bool error = false;
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result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
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result = smu7_read_smc_sram_dword(hwmgr->smumgr,
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SMU7_FIRMWARE_HEADER_LOCATION +
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offsetof(SMU74_Firmware_Header, DpmTable),
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&tmp, SMC_RAM_END);
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if (0 == result)
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smu_data->dpm_table_start = tmp;
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smu_data->smu7_data.dpm_table_start = tmp;
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error |= (0 != result);
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result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
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result = smu7_read_smc_sram_dword(hwmgr->smumgr,
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SMU7_FIRMWARE_HEADER_LOCATION +
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offsetof(SMU74_Firmware_Header, SoftRegisters),
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&tmp, SMC_RAM_END);
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if (!result)
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smu_data->soft_regs_start = tmp;
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smu_data->smu7_data.soft_regs_start = tmp;
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error |= (0 != result);
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result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
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result = smu7_read_smc_sram_dword(hwmgr->smumgr,
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SMU7_FIRMWARE_HEADER_LOCATION +
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offsetof(SMU74_Firmware_Header, mcRegisterTable),
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&tmp, SMC_RAM_END);
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if (!result)
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smu_data->mc_reg_table_start = tmp;
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smu_data->smu7_data.mc_reg_table_start = tmp;
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result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
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result = smu7_read_smc_sram_dword(hwmgr->smumgr,
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SMU7_FIRMWARE_HEADER_LOCATION +
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offsetof(SMU74_Firmware_Header, FanTable),
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&tmp, SMC_RAM_END);
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if (!result)
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smu_data->fan_table_start = tmp;
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smu_data->smu7_data.fan_table_start = tmp;
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error |= (0 != result);
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result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
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result = smu7_read_smc_sram_dword(hwmgr->smumgr,
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SMU7_FIRMWARE_HEADER_LOCATION +
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offsetof(SMU74_Firmware_Header, mcArbDramTimingTable),
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&tmp, SMC_RAM_END);
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if (!result)
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smu_data->arb_table_start = tmp;
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smu_data->smu7_data.arb_table_start = tmp;
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error |= (0 != result);
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result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
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result = smu7_read_smc_sram_dword(hwmgr->smumgr,
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SMU7_FIRMWARE_HEADER_LOCATION +
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offsetof(SMU74_Firmware_Header, Version),
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&tmp, SMC_RAM_END);
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@ -2281,4 +2284,4 @@ bool polaris10_is_dpm_running(struct pp_hwmgr *hwmgr)
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return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
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CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
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? true : false;
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}
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}
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@ -40,13 +40,7 @@
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#include "cgs_common.h"
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#include "polaris10_smc.h"
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#include "smu7_ppsmc.h"
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#define POLARIS10_SMC_SIZE 0x20000
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/* Microcode file is stored in this buffer */
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#define BUFFER_SIZE 80000
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#define MAX_STRING_SIZE 15
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#define BUFFER_SIZETWO 131072 /* 128 *1024 */
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#include "smu7_smumgr.h"
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#define PPPOLARIS10_TARGETACTIVITY_DFLT 50
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@ -66,569 +60,6 @@ static const SMU74_Discrete_GraphicsLevel avfs_graphics_level_polaris10[8] = {
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static const SMU74_Discrete_MemoryLevel avfs_memory_level_polaris10 = {
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0x100ea446, 0, 0x30750000, 0x01, 0x01, 0x01, 0x00, 0x00, 0x64, 0x00, 0x00, 0x1f00, 0x00, 0x00};
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/**
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* Set the address for reading/writing the SMC SRAM space.
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* @param smumgr the address of the powerplay hardware manager.
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* @param smcAddress the address in the SMC RAM to access.
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*/
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static int polaris10_set_smc_sram_address(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t limit)
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{
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PP_ASSERT_WITH_CODE((0 == (3 & smc_addr)), "SMC address must be 4 byte aligned.", return -EINVAL);
|
||||
PP_ASSERT_WITH_CODE((limit > (smc_addr + 3)), "SMC addr is beyond the SMC RAM area.", return -EINVAL);
|
||||
|
||||
cgs_write_register(smumgr->device, mmSMC_IND_INDEX_11, smc_addr);
|
||||
SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Copy bytes from SMC RAM space into driver memory.
|
||||
*
|
||||
* @param smumgr the address of the powerplay SMU manager.
|
||||
* @param smc_start_address the start address in the SMC RAM to copy bytes from
|
||||
* @param src the byte array to copy the bytes to.
|
||||
* @param byte_count the number of bytes to copy.
|
||||
*/
|
||||
int polaris10_copy_bytes_from_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address, uint32_t *dest, uint32_t byte_count, uint32_t limit)
|
||||
{
|
||||
uint32_t data;
|
||||
uint32_t addr;
|
||||
uint8_t *dest_byte;
|
||||
uint8_t i, data_byte[4] = {0};
|
||||
uint32_t *pdata = (uint32_t *)&data_byte;
|
||||
|
||||
PP_ASSERT_WITH_CODE((0 == (3 & smc_start_address)), "SMC address must be 4 byte aligned.", return -1;);
|
||||
PP_ASSERT_WITH_CODE((limit > (smc_start_address + byte_count)), "SMC address is beyond the SMC RAM area.", return -1);
|
||||
|
||||
addr = smc_start_address;
|
||||
|
||||
while (byte_count >= 4) {
|
||||
polaris10_read_smc_sram_dword(smumgr, addr, &data, limit);
|
||||
|
||||
*dest = PP_SMC_TO_HOST_UL(data);
|
||||
|
||||
dest += 1;
|
||||
byte_count -= 4;
|
||||
addr += 4;
|
||||
}
|
||||
|
||||
if (byte_count) {
|
||||
polaris10_read_smc_sram_dword(smumgr, addr, &data, limit);
|
||||
*pdata = PP_SMC_TO_HOST_UL(data);
|
||||
/* Cast dest into byte type in dest_byte. This way, we don't overflow if the allocated memory is not 4-byte aligned. */
|
||||
dest_byte = (uint8_t *)dest;
|
||||
for (i = 0; i < byte_count; i++)
|
||||
dest_byte[i] = data_byte[i];
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Copy bytes from an array into the SMC RAM space.
|
||||
*
|
||||
* @param pSmuMgr the address of the powerplay SMU manager.
|
||||
* @param smc_start_address the start address in the SMC RAM to copy bytes to.
|
||||
* @param src the byte array to copy the bytes from.
|
||||
* @param byte_count the number of bytes to copy.
|
||||
*/
|
||||
int polaris10_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address,
|
||||
const uint8_t *src, uint32_t byte_count, uint32_t limit)
|
||||
{
|
||||
int result;
|
||||
uint32_t data = 0;
|
||||
uint32_t original_data;
|
||||
uint32_t addr = 0;
|
||||
uint32_t extra_shift;
|
||||
|
||||
PP_ASSERT_WITH_CODE((0 == (3 & smc_start_address)), "SMC address must be 4 byte aligned.", return -1);
|
||||
PP_ASSERT_WITH_CODE((limit > (smc_start_address + byte_count)), "SMC address is beyond the SMC RAM area.", return -1);
|
||||
|
||||
addr = smc_start_address;
|
||||
|
||||
while (byte_count >= 4) {
|
||||
/* Bytes are written into the SMC addres space with the MSB first. */
|
||||
data = src[0] * 0x1000000 + src[1] * 0x10000 + src[2] * 0x100 + src[3];
|
||||
|
||||
result = polaris10_set_smc_sram_address(smumgr, addr, limit);
|
||||
|
||||
if (0 != result)
|
||||
return result;
|
||||
|
||||
cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, data);
|
||||
|
||||
src += 4;
|
||||
byte_count -= 4;
|
||||
addr += 4;
|
||||
}
|
||||
|
||||
if (0 != byte_count) {
|
||||
|
||||
data = 0;
|
||||
|
||||
result = polaris10_set_smc_sram_address(smumgr, addr, limit);
|
||||
|
||||
if (0 != result)
|
||||
return result;
|
||||
|
||||
|
||||
original_data = cgs_read_register(smumgr->device, mmSMC_IND_DATA_11);
|
||||
|
||||
extra_shift = 8 * (4 - byte_count);
|
||||
|
||||
while (byte_count > 0) {
|
||||
/* Bytes are written into the SMC addres space with the MSB first. */
|
||||
data = (0x100 * data) + *src++;
|
||||
byte_count--;
|
||||
}
|
||||
|
||||
data <<= extra_shift;
|
||||
|
||||
data |= (original_data & ~((~0UL) << extra_shift));
|
||||
|
||||
result = polaris10_set_smc_sram_address(smumgr, addr, limit);
|
||||
|
||||
if (0 != result)
|
||||
return result;
|
||||
|
||||
cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, data);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static int polaris10_program_jump_on_start(struct pp_smumgr *smumgr)
|
||||
{
|
||||
static const unsigned char data[4] = { 0xE0, 0x00, 0x80, 0x40 };
|
||||
|
||||
polaris10_copy_bytes_to_smc(smumgr, 0x0, data, 4, sizeof(data)+1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Return if the SMC is currently running.
|
||||
*
|
||||
* @param smumgr the address of the powerplay hardware manager.
|
||||
*/
|
||||
bool polaris10_is_smc_ram_running(struct pp_smumgr *smumgr)
|
||||
{
|
||||
return ((0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable))
|
||||
&& (0x20100 <= cgs_read_ind_register(smumgr->device, CGS_IND_REG__SMC, ixSMC_PC_C)));
|
||||
}
|
||||
|
||||
static bool polaris10_is_hw_avfs_present(struct pp_smumgr *smumgr)
|
||||
{
|
||||
uint32_t efuse;
|
||||
|
||||
efuse = cgs_read_ind_register(smumgr->device, CGS_IND_REG__SMC, ixSMU_EFUSE_0 + (49*4));
|
||||
efuse &= 0x00000001;
|
||||
if (efuse)
|
||||
return true;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
/**
|
||||
* Send a message to the SMC, and wait for its response.
|
||||
*
|
||||
* @param smumgr the address of the powerplay hardware manager.
|
||||
* @param msg the message to send.
|
||||
* @return The response that came from the SMC.
|
||||
*/
|
||||
int polaris10_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (!polaris10_is_smc_ram_running(smumgr))
|
||||
return -1;
|
||||
|
||||
|
||||
SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
|
||||
|
||||
ret = SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP);
|
||||
|
||||
if (ret != 1)
|
||||
printk("\n failed to send pre message %x ret is %d \n", msg, ret);
|
||||
|
||||
cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg);
|
||||
|
||||
SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
|
||||
|
||||
ret = SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP);
|
||||
|
||||
if (ret != 1)
|
||||
printk("\n failed to send message %x ret is %d \n", msg, ret);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* Send a message to the SMC, and do not wait for its response.
|
||||
*
|
||||
* @param smumgr the address of the powerplay hardware manager.
|
||||
* @param msg the message to send.
|
||||
* @return Always return 0.
|
||||
*/
|
||||
int polaris10_send_msg_to_smc_without_waiting(struct pp_smumgr *smumgr, uint16_t msg)
|
||||
{
|
||||
cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Send a message to the SMC with parameter
|
||||
*
|
||||
* @param smumgr: the address of the powerplay hardware manager.
|
||||
* @param msg: the message to send.
|
||||
* @param parameter: the parameter to send
|
||||
* @return The response that came from the SMC.
|
||||
*/
|
||||
int polaris10_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter)
|
||||
{
|
||||
if (!polaris10_is_smc_ram_running(smumgr)) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
|
||||
|
||||
cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, parameter);
|
||||
|
||||
return polaris10_send_msg_to_smc(smumgr, msg);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* Send a message to the SMC with parameter, do not wait for response
|
||||
*
|
||||
* @param smumgr: the address of the powerplay hardware manager.
|
||||
* @param msg: the message to send.
|
||||
* @param parameter: the parameter to send
|
||||
* @return The response that came from the SMC.
|
||||
*/
|
||||
int polaris10_send_msg_to_smc_with_parameter_without_waiting(struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter)
|
||||
{
|
||||
cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, parameter);
|
||||
|
||||
return polaris10_send_msg_to_smc_without_waiting(smumgr, msg);
|
||||
}
|
||||
|
||||
int polaris10_send_msg_to_smc_offset(struct pp_smumgr *smumgr)
|
||||
{
|
||||
cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, 0x20000);
|
||||
|
||||
cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, PPSMC_MSG_Test);
|
||||
|
||||
SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
|
||||
|
||||
if (1 != SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP))
|
||||
printk("Failed to send Message.\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Wait until the SMC is doing nithing. Doing nothing means that the SMC is either turned off or it is sitting on the STOP instruction.
|
||||
*
|
||||
* @param smumgr the address of the powerplay hardware manager.
|
||||
* @param msg the message to send.
|
||||
* @return The response that came from the SMC.
|
||||
*/
|
||||
int polaris10_wait_for_smc_inactive(struct pp_smumgr *smumgr)
|
||||
{
|
||||
/* If the SMC is not even on it qualifies as inactive. */
|
||||
if (!polaris10_is_smc_ram_running(smumgr))
|
||||
return -1;
|
||||
|
||||
SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, SMC_SYSCON_CLOCK_CNTL_0, cken, 0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* Upload the SMC firmware to the SMC microcontroller.
|
||||
*
|
||||
* @param smumgr the address of the powerplay hardware manager.
|
||||
* @param pFirmware the data structure containing the various sections of the firmware.
|
||||
*/
|
||||
static int polaris10_upload_smc_firmware_data(struct pp_smumgr *smumgr, uint32_t length, uint32_t *src, uint32_t limit)
|
||||
{
|
||||
uint32_t byte_count = length;
|
||||
|
||||
PP_ASSERT_WITH_CODE((limit >= byte_count), "SMC address is beyond the SMC RAM area.", return -1);
|
||||
|
||||
cgs_write_register(smumgr->device, mmSMC_IND_INDEX_11, 0x20000);
|
||||
SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 1);
|
||||
|
||||
for (; byte_count >= 4; byte_count -= 4)
|
||||
cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, *src++);
|
||||
|
||||
SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0);
|
||||
|
||||
PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be dividable by 4.", return -1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static enum cgs_ucode_id polaris10_convert_fw_type_to_cgs(uint32_t fw_type)
|
||||
{
|
||||
enum cgs_ucode_id result = CGS_UCODE_ID_MAXIMUM;
|
||||
|
||||
switch (fw_type) {
|
||||
case UCODE_ID_SMU:
|
||||
result = CGS_UCODE_ID_SMU;
|
||||
break;
|
||||
case UCODE_ID_SMU_SK:
|
||||
result = CGS_UCODE_ID_SMU_SK;
|
||||
break;
|
||||
case UCODE_ID_SDMA0:
|
||||
result = CGS_UCODE_ID_SDMA0;
|
||||
break;
|
||||
case UCODE_ID_SDMA1:
|
||||
result = CGS_UCODE_ID_SDMA1;
|
||||
break;
|
||||
case UCODE_ID_CP_CE:
|
||||
result = CGS_UCODE_ID_CP_CE;
|
||||
break;
|
||||
case UCODE_ID_CP_PFP:
|
||||
result = CGS_UCODE_ID_CP_PFP;
|
||||
break;
|
||||
case UCODE_ID_CP_ME:
|
||||
result = CGS_UCODE_ID_CP_ME;
|
||||
break;
|
||||
case UCODE_ID_CP_MEC:
|
||||
result = CGS_UCODE_ID_CP_MEC;
|
||||
break;
|
||||
case UCODE_ID_CP_MEC_JT1:
|
||||
result = CGS_UCODE_ID_CP_MEC_JT1;
|
||||
break;
|
||||
case UCODE_ID_CP_MEC_JT2:
|
||||
result = CGS_UCODE_ID_CP_MEC_JT2;
|
||||
break;
|
||||
case UCODE_ID_RLC_G:
|
||||
result = CGS_UCODE_ID_RLC_G;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
static int polaris10_upload_smu_firmware_image(struct pp_smumgr *smumgr)
|
||||
{
|
||||
int result = 0;
|
||||
struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
|
||||
|
||||
struct cgs_firmware_info info = {0};
|
||||
|
||||
if (smu_data->security_hard_key == 1)
|
||||
cgs_get_firmware_info(smumgr->device,
|
||||
polaris10_convert_fw_type_to_cgs(UCODE_ID_SMU), &info);
|
||||
else
|
||||
cgs_get_firmware_info(smumgr->device,
|
||||
polaris10_convert_fw_type_to_cgs(UCODE_ID_SMU_SK), &info);
|
||||
|
||||
/* TO DO cgs_init_samu_load_smu(smumgr->device, (uint32_t *)info.kptr, info.image_size, smu_data->post_initial_boot);*/
|
||||
result = polaris10_upload_smc_firmware_data(smumgr, info.image_size, (uint32_t *)info.kptr, POLARIS10_SMC_SIZE);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
/**
|
||||
* Read a 32bit value from the SMC SRAM space.
|
||||
* ALL PARAMETERS ARE IN HOST BYTE ORDER.
|
||||
* @param smumgr the address of the powerplay hardware manager.
|
||||
* @param smcAddress the address in the SMC RAM to access.
|
||||
* @param value and output parameter for the data read from the SMC SRAM.
|
||||
*/
|
||||
int polaris10_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t *value, uint32_t limit)
|
||||
{
|
||||
int result;
|
||||
|
||||
result = polaris10_set_smc_sram_address(smumgr, smc_addr, limit);
|
||||
|
||||
if (result)
|
||||
return result;
|
||||
|
||||
*value = cgs_read_register(smumgr->device, mmSMC_IND_DATA_11);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Write a 32bit value to the SMC SRAM space.
|
||||
* ALL PARAMETERS ARE IN HOST BYTE ORDER.
|
||||
* @param smumgr the address of the powerplay hardware manager.
|
||||
* @param smc_addr the address in the SMC RAM to access.
|
||||
* @param value to write to the SMC SRAM.
|
||||
*/
|
||||
int polaris10_write_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t value, uint32_t limit)
|
||||
{
|
||||
int result;
|
||||
|
||||
result = polaris10_set_smc_sram_address(smumgr, smc_addr, limit);
|
||||
|
||||
if (result)
|
||||
return result;
|
||||
|
||||
cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, value);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
int polaris10_smu_fini(struct pp_smumgr *smumgr)
|
||||
{
|
||||
if (smumgr->backend) {
|
||||
kfree(smumgr->backend);
|
||||
smumgr->backend = NULL;
|
||||
}
|
||||
cgs_rel_firmware(smumgr->device, CGS_UCODE_ID_SMU);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Convert the firmware type to SMU type mask. For MEC, we need to check all MEC related type */
|
||||
static uint32_t polaris10_get_mask_for_firmware_type(uint32_t fw_type)
|
||||
{
|
||||
uint32_t result = 0;
|
||||
|
||||
switch (fw_type) {
|
||||
case UCODE_ID_SDMA0:
|
||||
result = UCODE_ID_SDMA0_MASK;
|
||||
break;
|
||||
case UCODE_ID_SDMA1:
|
||||
result = UCODE_ID_SDMA1_MASK;
|
||||
break;
|
||||
case UCODE_ID_CP_CE:
|
||||
result = UCODE_ID_CP_CE_MASK;
|
||||
break;
|
||||
case UCODE_ID_CP_PFP:
|
||||
result = UCODE_ID_CP_PFP_MASK;
|
||||
break;
|
||||
case UCODE_ID_CP_ME:
|
||||
result = UCODE_ID_CP_ME_MASK;
|
||||
break;
|
||||
case UCODE_ID_CP_MEC_JT1:
|
||||
case UCODE_ID_CP_MEC_JT2:
|
||||
result = UCODE_ID_CP_MEC_MASK;
|
||||
break;
|
||||
case UCODE_ID_RLC_G:
|
||||
result = UCODE_ID_RLC_G_MASK;
|
||||
break;
|
||||
default:
|
||||
printk("UCode type is out of range! \n");
|
||||
result = 0;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
/* Populate one firmware image to the data structure */
|
||||
|
||||
static int polaris10_populate_single_firmware_entry(struct pp_smumgr *smumgr,
|
||||
uint32_t fw_type,
|
||||
struct SMU_Entry *entry)
|
||||
{
|
||||
int result = 0;
|
||||
struct cgs_firmware_info info = {0};
|
||||
|
||||
result = cgs_get_firmware_info(smumgr->device,
|
||||
polaris10_convert_fw_type_to_cgs(fw_type),
|
||||
&info);
|
||||
|
||||
if (!result) {
|
||||
entry->version = info.version;
|
||||
entry->id = (uint16_t)fw_type;
|
||||
entry->image_addr_high = smu_upper_32_bits(info.mc_addr);
|
||||
entry->image_addr_low = smu_lower_32_bits(info.mc_addr);
|
||||
entry->meta_data_addr_high = 0;
|
||||
entry->meta_data_addr_low = 0;
|
||||
entry->data_size_byte = info.image_size;
|
||||
entry->num_register_entries = 0;
|
||||
}
|
||||
|
||||
if (fw_type == UCODE_ID_RLC_G)
|
||||
entry->flags = 1;
|
||||
else
|
||||
entry->flags = 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int polaris10_request_smu_load_fw(struct pp_smumgr *smumgr)
|
||||
{
|
||||
struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
|
||||
uint32_t fw_to_load;
|
||||
|
||||
int result = 0;
|
||||
struct SMU_DRAMData_TOC *toc;
|
||||
|
||||
if (!smumgr->reload_fw) {
|
||||
printk(KERN_INFO "[ powerplay ] skip reloading...\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (smu_data->soft_regs_start)
|
||||
cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
|
||||
smu_data->soft_regs_start + offsetof(SMU74_SoftRegisters, UcodeLoadStatus),
|
||||
0x0);
|
||||
|
||||
polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_SMU_DRAM_ADDR_HI, smu_data->smu_buffer.mc_addr_high);
|
||||
polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_SMU_DRAM_ADDR_LO, smu_data->smu_buffer.mc_addr_low);
|
||||
|
||||
toc = (struct SMU_DRAMData_TOC *)smu_data->header;
|
||||
toc->num_entries = 0;
|
||||
toc->structure_version = 1;
|
||||
|
||||
PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_RLC_G, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
|
||||
PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_CE, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
|
||||
PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_PFP, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
|
||||
PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_ME, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
|
||||
PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_MEC, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
|
||||
PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_MEC_JT1, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
|
||||
PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_MEC_JT2, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
|
||||
PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_SDMA0, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
|
||||
PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_SDMA1, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
|
||||
|
||||
polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_DRV_DRAM_ADDR_HI, smu_data->header_buffer.mc_addr_high);
|
||||
polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_DRV_DRAM_ADDR_LO, smu_data->header_buffer.mc_addr_low);
|
||||
|
||||
fw_to_load = UCODE_ID_RLC_G_MASK
|
||||
+ UCODE_ID_SDMA0_MASK
|
||||
+ UCODE_ID_SDMA1_MASK
|
||||
+ UCODE_ID_CP_CE_MASK
|
||||
+ UCODE_ID_CP_ME_MASK
|
||||
+ UCODE_ID_CP_PFP_MASK
|
||||
+ UCODE_ID_CP_MEC_MASK;
|
||||
|
||||
if (polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_LoadUcodes, fw_to_load))
|
||||
printk(KERN_ERR "Fail to Request SMU Load uCode");
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
/* Check if the FW has been loaded, SMU will not return if loading has not finished. */
|
||||
static int polaris10_check_fw_load_finish(struct pp_smumgr *smumgr, uint32_t fw_type)
|
||||
{
|
||||
struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
|
||||
uint32_t fw_mask = polaris10_get_mask_for_firmware_type(fw_type);
|
||||
uint32_t ret;
|
||||
/* Check SOFT_REGISTERS_TABLE_28.UcodeLoadStatus */
|
||||
ret = smum_wait_on_indirect_register(smumgr, mmSMC_IND_INDEX_11,
|
||||
smu_data->soft_regs_start + offsetof(SMU74_SoftRegisters, UcodeLoadStatus),
|
||||
fw_mask, fw_mask);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int polaris10_reload_firmware(struct pp_smumgr *smumgr)
|
||||
{
|
||||
return smumgr->smumgr_funcs->start_smu(smumgr);
|
||||
}
|
||||
|
||||
static int polaris10_setup_pwr_virus(struct pp_smumgr *smumgr)
|
||||
{
|
||||
|
|
@ -670,7 +101,7 @@ static int polaris10_perform_btc(struct pp_smumgr *smumgr)
|
|||
struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
|
||||
|
||||
if (0 != smu_data->avfs.avfs_btc_param) {
|
||||
if (0 != polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_PerformBtc, smu_data->avfs.avfs_btc_param)) {
|
||||
if (0 != smu7_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_PerformBtc, smu_data->avfs.avfs_btc_param)) {
|
||||
printk("[AVFS][SmuPolaris10_PerformBtc] PerformBTC SMU msg failed");
|
||||
result = -1;
|
||||
}
|
||||
|
|
@ -698,7 +129,7 @@ int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr)
|
|||
graphics_level_size = sizeof(avfs_graphics_level_polaris10);
|
||||
u16_boot_mvdd = PP_HOST_TO_SMC_US(1300 * VOLTAGE_SCALE);
|
||||
|
||||
PP_ASSERT_WITH_CODE(0 == polaris10_read_smc_sram_dword(smumgr,
|
||||
PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(smumgr,
|
||||
SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, DpmTable),
|
||||
&dpm_table_start, 0x40000),
|
||||
"[AVFS][Polaris10_SetupGfxLvlStruct] SMU could not communicate starting address of DPM table",
|
||||
|
|
@ -709,14 +140,14 @@ int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr)
|
|||
|
||||
vr_config_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, VRConfig);
|
||||
|
||||
PP_ASSERT_WITH_CODE(0 == polaris10_copy_bytes_to_smc(smumgr, vr_config_address,
|
||||
PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, vr_config_address,
|
||||
(uint8_t *)&vr_config, sizeof(uint32_t), 0x40000),
|
||||
"[AVFS][Polaris10_SetupGfxLvlStruct] Problems copying VRConfig value over to SMC",
|
||||
return -1);
|
||||
|
||||
graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
|
||||
|
||||
PP_ASSERT_WITH_CODE(0 == polaris10_copy_bytes_to_smc(smumgr, graphics_level_address,
|
||||
PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, graphics_level_address,
|
||||
(uint8_t *)(&avfs_graphics_level_polaris10),
|
||||
graphics_level_size, 0x40000),
|
||||
"[AVFS][Polaris10_SetupGfxLvlStruct] Copying of SCLK DPM table failed!",
|
||||
|
|
@ -724,7 +155,7 @@ int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr)
|
|||
|
||||
graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
|
||||
|
||||
PP_ASSERT_WITH_CODE(0 == polaris10_copy_bytes_to_smc(smumgr, graphics_level_address,
|
||||
PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, graphics_level_address,
|
||||
(uint8_t *)(&avfs_memory_level_polaris10), sizeof(avfs_memory_level_polaris10), 0x40000),
|
||||
"[AVFS][Polaris10_SetupGfxLvlStruct] Copying of MCLK DPM table failed!",
|
||||
return -1);
|
||||
|
|
@ -733,7 +164,7 @@ int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr)
|
|||
|
||||
graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, BootMVdd);
|
||||
|
||||
PP_ASSERT_WITH_CODE(0 == polaris10_copy_bytes_to_smc(smumgr, graphics_level_address,
|
||||
PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, graphics_level_address,
|
||||
(uint8_t *)(&u16_boot_mvdd), sizeof(u16_boot_mvdd), 0x40000),
|
||||
"[AVFS][Polaris10_SetupGfxLvlStruct] Copying of DPM table failed!",
|
||||
return -1);
|
||||
|
|
@ -794,7 +225,7 @@ static int polaris10_start_smu_in_protection_mode(struct pp_smumgr *smumgr)
|
|||
SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
|
||||
SMC_SYSCON_RESET_CNTL, rst_reg, 1);
|
||||
|
||||
result = polaris10_upload_smu_firmware_image(smumgr);
|
||||
result = smu7_upload_smu_firmware_image(smumgr);
|
||||
if (result != 0)
|
||||
return result;
|
||||
|
||||
|
|
@ -813,7 +244,7 @@ static int polaris10_start_smu_in_protection_mode(struct pp_smumgr *smumgr)
|
|||
|
||||
|
||||
/* Call Test SMU message with 0x20000 offset to trigger SMU start */
|
||||
polaris10_send_msg_to_smc_offset(smumgr);
|
||||
smu7_send_msg_to_smc_offset(smumgr);
|
||||
|
||||
/* Wait done bit to be set */
|
||||
/* Check pass/failed indicator */
|
||||
|
|
@ -854,12 +285,12 @@ static int polaris10_start_smu_in_non_protection_mode(struct pp_smumgr *smumgr)
|
|||
SMC_SYSCON_RESET_CNTL,
|
||||
rst_reg, 1);
|
||||
|
||||
result = polaris10_upload_smu_firmware_image(smumgr);
|
||||
result = smu7_upload_smu_firmware_image(smumgr);
|
||||
if (result != 0)
|
||||
return result;
|
||||
|
||||
/* Set smc instruct start point at 0x0 */
|
||||
polaris10_program_jump_on_start(smumgr);
|
||||
smu7_program_jump_on_start(smumgr);
|
||||
|
||||
SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
|
||||
SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
|
||||
|
|
@ -882,10 +313,10 @@ static int polaris10_start_smu(struct pp_smumgr *smumgr)
|
|||
bool SMU_VFT_INTACT;
|
||||
|
||||
/* Only start SMC if SMC RAM is not running */
|
||||
if (!polaris10_is_smc_ram_running(smumgr)) {
|
||||
if (!smu7_is_smc_ram_running(smumgr)) {
|
||||
SMU_VFT_INTACT = false;
|
||||
smu_data->protected_mode = (uint8_t) (SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE));
|
||||
smu_data->security_hard_key = (uint8_t) (SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL));
|
||||
smu_data->smu7_data.security_hard_key = (uint8_t) (SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL));
|
||||
|
||||
/* Check if SMU is running in protected mode */
|
||||
if (smu_data->protected_mode == 0) {
|
||||
|
|
@ -895,7 +326,7 @@ static int polaris10_start_smu(struct pp_smumgr *smumgr)
|
|||
|
||||
/* If failed, try with different security Key. */
|
||||
if (result != 0) {
|
||||
smu_data->security_hard_key ^= 1;
|
||||
smu_data->smu7_data.security_hard_key ^= 1;
|
||||
result = polaris10_start_smu_in_protection_mode(smumgr);
|
||||
}
|
||||
}
|
||||
|
|
@ -907,71 +338,35 @@ static int polaris10_start_smu(struct pp_smumgr *smumgr)
|
|||
} else
|
||||
SMU_VFT_INTACT = true; /*Driver went offline but SMU was still alive and contains the VFT table */
|
||||
|
||||
smu_data->post_initial_boot = true;
|
||||
polaris10_avfs_event_mgr(smumgr, SMU_VFT_INTACT);
|
||||
/* Setup SoftRegsStart here for register lookup in case DummyBackEnd is used and ProcessFirmwareHeader is not executed */
|
||||
polaris10_read_smc_sram_dword(smumgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, SoftRegisters),
|
||||
&(smu_data->soft_regs_start), 0x40000);
|
||||
smu7_read_smc_sram_dword(smumgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, SoftRegisters),
|
||||
&(smu_data->smu7_data.soft_regs_start), 0x40000);
|
||||
|
||||
result = polaris10_request_smu_load_fw(smumgr);
|
||||
result = smu7_request_smu_load_fw(smumgr);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
static bool polaris10_is_hw_avfs_present(struct pp_smumgr *smumgr)
|
||||
{
|
||||
uint32_t efuse;
|
||||
|
||||
efuse = cgs_read_ind_register(smumgr->device, CGS_IND_REG__SMC, ixSMU_EFUSE_0 + (49*4));
|
||||
efuse &= 0x00000001;
|
||||
if (efuse)
|
||||
return true;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static int polaris10_smu_init(struct pp_smumgr *smumgr)
|
||||
{
|
||||
struct polaris10_smumgr *smu_data;
|
||||
uint8_t *internal_buf;
|
||||
uint64_t mc_addr = 0;
|
||||
struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
|
||||
int i;
|
||||
|
||||
/* Allocate memory for backend private data */
|
||||
smu_data = (struct polaris10_smumgr *)(smumgr->backend);
|
||||
smu_data->header_buffer.data_size =
|
||||
((sizeof(struct SMU_DRAMData_TOC) / 4096) + 1) * 4096;
|
||||
smu_data->smu_buffer.data_size = 200*4096;
|
||||
smu_data->avfs.avfs_btc_status = AVFS_BTC_NOTSUPPORTED;
|
||||
/* Allocate FW image data structure and header buffer and
|
||||
* send the header buffer address to SMU */
|
||||
smu_allocate_memory(smumgr->device,
|
||||
smu_data->header_buffer.data_size,
|
||||
CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
|
||||
PAGE_SIZE,
|
||||
&mc_addr,
|
||||
&smu_data->header_buffer.kaddr,
|
||||
&smu_data->header_buffer.handle);
|
||||
|
||||
smu_data->header = smu_data->header_buffer.kaddr;
|
||||
smu_data->header_buffer.mc_addr_high = smu_upper_32_bits(mc_addr);
|
||||
smu_data->header_buffer.mc_addr_low = smu_lower_32_bits(mc_addr);
|
||||
|
||||
PP_ASSERT_WITH_CODE((NULL != smu_data->header),
|
||||
"Out of memory.",
|
||||
kfree(smumgr->backend);
|
||||
cgs_free_gpu_mem(smumgr->device,
|
||||
(cgs_handle_t)smu_data->header_buffer.handle);
|
||||
return -1);
|
||||
|
||||
/* Allocate buffer for SMU internal buffer and send the address to SMU.
|
||||
* Iceland SMU does not need internal buffer.*/
|
||||
smu_allocate_memory(smumgr->device,
|
||||
smu_data->smu_buffer.data_size,
|
||||
CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
|
||||
PAGE_SIZE,
|
||||
&mc_addr,
|
||||
&smu_data->smu_buffer.kaddr,
|
||||
&smu_data->smu_buffer.handle);
|
||||
|
||||
internal_buf = smu_data->smu_buffer.kaddr;
|
||||
smu_data->smu_buffer.mc_addr_high = smu_upper_32_bits(mc_addr);
|
||||
smu_data->smu_buffer.mc_addr_low = smu_lower_32_bits(mc_addr);
|
||||
|
||||
PP_ASSERT_WITH_CODE((NULL != internal_buf),
|
||||
"Out of memory.",
|
||||
kfree(smumgr->backend);
|
||||
cgs_free_gpu_mem(smumgr->device,
|
||||
(cgs_handle_t)smu_data->smu_buffer.handle);
|
||||
return -1;);
|
||||
if (smu7_init(smumgr))
|
||||
return -EINVAL;
|
||||
|
||||
if (polaris10_is_hw_avfs_present(smumgr))
|
||||
smu_data->avfs.avfs_btc_status = AVFS_BTC_BOOT;
|
||||
|
|
@ -986,13 +381,13 @@ static int polaris10_smu_init(struct pp_smumgr *smumgr)
|
|||
|
||||
static const struct pp_smumgr_func polaris10_smu_funcs = {
|
||||
.smu_init = polaris10_smu_init,
|
||||
.smu_fini = polaris10_smu_fini,
|
||||
.smu_fini = smu7_smu_fini,
|
||||
.start_smu = polaris10_start_smu,
|
||||
.check_fw_load_finish = polaris10_check_fw_load_finish,
|
||||
.request_smu_load_fw = polaris10_reload_firmware,
|
||||
.check_fw_load_finish = smu7_check_fw_load_finish,
|
||||
.request_smu_load_fw = smu7_reload_firmware,
|
||||
.request_smu_load_specific_fw = NULL,
|
||||
.send_msg_to_smc = polaris10_send_msg_to_smc,
|
||||
.send_msg_to_smc_with_parameter = polaris10_send_msg_to_smc_with_parameter,
|
||||
.send_msg_to_smc = smu7_send_msg_to_smc,
|
||||
.send_msg_to_smc_with_parameter = smu7_send_msg_to_smc_with_parameter,
|
||||
.download_pptable_settings = NULL,
|
||||
.upload_pptable_settings = NULL,
|
||||
.update_smc_table = polaris10_update_smc_table,
|
||||
|
|
@ -1015,7 +410,7 @@ int polaris10_smum_init(struct pp_smumgr *smumgr)
|
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polaris10_smu = kzalloc(sizeof(struct polaris10_smumgr), GFP_KERNEL);
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||||
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||||
if (polaris10_smu == NULL)
|
||||
return -1;
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return -EINVAL;
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||||
|
||||
smumgr->backend = polaris10_smu;
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||||
smumgr->smumgr_funcs = &polaris10_smu_funcs;
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||||
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@ -28,7 +28,7 @@
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#include <pp_endian.h>
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||||
#include "smu74.h"
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||||
#include "smu74_discrete.h"
|
||||
|
||||
#include "smu7_smumgr.h"
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||||
|
||||
#define SMC_RAM_END 0x40000
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||||
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||||
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@ -51,13 +51,7 @@ struct polaris10_pt_defaults {
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uint16_t BAPMTI_RC[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS];
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||||
};
|
||||
|
||||
struct polaris10_buffer_entry {
|
||||
uint32_t data_size;
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||||
uint32_t mc_addr_low;
|
||||
uint32_t mc_addr_high;
|
||||
void *kaddr;
|
||||
unsigned long handle;
|
||||
};
|
||||
|
||||
|
||||
struct polaris10_range_table {
|
||||
uint32_t trans_lower_frequency; /* in 10khz */
|
||||
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|
@ -65,24 +59,8 @@ struct polaris10_range_table {
|
|||
};
|
||||
|
||||
struct polaris10_smumgr {
|
||||
uint8_t *header;
|
||||
uint8_t *mec_image;
|
||||
struct polaris10_buffer_entry smu_buffer;
|
||||
struct polaris10_buffer_entry header_buffer;
|
||||
|
||||
uint32_t soft_regs_start;
|
||||
uint32_t dpm_table_start;
|
||||
uint32_t mc_reg_table_start;
|
||||
uint32_t fan_table_start;
|
||||
uint32_t arb_table_start;
|
||||
|
||||
uint8_t *read_rrm_straps;
|
||||
uint32_t read_drm_straps_mc_address_high;
|
||||
uint32_t read_drm_straps_mc_address_low;
|
||||
uint32_t acpi_optimization;
|
||||
bool post_initial_boot;
|
||||
struct smu7_smumgr smu7_data;
|
||||
uint8_t protected_mode;
|
||||
uint8_t security_hard_key;
|
||||
struct polaris10_avfs avfs;
|
||||
SMU74_Discrete_DpmTable smc_state_table;
|
||||
struct SMU74_Discrete_Ulv ulv_setting;
|
||||
|
|
@ -94,10 +72,4 @@ struct polaris10_smumgr {
|
|||
};
|
||||
|
||||
|
||||
int polaris10_smum_init(struct pp_smumgr *smumgr);
|
||||
int polaris10_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t *value, uint32_t limit);
|
||||
int polaris10_write_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t value, uint32_t limit);
|
||||
int polaris10_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address,
|
||||
const uint8_t *src, uint32_t byte_count, uint32_t limit);
|
||||
|
||||
#endif
|
||||
|
|
|
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Reference in New Issue