mirror of https://gitee.com/openkylin/linux.git
ARM: arm-soc: SoC updates for 3.8
This contains the bulk of new SoC development for this merge window. Two new platforms have been added, the sunxi platforms (Allwinner A1x SoCs) by Maxime Ripard, and a generic Broadcom platform for a new series of ARMv7 platforms from them, where the hope is that we can keep the platform code generic enough to have them all share one mach directory. The new Broadcom platform is contributed by Christian Daudt. Highbank has grown support for Calxeda's next generation of hardware, ECX-2000. clps711x has seen a lot of cleanup from Alexander Shiyan, and he's also taken on maintainership of the platform. Beyond this there has been a bunch of work from a number of people on converting more platforms to IRQ domains, pinctrl conversion, cleanup and general feature enablement across most of the active platforms. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJQyLCjAAoJEIwa5zzehBx3AdQP/R+L3+EQMjiEWt/p7g/ql5Em 0SnP92CcGzrjgLTg9z1FeOazfOsGnkZAYUlDRkqfKobH3VqkhYFFtt1/0x0KMahm xcowHgMBOyimFdWT9vLK3J8U6DLui5XrEG9LGH2VL+lqmfjIyP/OOF3mVc0/+pV9 WTLAsYswdBRSeiNuF43kqlfrOwF6xsPLgiNMlc82w6BzHqoHu6dOif5M9MqWaApS V74DPmwLD371Tyit6aHqt3JOqpgiPSHlmxkzomK+5idcW3Pa7HnzzFYmx85dk/eN J2siqIkoOu7tEfjIbNZTL2MYoX4tUUKv4qZZ3IOl3YSWaV3P5ilMApF01XVrkk8E DWOMhzte9hC7L90W+/kCPLF1VyeAhCem2KQWUitO71fKur3r+3ZaUokNVvWzkJIL 7aduxAJOV2hfLgEqbjbjF3o4S8p63OV3kzivFJM1And15zDJo4+qqOh67+bPo4jj +R4du+SqzXriw4i3tDLGVpdjDffk4D41tbLzgkWAtvGyoP45yeYfHAzAh0pDFPRv ASfZVmZ5PhwAUAkIMnpC2sjgmxMYff3SYqmDgnsqXES7rbDH/hG+teymtHFTyUQp m+f60DNotSMcMvkLdvruLSB4aeTiwbfOqPn/g+aXYUlPuNMq1fVWgN7EJKWkamK4 nRwaJmLwx1/ojcVbpy2G =YMKB -----END PGP SIGNATURE----- Merge tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC updates from Olof Johansson: "This contains the bulk of new SoC development for this merge window. Two new platforms have been added, the sunxi platforms (Allwinner A1x SoCs) by Maxime Ripard, and a generic Broadcom platform for a new series of ARMv7 platforms from them, where the hope is that we can keep the platform code generic enough to have them all share one mach directory. The new Broadcom platform is contributed by Christian Daudt. Highbank has grown support for Calxeda's next generation of hardware, ECX-2000. clps711x has seen a lot of cleanup from Alexander Shiyan, and he's also taken on maintainership of the platform. Beyond this there has been a bunch of work from a number of people on converting more platforms to IRQ domains, pinctrl conversion, cleanup and general feature enablement across most of the active platforms." Fix up trivial conflicts as per Olof. * tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (174 commits) mfd: vexpress-sysreg: Remove LEDs code irqchip: irq-sunxi: Add terminating entry for sunxi_irq_dt_ids clocksource: sunxi_timer: Add terminating entry for sunxi_timer_dt_ids irq: versatile: delete dangling variable ARM: sunxi: add missing include for mdelay() ARM: EXYNOS: Avoid early use of of_machine_is_compatible() ARM: dts: add node for PL330 MDMA1 controller for exynos4 ARM: EXYNOS: Add support for secondary CPU bring-up on Exynos4412 ARM: EXYNOS: add UART3 to DEBUG_LL ports ARM: S3C24XX: Add clkdev entry for camif-upll clock ARM: SAMSUNG: Add s3c24xx/s3c64xx CAMIF GPIO setup helpers ARM: sunxi: Add missing sun4i.dtsi file pinctrl: samsung: Do not initialise statics to 0 ARM i.MX6: remove gate_mask from pllv3 ARM i.MX6: Fix ethernet PLL clocks ARM i.MX6: rename PLLs according to datasheet ARM i.MX6: Add pwm support ARM i.MX51: Add pwm support ARM i.MX53: Add pwm support ARM: mx5: Replace clk_register_clkdev with clock DT lookup ...
This commit is contained in:
Linus Torvalds
commit
d027db132b
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@ -0,0 +1,19 @@
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ARM Allwinner SoCs
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==================
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This document lists all the ARM Allwinner SoCs that are currently
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supported in mainline by the Linux kernel. This document will also
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provide links to documentation and or datasheet for these SoCs.
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SunXi family
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------------
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Flavors:
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Allwinner A10 (sun4i)
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Datasheet : http://dl.linux-sunxi.org/A10/A10%20Datasheet%20-%20v1.21%20%282012-04-06%29.pdf
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Allwinner A13 (sun5i)
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Datasheet : http://dl.linux-sunxi.org/A13/A13%20Datasheet%20-%20v1.12%20%282012-03-29%29.pdf
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Core: Cortex A8
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Linux kernel mach directory: arch/arm/mach-sunxi
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@ -0,0 +1,9 @@
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Broadcom BCM11351 device tree bindings
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-------------------------------------------
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Boards with the bcm281xx SoC family (which includes bcm11130, bcm11140,
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bcm11351, bcm28145, bcm28155 SoCs) shall have the following properties:
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Required root node property:
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compatible = "bcm,bcm11351";
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@ -1,8 +1,15 @@
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Calxeda Highbank Platforms Device Tree Bindings
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Calxeda Platforms Device Tree Bindings
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-----------------------------------------------
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Boards with Calxeda Cortex-A9 based Highbank SOC shall have the following
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properties.
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Boards with Calxeda Cortex-A9 based ECX-1000 (Highbank) SOC shall have the
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following properties.
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Required root node properties:
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- compatible = "calxeda,highbank";
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Boards with Calxeda Cortex-A15 based ECX-2000 SOC shall have the following
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properties.
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Required root node properties:
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- compatible = "calxeda,ecx-2000";
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|
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@ -0,0 +1,50 @@
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ARM Versatile Express system registers
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--------------------------------------
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This is a system control registers block, providing multiple low level
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platform functions like board detection and identification, software
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interrupt generation, MMC and NOR Flash control etc.
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Required node properties:
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- compatible value : = "arm,vexpress,sysreg";
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- reg : physical base address and the size of the registers window
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- gpio-controller : specifies that the node is a GPIO controller
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- #gpio-cells : size of the GPIO specifier, should be 2:
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- first cell is the pseudo-GPIO line number:
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0 - MMC CARDIN
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1 - MMC WPROT
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2 - NOR FLASH WPn
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- second cell can take standard GPIO flags (currently ignored).
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Example:
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v2m_sysreg: sysreg@10000000 {
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compatible = "arm,vexpress-sysreg";
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reg = <0x10000000 0x1000>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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This block also can also act a bridge to the platform's configuration
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bus via "system control" interface, addressing devices with site number,
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position in the board stack, config controller, function and device
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numbers - see motherboard's TRM for more details.
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The node describing a config device must refer to the sysreg node via
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"arm,vexpress,config-bridge" phandle (can be also defined in the node's
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parent) and relies on the board topology properties - see main vexpress
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node documentation for more details. It must must also define the
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following property:
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- arm,vexpress-sysreg,func : must contain two cells:
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- first cell defines function number (eg. 1 for clock generator,
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2 for voltage regulators etc.)
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- device number (eg. osc 0, osc 1 etc.)
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Example:
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mcc {
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arm,vexpress,config-bridge = <&v2m_sysreg>;
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osc@0 {
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compatible = "arm,vexpress-osc";
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arm,vexpress-sysreg,func = <1 0>;
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};
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};
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@ -11,6 +11,10 @@ the motherboard file using a /include/ directive. As the motherboard
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can be initialized in one of two different configurations ("memory
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maps"), care must be taken to include the correct one.
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Root node
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---------
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Required properties in the root node:
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- compatible value:
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compatible = "arm,vexpress,<model>", "arm,vexpress";
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@ -45,6 +49,10 @@ Optional properties in the root node:
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- Coretile Express A9x4 (V2P-CA9) HBI-0225:
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arm,hbi = <0x225>;
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CPU nodes
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---------
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Top-level standard "cpus" node is required. It must contain a node
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with device_type = "cpu" property for every available core, eg.:
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|
|
@ -59,6 +67,52 @@ with device_type = "cpu" property for every available core, eg.:
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};
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};
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Configuration infrastructure
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----------------------------
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The platform has an elaborated configuration system, consisting of
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microcontrollers residing on the mother- and daughterboards known
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as Motherboard/Daughterboard Configuration Controller (MCC and DCC).
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The controllers are responsible for the platform initialization
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(reset generation, flash programming, FPGA bitfiles loading etc.)
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but also control clock generators, voltage regulators, gather
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environmental data like temperature, power consumption etc. Even
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the video output switch (FPGA) is controlled that way.
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Nodes describing devices controlled by this infrastructure should
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point at the bridge device node:
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- bridge phandle:
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arm,vexpress,config-bridge = <phandle>;
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This property can be also defined in a parent node (eg. for a DCC)
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and is effective for all children.
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|
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Platform topology
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-----------------
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As Versatile Express can be configured in number of physically
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different setups, the device tree should describe platform topology.
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Root node and main motherboard node must define the following
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property, describing physical location of the children nodes:
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- site number:
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arm,vexpress,site = <number>;
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where 0 means motherboard, 1 or 2 are daugtherboard sites,
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0xf means "master" site (site containing main CPU tile)
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- when daughterboards are stacked on one site, their position
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in the stack be be described with:
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arm,vexpress,position = <number>;
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- when describing tiles consisting more than one DCC, its number
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can be described with:
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arm,vexpress,dcc = <number>;
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Any of the numbers above defaults to zero if not defined in
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the node or any of its parent.
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Motherboard
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-----------
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The motherboard description file provides a single "motherboard" node
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using 2 address cells corresponding to the Static Memory Bus used
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between the motherboard and the tile. The first cell defines the Chip
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|
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@ -87,22 +141,30 @@ can be used to obtain required phandle in the tile's "aliases" node:
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- SP804 timers:
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v2m_timer01 and v2m_timer23
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|
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Current Linux implementation requires a "arm,v2m_timer" alias
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pointing at one of the motherboard's SP804 timers, if it is to be
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used as the system timer. This alias should be defined in the
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motherboard files.
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The tile description should define a "smb" node, describing the
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Static Memory Bus between the tile and motherboard. It must define
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the following properties:
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- "simple-bus" compatible value (to ensure creation of the children)
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compatible = "simple-bus";
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- mapping of the SMB CS/offset addresses into main address space:
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <...>;
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- interrupts mapping:
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 63>;
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interrupt-map = <...>;
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|
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The tile description must define "ranges", "interrupt-map-mask" and
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"interrupt-map" properties to translate the motherboard's address
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and interrupt space into one used by the tile's processor.
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||||
Abbreviated example:
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Example of a VE tile description (simplified)
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---------------------------------------------
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/dts-v1/;
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/ {
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model = "V2P-CA5s";
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arm,hbi = <0x225>;
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arm,vexpress,site = <0xf>;
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compatible = "arm,vexpress-v2p-ca5s", "arm,vexpress";
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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|
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@ -134,13 +196,29 @@ Abbreviated example:
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<0x2c000100 0x100>;
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};
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motherboard {
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dcc {
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compatible = "simple-bus";
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arm,vexpress,config-bridge = <&v2m_sysreg>;
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|
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osc@0 {
|
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compatible = "arm,vexpress-osc";
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};
|
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};
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smb {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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/* CS0 is visible at 0x08000000 */
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ranges = <0 0 0x08000000 0x04000000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 63>;
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/* Active high IRQ 0 is connected to GIC's SPI0 */
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interrupt-map = <0 0 0 &gic 0 0 4>;
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/include/ "vexpress-v2m-rs1.dtsi"
|
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};
|
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};
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|
||||
/include/ "vexpress-v2m-rs1.dtsi"
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|
|
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|||
|
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@ -0,0 +1,191 @@
|
|||
* Clock bindings for Freescale i.MX5
|
||||
|
||||
Required properties:
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||||
- compatible: Should be "fsl,<soc>-ccm" , where <soc> can be imx51 or imx53
|
||||
- reg: Address and length of the register set
|
||||
- interrupts: Should contain CCM interrupt
|
||||
- #clock-cells: Should be <1>
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|
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The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. The following is a full list of i.MX5
|
||||
clocks and IDs.
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||||
|
||||
Clock ID
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||||
---------------------------
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dummy 0
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||||
ckil 1
|
||||
osc 2
|
||||
ckih1 3
|
||||
ckih2 4
|
||||
ahb 5
|
||||
ipg 6
|
||||
axi_a 7
|
||||
axi_b 8
|
||||
uart_pred 9
|
||||
uart_root 10
|
||||
esdhc_a_pred 11
|
||||
esdhc_b_pred 12
|
||||
esdhc_c_s 13
|
||||
esdhc_d_s 14
|
||||
emi_sel 15
|
||||
emi_slow_podf 16
|
||||
nfc_podf 17
|
||||
ecspi_pred 18
|
||||
ecspi_podf 19
|
||||
usboh3_pred 20
|
||||
usboh3_podf 21
|
||||
usb_phy_pred 22
|
||||
usb_phy_podf 23
|
||||
cpu_podf 24
|
||||
di_pred 25
|
||||
tve_di 26
|
||||
tve_s 27
|
||||
uart1_ipg_gate 28
|
||||
uart1_per_gate 29
|
||||
uart2_ipg_gate 30
|
||||
uart2_per_gate 31
|
||||
uart3_ipg_gate 32
|
||||
uart3_per_gate 33
|
||||
i2c1_gate 34
|
||||
i2c2_gate 35
|
||||
gpt_ipg_gate 36
|
||||
pwm1_ipg_gate 37
|
||||
pwm1_hf_gate 38
|
||||
pwm2_ipg_gate 39
|
||||
pwm2_hf_gate 40
|
||||
gpt_hf_gate 41
|
||||
fec_gate 42
|
||||
usboh3_per_gate 43
|
||||
esdhc1_ipg_gate 44
|
||||
esdhc2_ipg_gate 45
|
||||
esdhc3_ipg_gate 46
|
||||
esdhc4_ipg_gate 47
|
||||
ssi1_ipg_gate 48
|
||||
ssi2_ipg_gate 49
|
||||
ssi3_ipg_gate 50
|
||||
ecspi1_ipg_gate 51
|
||||
ecspi1_per_gate 52
|
||||
ecspi2_ipg_gate 53
|
||||
ecspi2_per_gate 54
|
||||
cspi_ipg_gate 55
|
||||
sdma_gate 56
|
||||
emi_slow_gate 57
|
||||
ipu_s 58
|
||||
ipu_gate 59
|
||||
nfc_gate 60
|
||||
ipu_di1_gate 61
|
||||
vpu_s 62
|
||||
vpu_gate 63
|
||||
vpu_reference_gate 64
|
||||
uart4_ipg_gate 65
|
||||
uart4_per_gate 66
|
||||
uart5_ipg_gate 67
|
||||
uart5_per_gate 68
|
||||
tve_gate 69
|
||||
tve_pred 70
|
||||
esdhc1_per_gate 71
|
||||
esdhc2_per_gate 72
|
||||
esdhc3_per_gate 73
|
||||
esdhc4_per_gate 74
|
||||
usb_phy_gate 75
|
||||
hsi2c_gate 76
|
||||
mipi_hsc1_gate 77
|
||||
mipi_hsc2_gate 78
|
||||
mipi_esc_gate 79
|
||||
mipi_hsp_gate 80
|
||||
ldb_di1_div_3_5 81
|
||||
ldb_di1_div 82
|
||||
ldb_di0_div_3_5 83
|
||||
ldb_di0_div 84
|
||||
ldb_di1_gate 85
|
||||
can2_serial_gate 86
|
||||
can2_ipg_gate 87
|
||||
i2c3_gate 88
|
||||
lp_apm 89
|
||||
periph_apm 90
|
||||
main_bus 91
|
||||
ahb_max 92
|
||||
aips_tz1 93
|
||||
aips_tz2 94
|
||||
tmax1 95
|
||||
tmax2 96
|
||||
tmax3 97
|
||||
spba 98
|
||||
uart_sel 99
|
||||
esdhc_a_sel 100
|
||||
esdhc_b_sel 101
|
||||
esdhc_a_podf 102
|
||||
esdhc_b_podf 103
|
||||
ecspi_sel 104
|
||||
usboh3_sel 105
|
||||
usb_phy_sel 106
|
||||
iim_gate 107
|
||||
usboh3_gate 108
|
||||
emi_fast_gate 109
|
||||
ipu_di0_gate 110
|
||||
gpc_dvfs 111
|
||||
pll1_sw 112
|
||||
pll2_sw 113
|
||||
pll3_sw 114
|
||||
ipu_di0_sel 115
|
||||
ipu_di1_sel 116
|
||||
tve_ext_sel 117
|
||||
mx51_mipi 118
|
||||
pll4_sw 119
|
||||
ldb_di1_sel 120
|
||||
di_pll4_podf 121
|
||||
ldb_di0_sel 122
|
||||
ldb_di0_gate 123
|
||||
usb_phy1_gate 124
|
||||
usb_phy2_gate 125
|
||||
per_lp_apm 126
|
||||
per_pred1 127
|
||||
per_pred2 128
|
||||
per_podf 129
|
||||
per_root 130
|
||||
ssi_apm 131
|
||||
ssi1_root_sel 132
|
||||
ssi2_root_sel 133
|
||||
ssi3_root_sel 134
|
||||
ssi_ext1_sel 135
|
||||
ssi_ext2_sel 136
|
||||
ssi_ext1_com_sel 137
|
||||
ssi_ext2_com_sel 138
|
||||
ssi1_root_pred 139
|
||||
ssi1_root_podf 140
|
||||
ssi2_root_pred 141
|
||||
ssi2_root_podf 142
|
||||
ssi_ext1_pred 143
|
||||
ssi_ext1_podf 144
|
||||
ssi_ext2_pred 145
|
||||
ssi_ext2_podf 146
|
||||
ssi1_root_gate 147
|
||||
ssi2_root_gate 148
|
||||
ssi3_root_gate 149
|
||||
ssi_ext1_gate 150
|
||||
ssi_ext2_gate 151
|
||||
epit1_ipg_gate 152
|
||||
epit1_hf_gate 153
|
||||
epit2_ipg_gate 154
|
||||
epit2_hf_gate 155
|
||||
can_sel 156
|
||||
can1_serial_gate 157
|
||||
can1_ipg_gate 158
|
||||
|
||||
Examples (for mx53):
|
||||
|
||||
clks: ccm@53fd4000{
|
||||
compatible = "fsl,imx53-ccm";
|
||||
reg = <0x53fd4000 0x4000>;
|
||||
interrupts = <0 71 0x04 0 72 0x04>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
can1: can@53fc8000 {
|
||||
compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
|
||||
reg = <0x53fc8000 0x4000>;
|
||||
interrupts = <82>;
|
||||
clocks = <&clks 158>, <&clks 157>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -187,9 +187,9 @@ clocks and IDs.
|
|||
pll3_usb_otg 172
|
||||
pll4_audio 173
|
||||
pll5_video 174
|
||||
pll6_mlb 175
|
||||
pll8_mlb 175
|
||||
pll7_usb_host 176
|
||||
pll8_enet 177
|
||||
pll6_enet 177
|
||||
ssi1_ipg 178
|
||||
ssi2_ipg 179
|
||||
ssi3_ipg 180
|
||||
|
|
@ -198,6 +198,11 @@ clocks and IDs.
|
|||
usbphy2 183
|
||||
ldb_di0_div_3_5 184
|
||||
ldb_di1_div_3_5 185
|
||||
sata_ref 186
|
||||
sata_ref_100m 187
|
||||
pcie_ref 188
|
||||
pcie_ref_125m 189
|
||||
enet_ref 190
|
||||
|
||||
Examples:
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,104 @@
|
|||
Allwinner Sunxi Interrupt Controller
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : should be "allwinner,sunxi-ic"
|
||||
- reg : Specifies base physical address and size of the registers.
|
||||
- interrupt-controller : Identifies the node as an interrupt controller
|
||||
- #interrupt-cells : Specifies the number of cells needed to encode an
|
||||
interrupt source. The value shall be 1.
|
||||
|
||||
The interrupt sources are as follows:
|
||||
|
||||
0: ENMI
|
||||
1: UART0
|
||||
2: UART1
|
||||
3: UART2
|
||||
4: UART3
|
||||
5: IR0
|
||||
6: IR1
|
||||
7: I2C0
|
||||
8: I2C1
|
||||
9: I2C2
|
||||
10: SPI0
|
||||
11: SPI1
|
||||
12: SPI2
|
||||
13: SPDIF
|
||||
14: AC97
|
||||
15: TS
|
||||
16: I2S
|
||||
17: UART4
|
||||
18: UART5
|
||||
19: UART6
|
||||
20: UART7
|
||||
21: KEYPAD
|
||||
22: TIMER0
|
||||
23: TIMER1
|
||||
24: TIMER2
|
||||
25: TIMER3
|
||||
26: CAN
|
||||
27: DMA
|
||||
28: PIO
|
||||
29: TOUCH_PANEL
|
||||
30: AUDIO_CODEC
|
||||
31: LRADC
|
||||
32: SDMC0
|
||||
33: SDMC1
|
||||
34: SDMC2
|
||||
35: SDMC3
|
||||
36: MEMSTICK
|
||||
37: NAND
|
||||
38: USB0
|
||||
39: USB1
|
||||
40: USB2
|
||||
41: SCR
|
||||
42: CSI0
|
||||
43: CSI1
|
||||
44: LCDCTRL0
|
||||
45: LCDCTRL1
|
||||
46: MP
|
||||
47: DEFEBE0
|
||||
48: DEFEBE1
|
||||
49: PMU
|
||||
50: SPI3
|
||||
51: TZASC
|
||||
52: PATA
|
||||
53: VE
|
||||
54: SS
|
||||
55: EMAC
|
||||
56: SATA
|
||||
57: GPS
|
||||
58: HDMI
|
||||
59: TVE
|
||||
60: ACE
|
||||
61: TVD
|
||||
62: PS2_0
|
||||
63: PS2_1
|
||||
64: USB3
|
||||
65: USB4
|
||||
66: PLE_PFM
|
||||
67: TIMER4
|
||||
68: TIMER5
|
||||
69: GPU_GP
|
||||
70: GPU_GPMMU
|
||||
71: GPU_PP0
|
||||
72: GPU_PPMMU0
|
||||
73: GPU_PMU
|
||||
74: GPU_RSV0
|
||||
75: GPU_RSV1
|
||||
76: GPU_RSV2
|
||||
77: GPU_RSV3
|
||||
78: GPU_RSV4
|
||||
79: GPU_RSV5
|
||||
80: GPU_RSV6
|
||||
82: SYNC_TIMER0
|
||||
83: SYNC_TIMER1
|
||||
|
||||
Example:
|
||||
|
||||
intc: interrupt-controller {
|
||||
compatible = "allwinner,sunxi-ic";
|
||||
reg = <0x01c20400 0x400>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
|
@ -8,13 +8,20 @@ on-chip controllers onto these pads.
|
|||
Required Properties:
|
||||
- compatible: should be one of the following.
|
||||
- "samsung,pinctrl-exynos4210": for Exynos4210 compatible pin-controller.
|
||||
- "samsung,pinctrl-exynos4x12": for Exynos4x12 compatible pin-controller.
|
||||
- "samsung,pinctrl-exynos5250": for Exynos5250 compatible pin-controller.
|
||||
|
||||
- reg: Base address of the pin controller hardware module and length of
|
||||
the address space it occupies.
|
||||
|
||||
- interrupts: interrupt specifier for the controller. The format and value of
|
||||
the interrupt specifier depends on the interrupt parent for the controller.
|
||||
- Pin banks as child nodes: Pin banks of the controller are represented by child
|
||||
nodes of the controller node. Bank name is taken from name of the node. Each
|
||||
bank node must contain following properties:
|
||||
|
||||
- gpio-controller: identifies the node as a gpio controller and pin bank.
|
||||
- #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
|
||||
binding is used, the amount of cells must be specified as 2. See generic
|
||||
GPIO binding documentation for description of particular cells.
|
||||
|
||||
- Pin mux/config groups as child nodes: The pin mux (selecting pin function
|
||||
mode) and pin config (pull up/down, driver strength) settings are represented
|
||||
|
|
@ -72,16 +79,24 @@ used as system wakeup events.
|
|||
A. External GPIO Interrupts: For supporting external gpio interrupts, the
|
||||
following properties should be specified in the pin-controller device node.
|
||||
|
||||
- interrupt-controller: identifies the controller node as interrupt-parent.
|
||||
- #interrupt-cells: the value of this property should be 2.
|
||||
- First Cell: represents the external gpio interrupt number local to the
|
||||
external gpio interrupt space of the controller.
|
||||
- Second Cell: flags to identify the type of the interrupt
|
||||
- 1 = rising edge triggered
|
||||
- 2 = falling edge triggered
|
||||
- 3 = rising and falling edge triggered
|
||||
- 4 = high level triggered
|
||||
- 8 = low level triggered
|
||||
- interrupt-parent: phandle of the interrupt parent to which the external
|
||||
GPIO interrupts are forwarded to.
|
||||
- interrupts: interrupt specifier for the controller. The format and value of
|
||||
the interrupt specifier depends on the interrupt parent for the controller.
|
||||
|
||||
In addition, following properties must be present in node of every bank
|
||||
of pins supporting GPIO interrupts:
|
||||
|
||||
- interrupt-controller: identifies the controller node as interrupt-parent.
|
||||
- #interrupt-cells: the value of this property should be 2.
|
||||
- First Cell: represents the external gpio interrupt number local to the
|
||||
external gpio interrupt space of the controller.
|
||||
- Second Cell: flags to identify the type of the interrupt
|
||||
- 1 = rising edge triggered
|
||||
- 2 = falling edge triggered
|
||||
- 3 = rising and falling edge triggered
|
||||
- 4 = high level triggered
|
||||
- 8 = low level triggered
|
||||
|
||||
B. External Wakeup Interrupts: For supporting external wakeup interrupts, a
|
||||
child node representing the external wakeup interrupt controller should be
|
||||
|
|
@ -94,6 +109,11 @@ B. External Wakeup Interrupts: For supporting external wakeup interrupts, a
|
|||
found on Samsung Exynos4210 SoC.
|
||||
- interrupt-parent: phandle of the interrupt parent to which the external
|
||||
wakeup interrupts are forwarded to.
|
||||
- interrupts: interrupt used by multiplexed wakeup interrupts.
|
||||
|
||||
In addition, following properties must be present in node of every bank
|
||||
of pins supporting wake-up interrupts:
|
||||
|
||||
- interrupt-controller: identifies the node as interrupt-parent.
|
||||
- #interrupt-cells: the value of this property should be 2
|
||||
- First Cell: represents the external wakeup interrupt number local to
|
||||
|
|
@ -105,11 +125,63 @@ B. External Wakeup Interrupts: For supporting external wakeup interrupts, a
|
|||
- 4 = high level triggered
|
||||
- 8 = low level triggered
|
||||
|
||||
Node of every bank of pins supporting direct wake-up interrupts (without
|
||||
multiplexing) must contain following properties:
|
||||
|
||||
- interrupt-parent: phandle of the interrupt parent to which the external
|
||||
wakeup interrupts are forwarded to.
|
||||
- interrupts: interrupts of the interrupt parent which are used for external
|
||||
wakeup interrupts from pins of the bank, must contain interrupts for all
|
||||
pins of the bank.
|
||||
|
||||
Aliases:
|
||||
|
||||
All the pin controller nodes should be represented in the aliases node using
|
||||
the following format 'pinctrl{n}' where n is a unique number for the alias.
|
||||
|
||||
Example: A pin-controller node with pin banks:
|
||||
|
||||
pinctrl_0: pinctrl@11400000 {
|
||||
compatible = "samsung,pinctrl-exynos4210";
|
||||
reg = <0x11400000 0x1000>;
|
||||
interrupts = <0 47 0>;
|
||||
|
||||
/* ... */
|
||||
|
||||
/* Pin bank without external interrupts */
|
||||
gpy0: gpy0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
/* ... */
|
||||
|
||||
/* Pin bank with external GPIO or muxed wake-up interrupts */
|
||||
gpj0: gpj0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
/* ... */
|
||||
|
||||
/* Pin bank with external direct wake-up interrupts */
|
||||
gpx0: gpx0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
|
||||
<0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
/* ... */
|
||||
};
|
||||
|
||||
Example 1: A pin-controller node with pin groups.
|
||||
|
||||
pinctrl_0: pinctrl@11400000 {
|
||||
|
|
@ -117,6 +189,8 @@ Example 1: A pin-controller node with pin groups.
|
|||
reg = <0x11400000 0x1000>;
|
||||
interrupts = <0 47 0>;
|
||||
|
||||
/* ... */
|
||||
|
||||
uart0_data: uart0-data {
|
||||
samsung,pins = "gpa0-0", "gpa0-1";
|
||||
samsung,pin-function = <2>;
|
||||
|
|
@ -158,20 +232,14 @@ Example 2: A pin-controller node with external wakeup interrupt controller node.
|
|||
pinctrl_1: pinctrl@11000000 {
|
||||
compatible = "samsung,pinctrl-exynos4210";
|
||||
reg = <0x11000000 0x1000>;
|
||||
interrupts = <0 46 0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0 46 0>
|
||||
|
||||
wakup_eint: wakeup-interrupt-controller {
|
||||
/* ... */
|
||||
|
||||
wakeup-interrupt-controller {
|
||||
compatible = "samsung,exynos4210-wakeup-eint";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
|
||||
<0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
|
||||
<0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
|
||||
<0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>,
|
||||
<0 32 0>;
|
||||
interrupts = <0 32 0>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -190,7 +258,8 @@ Example 4: Set up the default pin state for uart controller.
|
|||
|
||||
static int s3c24xx_serial_probe(struct platform_device *pdev) {
|
||||
struct pinctrl *pinctrl;
|
||||
...
|
||||
...
|
||||
|
||||
/* ... */
|
||||
|
||||
pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,17 @@
|
|||
Allwinner A1X SoCs Timer Controller
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : should be "allwinner,sunxi-timer"
|
||||
- reg : Specifies base physical address and size of the registers.
|
||||
- interrupts : The interrupt of the first timer
|
||||
- clocks: phandle to the source clock (usually a 24 MHz fixed clock)
|
||||
|
||||
Example:
|
||||
|
||||
timer {
|
||||
compatible = "allwinner,sunxi-timer";
|
||||
reg = <0x01c20c00 0x400>;
|
||||
interrupts = <22>;
|
||||
clocks = <&osc>;
|
||||
};
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
BCM2835 Watchdog timer
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : should be "brcm,bcm2835-pm-wdt"
|
||||
- reg : Specifies base physical address and size of the registers.
|
||||
|
||||
Example:
|
||||
|
||||
watchdog {
|
||||
compatible = "brcm,bcm2835-pm-wdt";
|
||||
reg = <0x7e100000 0x28>;
|
||||
};
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
Allwinner sunXi Watchdog timer
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : should be "allwinner,sunxi-wdt"
|
||||
- reg : Specifies base physical address and size of the registers.
|
||||
|
||||
Example:
|
||||
|
||||
wdt: watchdog@01c20c90 {
|
||||
compatible = "allwinner,sunxi-wdt";
|
||||
reg = <0x01c20c90 0x10>;
|
||||
};
|
||||
12
MAINTAINERS
12
MAINTAINERS
|
|
@ -685,6 +685,12 @@ M: Lennert Buytenhek <kernel@wantstofly.org>
|
|||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
|
||||
ARM/Allwinner A1X SoC support
|
||||
M: Maxime Ripard <maxime.ripard@free-electrons.com>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
F: arch/arm/mach-sunxi/
|
||||
|
||||
ARM/ATMEL AT91RM9200 AND AT91SAM ARM ARCHITECTURES
|
||||
M: Andrew Victor <linux@maxim.org.za>
|
||||
M: Nicolas Ferre <nicolas.ferre@atmel.com>
|
||||
|
|
@ -707,6 +713,12 @@ S: Maintained
|
|||
F: arch/arm/mach-cns3xxx/
|
||||
T: git git://git.infradead.org/users/cbou/linux-cns3xxx.git
|
||||
|
||||
ARM/CIRRUS LOGIC CLPS711X ARM ARCHITECTURE
|
||||
M: Alexander Shiyan <shc_work@mail.ru>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Odd Fixes
|
||||
F: arch/arm/mach-clps711x/
|
||||
|
||||
ARM/CIRRUS LOGIC EP93XX ARM ARCHITECTURE
|
||||
M: Hartley Sweeten <hsweeten@visionengravers.com>
|
||||
M: Ryan Mallon <rmallon@gmail.com>
|
||||
|
|
|
|||
|
|
@ -286,8 +286,8 @@ config ARCH_INTEGRATOR
|
|||
select MULTI_IRQ_HANDLER
|
||||
select NEED_MACH_MEMORY_H
|
||||
select PLAT_VERSATILE
|
||||
select PLAT_VERSATILE_FPGA_IRQ
|
||||
select SPARSE_IRQ
|
||||
select VERSATILE_FPGA_IRQ
|
||||
help
|
||||
Support for ARM's Integrator platform.
|
||||
|
||||
|
|
@ -320,7 +320,7 @@ config ARCH_VERSATILE
|
|||
select PLAT_VERSATILE
|
||||
select PLAT_VERSATILE_CLCD
|
||||
select PLAT_VERSATILE_CLOCK
|
||||
select PLAT_VERSATILE_FPGA_IRQ
|
||||
select VERSATILE_FPGA_IRQ
|
||||
help
|
||||
This enables support for ARM Ltd Versatile board.
|
||||
|
||||
|
|
@ -340,7 +340,7 @@ config ARCH_AT91
|
|||
|
||||
config ARCH_BCM2835
|
||||
bool "Broadcom BCM2835 family"
|
||||
select ARCH_WANT_OPTIONAL_GPIOLIB
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select ARM_AMBA
|
||||
select ARM_ERRATA_411920
|
||||
select ARM_TIMER_SP804
|
||||
|
|
@ -348,7 +348,10 @@ config ARCH_BCM2835
|
|||
select COMMON_CLK
|
||||
select CPU_V6
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select GENERIC_GPIO
|
||||
select MULTI_IRQ_HANDLER
|
||||
select PINCTRL
|
||||
select PINCTRL_BCM2835
|
||||
select SPARSE_IRQ
|
||||
select USE_OF
|
||||
help
|
||||
|
|
@ -370,10 +373,14 @@ config ARCH_CLPS711X
|
|||
bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select ARCH_USES_GETTIMEOFFSET
|
||||
select AUTO_ZRELADDR
|
||||
select CLKDEV_LOOKUP
|
||||
select COMMON_CLK
|
||||
select CPU_ARM720T
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select MULTI_IRQ_HANDLER
|
||||
select NEED_MACH_MEMORY_H
|
||||
select SPARSE_IRQ
|
||||
help
|
||||
Support for Cirrus Logic 711x/721x/731x based boards.
|
||||
|
||||
|
|
@ -1015,6 +1022,8 @@ source "arch/arm/mach-mvebu/Kconfig"
|
|||
|
||||
source "arch/arm/mach-at91/Kconfig"
|
||||
|
||||
source "arch/arm/mach-bcm/Kconfig"
|
||||
|
||||
source "arch/arm/mach-clps711x/Kconfig"
|
||||
|
||||
source "arch/arm/mach-cns3xxx/Kconfig"
|
||||
|
|
@ -1106,6 +1115,8 @@ source "arch/arm/mach-exynos/Kconfig"
|
|||
|
||||
source "arch/arm/mach-shmobile/Kconfig"
|
||||
|
||||
source "arch/arm/mach-sunxi/Kconfig"
|
||||
|
||||
source "arch/arm/mach-prima2/Kconfig"
|
||||
|
||||
source "arch/arm/mach-tegra/Kconfig"
|
||||
|
|
|
|||
|
|
@ -338,6 +338,17 @@ choice
|
|||
The uncompressor code port configuration is now handled
|
||||
by CONFIG_S3C_LOWLEVEL_UART_PORT.
|
||||
|
||||
config DEBUG_S3C_UART3
|
||||
depends on PLAT_SAMSUNG && ARCH_EXYNOS
|
||||
bool "Use S3C UART 3 for low-level debug"
|
||||
help
|
||||
Say Y here if you want the debug print routines to direct
|
||||
their output to UART 3. The port must have been initialised
|
||||
by the boot-loader before use.
|
||||
|
||||
The uncompressor code port configuration is now handled
|
||||
by CONFIG_S3C_LOWLEVEL_UART_PORT.
|
||||
|
||||
config DEBUG_SOCFPGA_UART
|
||||
depends on ARCH_SOCFPGA
|
||||
bool "Use SOCFPGA UART for low-level debug"
|
||||
|
|
@ -345,6 +356,20 @@ choice
|
|||
Say Y here if you want kernel low-level debugging support
|
||||
on SOCFPGA based platforms.
|
||||
|
||||
config DEBUG_SUNXI_UART0
|
||||
bool "Kernel low-level debugging messages via sunXi UART0"
|
||||
depends on ARCH_SUNXI
|
||||
help
|
||||
Say Y here if you want kernel low-level debugging support
|
||||
on Allwinner A1X based platforms on the UART0.
|
||||
|
||||
config DEBUG_SUNXI_UART1
|
||||
bool "Kernel low-level debugging messages via sunXi UART1"
|
||||
depends on ARCH_SUNXI
|
||||
help
|
||||
Say Y here if you want kernel low-level debugging support
|
||||
on Allwinner A1X based platforms on the UART1.
|
||||
|
||||
config DEBUG_VEXPRESS_UART0_DETECT
|
||||
bool "Autodetect UART0 on Versatile Express Cortex-A core tiles"
|
||||
depends on ARCH_VEXPRESS && CPU_CP15_MMU
|
||||
|
|
@ -424,6 +449,7 @@ config DEBUG_LL_INCLUDE
|
|||
default "debug/mvebu.S" if DEBUG_MVEBU_UART
|
||||
default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART
|
||||
default "debug/socfpga.S" if DEBUG_SOCFPGA_UART
|
||||
default "debug/sunxi.S" if DEBUG_SUNXI_UART0 || DEBUG_SUNXI_UART1
|
||||
default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \
|
||||
DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1
|
||||
default "mach/debug-macro.S"
|
||||
|
|
|
|||
|
|
@ -138,6 +138,7 @@ textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
|
|||
# Machine directory name. This list is sorted alphanumerically
|
||||
# by CONFIG_* macro name.
|
||||
machine-$(CONFIG_ARCH_AT91) += at91
|
||||
machine-$(CONFIG_ARCH_BCM) += bcm
|
||||
machine-$(CONFIG_ARCH_BCM2835) += bcm2835
|
||||
machine-$(CONFIG_ARCH_CLPS711X) += clps711x
|
||||
machine-$(CONFIG_ARCH_CNS3XXX) += cns3xxx
|
||||
|
|
@ -194,6 +195,7 @@ machine-$(CONFIG_ARCH_SPEAR13XX) += spear13xx
|
|||
machine-$(CONFIG_ARCH_SPEAR3XX) += spear3xx
|
||||
machine-$(CONFIG_MACH_SPEAR600) += spear6xx
|
||||
machine-$(CONFIG_ARCH_ZYNQ) += zynq
|
||||
machine-$(CONFIG_ARCH_SUNXI) += sunxi
|
||||
|
||||
# Platform directory name. This list is sorted alphanumerically
|
||||
# by CONFIG_* macro name.
|
||||
|
|
|
|||
|
|
@ -45,11 +45,6 @@ ifeq ($(CONFIG_ARCH_SHARK),y)
|
|||
OBJS += head-shark.o ofw-shark.o
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ARCH_P720T),y)
|
||||
# Borrow this code from SA1100
|
||||
OBJS += head-sa1100.o
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ARCH_SA1100),y)
|
||||
OBJS += head-sa1100.o
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -33,14 +33,17 @@ dtb-$(CONFIG_ARCH_AT91) += at91sam9x25ek.dtb
|
|||
dtb-$(CONFIG_ARCH_AT91) += at91sam9x35ek.dtb
|
||||
|
||||
dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
|
||||
dtb-$(CONFIG_ARCH_BCM) += bcm11351-brt.dtb
|
||||
dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
|
||||
dove-cubox.dtb \
|
||||
dove-dove-db.dtb
|
||||
dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
|
||||
exynos4210-smdkv310.dtb \
|
||||
exynos4210-trats.dtb \
|
||||
exynos5250-smdk5250.dtb
|
||||
dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb
|
||||
exynos5250-smdk5250.dtb \
|
||||
exynos5440-ssdk5440.dtb
|
||||
dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
|
||||
ecx-2000.dtb
|
||||
dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \
|
||||
integratorcp.dtb
|
||||
dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
|
||||
|
|
@ -102,6 +105,8 @@ dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
|
|||
spear310-evb.dtb \
|
||||
spear320-evb.dtb
|
||||
dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
|
||||
dtb-$(CONFIG_ARCH_SUNXI) += sun4i-cubieboard.dtb \
|
||||
sun5i-olinuxino.dtb
|
||||
dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
|
||||
tegra20-medcom-wide.dtb \
|
||||
tegra20-paz00.dtb \
|
||||
|
|
|
|||
|
|
@ -0,0 +1,30 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Broadcom Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "bcm11351.dtsi"
|
||||
|
||||
/ {
|
||||
model = "BCM11351 BRT board";
|
||||
compatible = "bcm,bcm11351-brt", "bcm,bcm11351";
|
||||
|
||||
memory {
|
||||
reg = <0x80000000 0x40000000>; /* 1 GB */
|
||||
};
|
||||
|
||||
uart@3e000000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
};
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Broadcom Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
model = "BCM11351 SoC";
|
||||
compatible = "bcm,bcm11351";
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200n8";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@3ff00100 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
reg = <0x3ff01000 0x1000>,
|
||||
<0x3ff00100 0x100>;
|
||||
};
|
||||
|
||||
uart@3e000000 {
|
||||
compatible = "bcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
|
||||
status = "disabled";
|
||||
reg = <0x3e000000 0x1000>;
|
||||
clock-frequency = <13000000>;
|
||||
interrupts = <0x0 67 0x4>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
};
|
||||
|
||||
L2: l2-cache {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0x3ff20000 0x1000>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
};
|
||||
|
|
@ -10,3 +10,18 @@ memory {
|
|||
reg = <0 0x10000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&gpio {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&alt0 &alt3>;
|
||||
|
||||
alt0: alt0 {
|
||||
brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11 14 15 40 45>;
|
||||
brcm,function = <4>; /* alt0 */
|
||||
};
|
||||
|
||||
alt3: alt3 {
|
||||
brcm,pins = <48 49 50 51 52 53>;
|
||||
brcm,function = <7>; /* alt3 */
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -29,11 +29,39 @@ intc: interrupt-controller {
|
|||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
watchdog {
|
||||
compatible = "brcm,bcm2835-pm-wdt";
|
||||
reg = <0x7e100000 0x28>;
|
||||
};
|
||||
|
||||
uart@20201000 {
|
||||
compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
|
||||
reg = <0x7e201000 0x1000>;
|
||||
interrupts = <2 25>;
|
||||
clock-frequency = <3000000>;
|
||||
};
|
||||
|
||||
gpio: gpio {
|
||||
compatible = "brcm,bcm2835-gpio";
|
||||
reg = <0x7e200000 0xb4>;
|
||||
/*
|
||||
* The GPIO IP block is designed for 3 banks of GPIOs.
|
||||
* Each bank has a GPIO interrupt for itself.
|
||||
* There is an overall "any bank" interrupt.
|
||||
* In order, these are GIC interrupts 17, 18, 19, 20.
|
||||
* Since the BCM2835 only has 2 banks, the 2nd bank
|
||||
* interrupt output appears to be mirrored onto the
|
||||
* 3rd bank's interrupt signal.
|
||||
* So, a bank0 interrupt shows up on 17, 20, and
|
||||
* a bank1 interrupt shows up on 18, 19, 20!
|
||||
*/
|
||||
interrupts = <2 17>, <2 18>, <2 19>, <2 20>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,104 @@
|
|||
/*
|
||||
* Copyright 2011-2012 Calxeda, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/* First 4KB has pen for secondary cores. */
|
||||
/memreserve/ 0x00000000 0x0001000;
|
||||
|
||||
/ {
|
||||
model = "Calxeda ECX-2000";
|
||||
compatible = "calxeda,ecx-2000";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
clock-ranges;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0>;
|
||||
clocks = <&a9pll>;
|
||||
clock-names = "cpu";
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <1>;
|
||||
clocks = <&a9pll>;
|
||||
clock-names = "cpu";
|
||||
};
|
||||
|
||||
cpu@2 {
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <2>;
|
||||
clocks = <&a9pll>;
|
||||
clock-names = "cpu";
|
||||
};
|
||||
|
||||
cpu@3 {
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <3>;
|
||||
clocks = <&a9pll>;
|
||||
clock-names = "cpu";
|
||||
};
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
name = "memory";
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x00000000 0x00000000 0xff800000>;
|
||||
};
|
||||
|
||||
memory@200000000 {
|
||||
name = "memory";
|
||||
device_type = "memory";
|
||||
reg = <0x00000002 0x00000000 0x00000003 0x00000000>;
|
||||
};
|
||||
|
||||
soc {
|
||||
ranges = <0x00000000 0x00000000 0x00000000 0xffffffff>;
|
||||
|
||||
timer {
|
||||
compatible = "arm,cortex-a15-timer", "arm,armv7-timer"; interrupts = <1 13 0xf08>,
|
||||
<1 14 0xf08>,
|
||||
<1 11 0xf08>,
|
||||
<1 10 0xf08>;
|
||||
};
|
||||
|
||||
intc: interrupt-controller@fff11000 {
|
||||
compatible = "arm,cortex-a15-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#size-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
interrupt-controller;
|
||||
interrupts = <1 9 0xf04>;
|
||||
reg = <0xfff11000 0x1000>,
|
||||
<0xfff12000 0x1000>,
|
||||
<0xfff14000 0x2000>,
|
||||
<0xfff16000 0x2000>;
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a9-pmu";
|
||||
interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "ecx-common.dtsi"
|
||||
|
|
@ -0,0 +1,237 @@
|
|||
/*
|
||||
* Copyright 2011-2012 Calxeda, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
bootargs = "console=ttyAMA0";
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
sata@ffe08000 {
|
||||
compatible = "calxeda,hb-ahci";
|
||||
reg = <0xffe08000 0x10000>;
|
||||
interrupts = <0 83 4>;
|
||||
dma-coherent;
|
||||
calxeda,port-phys = <&combophy5 0 &combophy0 0
|
||||
&combophy0 1 &combophy0 2
|
||||
&combophy0 3>;
|
||||
};
|
||||
|
||||
sdhci@ffe0e000 {
|
||||
compatible = "calxeda,hb-sdhci";
|
||||
reg = <0xffe0e000 0x1000>;
|
||||
interrupts = <0 90 4>;
|
||||
clocks = <&eclk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
memory-controller@fff00000 {
|
||||
compatible = "calxeda,hb-ddr-ctrl";
|
||||
reg = <0xfff00000 0x1000>;
|
||||
interrupts = <0 91 4>;
|
||||
};
|
||||
|
||||
ipc@fff20000 {
|
||||
compatible = "arm,pl320", "arm,primecell";
|
||||
reg = <0xfff20000 0x1000>;
|
||||
interrupts = <0 7 4>;
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
gpioe: gpio@fff30000 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "arm,pl061", "arm,primecell";
|
||||
gpio-controller;
|
||||
reg = <0xfff30000 0x1000>;
|
||||
interrupts = <0 14 4>;
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpiof: gpio@fff31000 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "arm,pl061", "arm,primecell";
|
||||
gpio-controller;
|
||||
reg = <0xfff31000 0x1000>;
|
||||
interrupts = <0 15 4>;
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpiog: gpio@fff32000 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "arm,pl061", "arm,primecell";
|
||||
gpio-controller;
|
||||
reg = <0xfff32000 0x1000>;
|
||||
interrupts = <0 16 4>;
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpioh: gpio@fff33000 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "arm,pl061", "arm,primecell";
|
||||
gpio-controller;
|
||||
reg = <0xfff33000 0x1000>;
|
||||
interrupts = <0 17 4>;
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer@fff34000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0xfff34000 0x1000>;
|
||||
interrupts = <0 18 4>;
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
rtc@fff35000 {
|
||||
compatible = "arm,pl031", "arm,primecell";
|
||||
reg = <0xfff35000 0x1000>;
|
||||
interrupts = <0 19 4>;
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
serial@fff36000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0xfff36000 0x1000>;
|
||||
interrupts = <0 20 4>;
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
smic@fff3a000 {
|
||||
compatible = "ipmi-smic";
|
||||
device_type = "ipmi";
|
||||
reg = <0xfff3a000 0x1000>;
|
||||
interrupts = <0 24 4>;
|
||||
reg-size = <4>;
|
||||
reg-spacing = <4>;
|
||||
};
|
||||
|
||||
sregs@fff3c000 {
|
||||
compatible = "calxeda,hb-sregs";
|
||||
reg = <0xfff3c000 0x1000>;
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
osc: oscillator {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <33333000>;
|
||||
};
|
||||
|
||||
ddrpll: ddrpll {
|
||||
#clock-cells = <0>;
|
||||
compatible = "calxeda,hb-pll-clock";
|
||||
clocks = <&osc>;
|
||||
reg = <0x108>;
|
||||
};
|
||||
|
||||
a9pll: a9pll {
|
||||
#clock-cells = <0>;
|
||||
compatible = "calxeda,hb-pll-clock";
|
||||
clocks = <&osc>;
|
||||
reg = <0x100>;
|
||||
};
|
||||
|
||||
a9periphclk: a9periphclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "calxeda,hb-a9periph-clock";
|
||||
clocks = <&a9pll>;
|
||||
reg = <0x104>;
|
||||
};
|
||||
|
||||
a9bclk: a9bclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "calxeda,hb-a9bus-clock";
|
||||
clocks = <&a9pll>;
|
||||
reg = <0x104>;
|
||||
};
|
||||
|
||||
emmcpll: emmcpll {
|
||||
#clock-cells = <0>;
|
||||
compatible = "calxeda,hb-pll-clock";
|
||||
clocks = <&osc>;
|
||||
reg = <0x10C>;
|
||||
};
|
||||
|
||||
eclk: eclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "calxeda,hb-emmc-clock";
|
||||
clocks = <&emmcpll>;
|
||||
reg = <0x114>;
|
||||
};
|
||||
|
||||
pclk: pclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <150000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dma@fff3d000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0xfff3d000 0x1000>;
|
||||
interrupts = <0 92 4>;
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
ethernet@fff50000 {
|
||||
compatible = "calxeda,hb-xgmac";
|
||||
reg = <0xfff50000 0x1000>;
|
||||
interrupts = <0 77 4 0 78 4 0 79 4>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
ethernet@fff51000 {
|
||||
compatible = "calxeda,hb-xgmac";
|
||||
reg = <0xfff51000 0x1000>;
|
||||
interrupts = <0 80 4 0 81 4 0 82 4>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
combophy0: combo-phy@fff58000 {
|
||||
compatible = "calxeda,hb-combophy";
|
||||
#phy-cells = <1>;
|
||||
reg = <0xfff58000 0x1000>;
|
||||
phydev = <5>;
|
||||
};
|
||||
|
||||
combophy5: combo-phy@fff5d000 {
|
||||
compatible = "calxeda,hb-combophy";
|
||||
#phy-cells = <1>;
|
||||
reg = <0xfff5d000 0x1000>;
|
||||
phydev = <31>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -244,5 +244,11 @@ pdma1: pdma@12690000 {
|
|||
reg = <0x12690000 0x1000>;
|
||||
interrupts = <0 36 0>;
|
||||
};
|
||||
|
||||
mdma1: mdma@12850000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x12850000 0x1000>;
|
||||
interrupts = <0 34 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -16,6 +16,134 @@
|
|||
|
||||
/ {
|
||||
pinctrl@11400000 {
|
||||
gpa0: gpa0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpa1: gpa1 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpb: gpb {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpc0: gpc0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpc1: gpc1 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpd0: gpd0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpd1: gpd1 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpe0: gpe0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpe1: gpe1 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpe2: gpe2 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpe3: gpe3 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpe4: gpe4 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpf0: gpf0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpf1: gpf1 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpf2: gpf2 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpf3: gpf3 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
uart0_data: uart0-data {
|
||||
samsung,pins = "gpa0-0", "gpa0-1";
|
||||
samsung,pin-function = <0x2>;
|
||||
|
|
@ -205,6 +333,151 @@ i2c1_bus: i2c1-bus {
|
|||
};
|
||||
|
||||
pinctrl@11000000 {
|
||||
gpj0: gpj0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpj1: gpj1 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpk0: gpk0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpk1: gpk1 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpk2: gpk2 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpk3: gpk3 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpl0: gpl0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpl1: gpl1 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpl2: gpl2 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpy0: gpy0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpy1: gpy1 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpy2: gpy2 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpy3: gpy3 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpy4: gpy4 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpy5: gpy5 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpy6: gpy6 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpx0: gpx0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
|
||||
<0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpx1: gpx1 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
|
||||
<0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpx2: gpx2 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpx3: gpx3 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
sd0_clk: sd0-clk {
|
||||
samsung,pins = "gpk0-0";
|
||||
samsung,pin-function = <2>;
|
||||
|
|
@ -438,6 +711,11 @@ eint31: ext-int31 {
|
|||
};
|
||||
|
||||
pinctrl@03860000 {
|
||||
gpz: gpz {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
i2s0_bus: i2s0-bus {
|
||||
samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
|
||||
"gpz-4", "gpz-5", "gpz-6";
|
||||
|
|
|
|||
|
|
@ -46,27 +46,17 @@ pinctrl_0: pinctrl@11400000 {
|
|||
compatible = "samsung,pinctrl-exynos4210";
|
||||
reg = <0x11400000 0x1000>;
|
||||
interrupts = <0 47 0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
pinctrl_1: pinctrl@11000000 {
|
||||
compatible = "samsung,pinctrl-exynos4210";
|
||||
reg = <0x11000000 0x1000>;
|
||||
interrupts = <0 46 0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
wakup_eint: wakeup-interrupt-controller {
|
||||
compatible = "samsung,exynos4210-wakeup-eint";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
|
||||
<0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
|
||||
<0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
|
||||
<0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>,
|
||||
<0 32 0>;
|
||||
interrupts = <0 32 0>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -74,233 +64,4 @@ pinctrl_2: pinctrl@03860000 {
|
|||
compatible = "samsung,pinctrl-exynos4210";
|
||||
reg = <0x03860000 0x1000>;
|
||||
};
|
||||
|
||||
gpio-controllers {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
gpio-controller;
|
||||
ranges;
|
||||
|
||||
gpa0: gpio-controller@11400000 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400000 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpa1: gpio-controller@11400020 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400020 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpb: gpio-controller@11400040 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400040 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpc0: gpio-controller@11400060 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400060 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpc1: gpio-controller@11400080 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400080 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpd0: gpio-controller@114000A0 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x114000A0 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpd1: gpio-controller@114000C0 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x114000C0 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpe0: gpio-controller@114000E0 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x114000E0 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpe1: gpio-controller@11400100 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400100 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpe2: gpio-controller@11400120 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400120 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpe3: gpio-controller@11400140 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400140 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpe4: gpio-controller@11400160 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400160 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpf0: gpio-controller@11400180 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11400180 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpf1: gpio-controller@114001A0 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x114001A0 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpf2: gpio-controller@114001C0 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x114001C0 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpf3: gpio-controller@114001E0 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x114001E0 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpj0: gpio-controller@11000000 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11000000 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpj1: gpio-controller@11000020 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11000020 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpk0: gpio-controller@11000040 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11000040 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpk1: gpio-controller@11000060 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11000060 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpk2: gpio-controller@11000080 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11000080 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpk3: gpio-controller@110000A0 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x110000A0 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpl0: gpio-controller@110000C0 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x110000C0 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpl1: gpio-controller@110000E0 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x110000E0 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpl2: gpio-controller@11000100 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11000100 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpy0: gpio-controller@11000120 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11000120 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpy1: gpio-controller@11000140 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11000140 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpy2: gpio-controller@11000160 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11000160 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpy3: gpio-controller@11000180 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11000180 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpy4: gpio-controller@110001A0 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x110001A0 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpy5: gpio-controller@110001C0 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x110001C0 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpy6: gpio-controller@110001E0 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x110001E0 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpx0: gpio-controller@11000C00 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11000C00 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpx1: gpio-controller@11000C20 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11000C20 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpx2: gpio-controller@11000C40 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11000C40 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpx3: gpio-controller@11000C60 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x11000C60 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
|
||||
gpz: gpio-controller@03860000 {
|
||||
compatible = "samsung,exynos4-gpio";
|
||||
reg = <0x03860000 0x20>;
|
||||
#gpio-cells = <4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,46 @@
|
|||
/*
|
||||
* SAMSUNG SSDK5440 board device tree source
|
||||
*
|
||||
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "exynos5440.dtsi"
|
||||
|
||||
/ {
|
||||
model = "SAMSUNG SSDK5440 board based on EXYNOS5440";
|
||||
compatible = "samsung,ssdk5440", "samsung,exynos5440";
|
||||
|
||||
memory {
|
||||
reg = <0x80000000 0x80000000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x81000000,8M console=ttySAC2,115200 init=/linuxrc";
|
||||
};
|
||||
|
||||
spi {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@F0000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@100000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
watchdog {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rtc {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,159 @@
|
|||
/*
|
||||
* SAMSUNG EXYNOS5440 SoC device tree source
|
||||
*
|
||||
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "samsung,exynos5440";
|
||||
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
gic:interrupt-controller@2E0000 {
|
||||
compatible = "arm,cortex-a15-gic";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0x2E1000 0x1000>, <0x2E2000 0x1000>;
|
||||
};
|
||||
|
||||
cpus {
|
||||
cpu@0 {
|
||||
compatible = "arm,cortex-a15";
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts = <1 13 0xf08>;
|
||||
clock-frequency = <1000000>;
|
||||
};
|
||||
};
|
||||
cpu@1 {
|
||||
compatible = "arm,cortex-a15";
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts = <1 14 0xf08>;
|
||||
clock-frequency = <1000000>;
|
||||
};
|
||||
};
|
||||
cpu@2 {
|
||||
compatible = "arm,cortex-a15";
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts = <1 14 0xf08>;
|
||||
clock-frequency = <1000000>;
|
||||
};
|
||||
};
|
||||
cpu@3 {
|
||||
compatible = "arm,cortex-a15";
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts = <1 14 0xf08>;
|
||||
clock-frequency = <1000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
common {
|
||||
compatible = "samsung,exynos5440";
|
||||
|
||||
};
|
||||
|
||||
serial@B0000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0xB0000 0x1000>;
|
||||
interrupts = <0 2 0>;
|
||||
};
|
||||
|
||||
serial@C0000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0xC0000 0x1000>;
|
||||
interrupts = <0 3 0>;
|
||||
};
|
||||
|
||||
spi {
|
||||
compatible = "samsung,exynos4210-spi";
|
||||
reg = <0xD0000 0x1000>;
|
||||
interrupts = <0 4 0>;
|
||||
tx-dma-channel = <&pdma0 5>; /* preliminary */
|
||||
rx-dma-channel = <&pdma0 4>; /* preliminary */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
pinctrl {
|
||||
compatible = "samsung,pinctrl-exynos5440";
|
||||
reg = <0xE0000 0x1000>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
fan: fan {
|
||||
samsung,exynos5440-pin-function = <1>;
|
||||
};
|
||||
|
||||
hdd_led0: hdd_led0 {
|
||||
samsung,exynos5440-pin-function = <2>;
|
||||
};
|
||||
|
||||
hdd_led1: hdd_led1 {
|
||||
samsung,exynos5440-pin-function = <3>;
|
||||
};
|
||||
|
||||
uart1: uart1 {
|
||||
samsung,exynos5440-pin-function = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@F0000 {
|
||||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0xF0000 0x1000>;
|
||||
interrupts = <0 5 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
i2c@100000 {
|
||||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x100000 0x1000>;
|
||||
interrupts = <0 6 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
watchdog {
|
||||
compatible = "samsung,s3c2410-wdt";
|
||||
reg = <0x110000 0x1000>;
|
||||
interrupts = <0 1 0>;
|
||||
};
|
||||
|
||||
amba {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "arm,amba-bus";
|
||||
interrupt-parent = <&gic>;
|
||||
ranges;
|
||||
|
||||
pdma0: pdma@121A0000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x120000 0x1000>;
|
||||
interrupts = <0 34 0>;
|
||||
};
|
||||
|
||||
pdma1: pdma@121B0000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x121000 0x1000>;
|
||||
interrupts = <0 35 0>;
|
||||
};
|
||||
};
|
||||
|
||||
rtc {
|
||||
compatible = "samsung,s3c6410-rtc";
|
||||
reg = <0x130000 0x1000>;
|
||||
interrupts = <0 16 0>, <0 17 0>;
|
||||
};
|
||||
};
|
||||
|
|
@ -69,16 +69,8 @@ memory {
|
|||
reg = <0x00000000 0xff900000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyAMA0";
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
interrupt-parent = <&intc>;
|
||||
ranges;
|
||||
ranges = <0x00000000 0x00000000 0xffffffff>;
|
||||
|
||||
timer@fff10600 {
|
||||
compatible = "arm,cortex-a9-twd-timer";
|
||||
|
|
@ -117,173 +109,6 @@ pmu {
|
|||
interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>;
|
||||
};
|
||||
|
||||
sata@ffe08000 {
|
||||
compatible = "calxeda,hb-ahci";
|
||||
reg = <0xffe08000 0x10000>;
|
||||
interrupts = <0 83 4>;
|
||||
calxeda,port-phys = <&combophy5 0 &combophy0 0
|
||||
&combophy0 1 &combophy0 2
|
||||
&combophy0 3>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
sdhci@ffe0e000 {
|
||||
compatible = "calxeda,hb-sdhci";
|
||||
reg = <0xffe0e000 0x1000>;
|
||||
interrupts = <0 90 4>;
|
||||
clocks = <&eclk>;
|
||||
};
|
||||
|
||||
memory-controller@fff00000 {
|
||||
compatible = "calxeda,hb-ddr-ctrl";
|
||||
reg = <0xfff00000 0x1000>;
|
||||
interrupts = <0 91 4>;
|
||||
};
|
||||
|
||||
ipc@fff20000 {
|
||||
compatible = "arm,pl320", "arm,primecell";
|
||||
reg = <0xfff20000 0x1000>;
|
||||
interrupts = <0 7 4>;
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
gpioe: gpio@fff30000 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "arm,pl061", "arm,primecell";
|
||||
gpio-controller;
|
||||
reg = <0xfff30000 0x1000>;
|
||||
interrupts = <0 14 4>;
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
gpiof: gpio@fff31000 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "arm,pl061", "arm,primecell";
|
||||
gpio-controller;
|
||||
reg = <0xfff31000 0x1000>;
|
||||
interrupts = <0 15 4>;
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
gpiog: gpio@fff32000 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "arm,pl061", "arm,primecell";
|
||||
gpio-controller;
|
||||
reg = <0xfff32000 0x1000>;
|
||||
interrupts = <0 16 4>;
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
gpioh: gpio@fff33000 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "arm,pl061", "arm,primecell";
|
||||
gpio-controller;
|
||||
reg = <0xfff33000 0x1000>;
|
||||
interrupts = <0 17 4>;
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0xfff34000 0x1000>;
|
||||
interrupts = <0 18 4>;
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
rtc@fff35000 {
|
||||
compatible = "arm,pl031", "arm,primecell";
|
||||
reg = <0xfff35000 0x1000>;
|
||||
interrupts = <0 19 4>;
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
serial@fff36000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0xfff36000 0x1000>;
|
||||
interrupts = <0 20 4>;
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
smic@fff3a000 {
|
||||
compatible = "ipmi-smic";
|
||||
device_type = "ipmi";
|
||||
reg = <0xfff3a000 0x1000>;
|
||||
interrupts = <0 24 4>;
|
||||
reg-size = <4>;
|
||||
reg-spacing = <4>;
|
||||
};
|
||||
|
||||
sregs@fff3c000 {
|
||||
compatible = "calxeda,hb-sregs";
|
||||
reg = <0xfff3c000 0x1000>;
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
osc: oscillator {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <33333000>;
|
||||
};
|
||||
|
||||
ddrpll: ddrpll {
|
||||
#clock-cells = <0>;
|
||||
compatible = "calxeda,hb-pll-clock";
|
||||
clocks = <&osc>;
|
||||
reg = <0x108>;
|
||||
};
|
||||
|
||||
a9pll: a9pll {
|
||||
#clock-cells = <0>;
|
||||
compatible = "calxeda,hb-pll-clock";
|
||||
clocks = <&osc>;
|
||||
reg = <0x100>;
|
||||
};
|
||||
|
||||
a9periphclk: a9periphclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "calxeda,hb-a9periph-clock";
|
||||
clocks = <&a9pll>;
|
||||
reg = <0x104>;
|
||||
};
|
||||
|
||||
a9bclk: a9bclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "calxeda,hb-a9bus-clock";
|
||||
clocks = <&a9pll>;
|
||||
reg = <0x104>;
|
||||
};
|
||||
|
||||
emmcpll: emmcpll {
|
||||
#clock-cells = <0>;
|
||||
compatible = "calxeda,hb-pll-clock";
|
||||
clocks = <&osc>;
|
||||
reg = <0x10C>;
|
||||
};
|
||||
|
||||
eclk: eclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "calxeda,hb-emmc-clock";
|
||||
clocks = <&emmcpll>;
|
||||
reg = <0x114>;
|
||||
};
|
||||
|
||||
pclk: pclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <150000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sregs@fff3c200 {
|
||||
compatible = "calxeda,hb-sregs-l2-ecc";
|
||||
|
|
@ -291,38 +116,7 @@ sregs@fff3c200 {
|
|||
interrupts = <0 71 4 0 72 4>;
|
||||
};
|
||||
|
||||
dma@fff3d000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0xfff3d000 0x1000>;
|
||||
interrupts = <0 92 4>;
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
ethernet@fff50000 {
|
||||
compatible = "calxeda,hb-xgmac";
|
||||
reg = <0xfff50000 0x1000>;
|
||||
interrupts = <0 77 4 0 78 4 0 79 4>;
|
||||
};
|
||||
|
||||
ethernet@fff51000 {
|
||||
compatible = "calxeda,hb-xgmac";
|
||||
reg = <0xfff51000 0x1000>;
|
||||
interrupts = <0 80 4 0 81 4 0 82 4>;
|
||||
};
|
||||
|
||||
combophy0: combo-phy@fff58000 {
|
||||
compatible = "calxeda,hb-combophy";
|
||||
#phy-cells = <1>;
|
||||
reg = <0xfff58000 0x1000>;
|
||||
phydev = <5>;
|
||||
};
|
||||
|
||||
combophy5: combo-phy@fff5d000 {
|
||||
compatible = "calxeda,hb-combophy";
|
||||
#phy-cells = <1>;
|
||||
reg = <0xfff5d000 0x1000>;
|
||||
phydev = <31>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "ecx-common.dtsi"
|
||||
|
|
|
|||
|
|
@ -23,10 +23,6 @@ memory {
|
|||
soc {
|
||||
aipi@10000000 { /* aipi */
|
||||
|
||||
wdog@10002000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
uart1: serial@1000a000 {
|
||||
fsl,uart-has-rtscts;
|
||||
status = "okay";
|
||||
|
|
|
|||
|
|
@ -22,6 +22,22 @@ memory {
|
|||
};
|
||||
|
||||
soc {
|
||||
display@di0 {
|
||||
compatible = "fsl,imx-parallel-display";
|
||||
crtcs = <&ipu 0>;
|
||||
interface-pix-fmt = "rgb24";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ipu_disp1_1>;
|
||||
};
|
||||
|
||||
display@di1 {
|
||||
compatible = "fsl,imx-parallel-display";
|
||||
crtcs = <&ipu 1>;
|
||||
interface-pix-fmt = "rgb565";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ipu_disp2_1>;
|
||||
};
|
||||
|
||||
aips@70000000 { /* aips-1 */
|
||||
spba@70000000 {
|
||||
esdhc@70004000 { /* ESDHC1 */
|
||||
|
|
|
|||
|
|
@ -62,6 +62,13 @@ soc {
|
|||
interrupt-parent = <&tzic>;
|
||||
ranges;
|
||||
|
||||
ipu: ipu@40000000 {
|
||||
#crtc-cells = <1>;
|
||||
compatible = "fsl,imx51-ipu";
|
||||
reg = <0x40000000 0x20000000>;
|
||||
interrupts = <11 10>;
|
||||
};
|
||||
|
||||
aips@70000000 { /* AIPS1 */
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
|
|
@ -80,6 +87,8 @@ esdhc@70004000 { /* ESDHC1 */
|
|||
compatible = "fsl,imx51-esdhc";
|
||||
reg = <0x70004000 0x4000>;
|
||||
interrupts = <1>;
|
||||
clocks = <&clks 44>, <&clks 0>, <&clks 71>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -87,6 +96,8 @@ esdhc@70008000 { /* ESDHC2 */
|
|||
compatible = "fsl,imx51-esdhc";
|
||||
reg = <0x70008000 0x4000>;
|
||||
interrupts = <2>;
|
||||
clocks = <&clks 45>, <&clks 0>, <&clks 72>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -94,6 +105,8 @@ uart3: serial@7000c000 {
|
|||
compatible = "fsl,imx51-uart", "fsl,imx21-uart";
|
||||
reg = <0x7000c000 0x4000>;
|
||||
interrupts = <33>;
|
||||
clocks = <&clks 32>, <&clks 33>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -103,6 +116,8 @@ ecspi@70010000 { /* ECSPI1 */
|
|||
compatible = "fsl,imx51-ecspi";
|
||||
reg = <0x70010000 0x4000>;
|
||||
interrupts = <36>;
|
||||
clocks = <&clks 51>, <&clks 52>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -110,6 +125,7 @@ ssi2: ssi@70014000 {
|
|||
compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
|
||||
reg = <0x70014000 0x4000>;
|
||||
interrupts = <30>;
|
||||
clocks = <&clks 49>;
|
||||
fsl,fifo-depth = <15>;
|
||||
fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
|
||||
status = "disabled";
|
||||
|
|
@ -119,6 +135,8 @@ esdhc@70020000 { /* ESDHC3 */
|
|||
compatible = "fsl,imx51-esdhc";
|
||||
reg = <0x70020000 0x4000>;
|
||||
interrupts = <3>;
|
||||
clocks = <&clks 46>, <&clks 0>, <&clks 73>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -126,6 +144,8 @@ esdhc@70024000 { /* ESDHC4 */
|
|||
compatible = "fsl,imx51-esdhc";
|
||||
reg = <0x70024000 0x4000>;
|
||||
interrupts = <4>;
|
||||
clocks = <&clks 47>, <&clks 0>, <&clks 74>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
@ -202,12 +222,14 @@ wdog@73f98000 { /* WDOG1 */
|
|||
compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x73f98000 0x4000>;
|
||||
interrupts = <58>;
|
||||
clocks = <&clks 0>;
|
||||
};
|
||||
|
||||
wdog@73f9c000 { /* WDOG2 */
|
||||
compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x73f9c000 0x4000>;
|
||||
interrupts = <59>;
|
||||
clocks = <&clks 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -295,6 +317,66 @@ pinctrl_i2c2_1: i2c2grp-1 {
|
|||
};
|
||||
};
|
||||
|
||||
ipu_disp1 {
|
||||
pinctrl_ipu_disp1_1: ipudisp1grp-1 {
|
||||
fsl,pins = <
|
||||
528 0x5 /* MX51_PAD_DISP1_DAT0__DISP1_DAT0 */
|
||||
529 0x5 /* MX51_PAD_DISP1_DAT1__DISP1_DAT1 */
|
||||
530 0x5 /* MX51_PAD_DISP1_DAT2__DISP1_DAT2 */
|
||||
531 0x5 /* MX51_PAD_DISP1_DAT3__DISP1_DAT3 */
|
||||
532 0x5 /* MX51_PAD_DISP1_DAT4__DISP1_DAT4 */
|
||||
533 0x5 /* MX51_PAD_DISP1_DAT5__DISP1_DAT5 */
|
||||
535 0x5 /* MX51_PAD_DISP1_DAT6__DISP1_DAT6 */
|
||||
537 0x5 /* MX51_PAD_DISP1_DAT7__DISP1_DAT7 */
|
||||
539 0x5 /* MX51_PAD_DISP1_DAT8__DISP1_DAT8 */
|
||||
541 0x5 /* MX51_PAD_DISP1_DAT9__DISP1_DAT9 */
|
||||
543 0x5 /* MX51_PAD_DISP1_DAT10__DISP1_DAT10 */
|
||||
545 0x5 /* MX51_PAD_DISP1_DAT11__DISP1_DAT11 */
|
||||
547 0x5 /* MX51_PAD_DISP1_DAT12__DISP1_DAT12 */
|
||||
549 0x5 /* MX51_PAD_DISP1_DAT13__DISP1_DAT13 */
|
||||
551 0x5 /* MX51_PAD_DISP1_DAT14__DISP1_DAT14 */
|
||||
553 0x5 /* MX51_PAD_DISP1_DAT15__DISP1_DAT15 */
|
||||
555 0x5 /* MX51_PAD_DISP1_DAT16__DISP1_DAT16 */
|
||||
557 0x5 /* MX51_PAD_DISP1_DAT17__DISP1_DAT17 */
|
||||
559 0x5 /* MX51_PAD_DISP1_DAT18__DISP1_DAT18 */
|
||||
563 0x5 /* MX51_PAD_DISP1_DAT19__DISP1_DAT19 */
|
||||
567 0x5 /* MX51_PAD_DISP1_DAT20__DISP1_DAT20 */
|
||||
571 0x5 /* MX51_PAD_DISP1_DAT21__DISP1_DAT21 */
|
||||
575 0x5 /* MX51_PAD_DISP1_DAT22__DISP1_DAT22 */
|
||||
579 0x5 /* MX51_PAD_DISP1_DAT23__DISP1_DAT23 */
|
||||
584 0x5 /* MX51_PAD_DI1_PIN2__DI1_PIN2 (hsync) */
|
||||
583 0x5 /* MX51_PAD_DI1_PIN3__DI1_PIN3 (vsync) */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
ipu_disp2 {
|
||||
pinctrl_ipu_disp2_1: ipudisp2grp-1 {
|
||||
fsl,pins = <
|
||||
603 0x5 /* MX51_PAD_DISP2_DAT0__DISP2_DAT0 */
|
||||
608 0x5 /* MX51_PAD_DISP2_DAT1__DISP2_DAT1 */
|
||||
613 0x5 /* MX51_PAD_DISP2_DAT2__DISP2_DAT2 */
|
||||
614 0x5 /* MX51_PAD_DISP2_DAT3__DISP2_DAT3 */
|
||||
615 0x5 /* MX51_PAD_DISP2_DAT4__DISP2_DAT4 */
|
||||
616 0x5 /* MX51_PAD_DISP2_DAT5__DISP2_DAT5 */
|
||||
617 0x5 /* MX51_PAD_DISP2_DAT6__DISP2_DAT6 */
|
||||
622 0x5 /* MX51_PAD_DISP2_DAT7__DISP2_DAT7 */
|
||||
627 0x5 /* MX51_PAD_DISP2_DAT8__DISP2_DAT8 */
|
||||
633 0x5 /* MX51_PAD_DISP2_DAT9__DISP2_DAT9 */
|
||||
637 0x5 /* MX51_PAD_DISP2_DAT10__DISP2_DAT10 */
|
||||
643 0x5 /* MX51_PAD_DISP2_DAT11__DISP2_DAT11 */
|
||||
648 0x5 /* MX51_PAD_DISP2_DAT12__DISP2_DAT12 */
|
||||
652 0x5 /* MX51_PAD_DISP2_DAT13__DISP2_DAT13 */
|
||||
656 0x5 /* MX51_PAD_DISP2_DAT14__DISP2_DAT14 */
|
||||
661 0x5 /* MX51_PAD_DISP2_DAT15__DISP2_DAT15 */
|
||||
593 0x5 /* MX51_PAD_DI2_PIN2__DI2_PIN2 (hsync) */
|
||||
595 0x5 /* MX51_PAD_DI2_PIN3__DI2_PIN3 (vsync) */
|
||||
597 0x5 /* MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK */
|
||||
599 0x5 /* MX51_PAD_DI_GP4__DI2_PIN15 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
uart1 {
|
||||
pinctrl_uart1_1: uart1grp-1 {
|
||||
fsl,pins = <
|
||||
|
|
@ -327,10 +409,30 @@ pinctrl_uart3_1: uart3grp-1 {
|
|||
};
|
||||
};
|
||||
|
||||
pwm1: pwm@73fb4000 {
|
||||
#pwm-cells = <2>;
|
||||
compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x73fb4000 0x4000>;
|
||||
clocks = <&clks 37>, <&clks 38>;
|
||||
clock-names = "ipg", "per";
|
||||
interrupts = <61>;
|
||||
};
|
||||
|
||||
pwm2: pwm@73fb8000 {
|
||||
#pwm-cells = <2>;
|
||||
compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x73fb8000 0x4000>;
|
||||
clocks = <&clks 39>, <&clks 40>;
|
||||
clock-names = "ipg", "per";
|
||||
interrupts = <94>;
|
||||
};
|
||||
|
||||
uart1: serial@73fbc000 {
|
||||
compatible = "fsl,imx51-uart", "fsl,imx21-uart";
|
||||
reg = <0x73fbc000 0x4000>;
|
||||
interrupts = <31>;
|
||||
clocks = <&clks 28>, <&clks 29>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -338,8 +440,17 @@ uart2: serial@73fc0000 {
|
|||
compatible = "fsl,imx51-uart", "fsl,imx21-uart";
|
||||
reg = <0x73fc0000 0x4000>;
|
||||
interrupts = <32>;
|
||||
clocks = <&clks 30>, <&clks 31>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
clks: ccm@73fd4000{
|
||||
compatible = "fsl,imx51-ccm";
|
||||
reg = <0x73fd4000 0x4000>;
|
||||
interrupts = <0 71 0x04 0 72 0x04>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
aips@80000000 { /* AIPS2 */
|
||||
|
|
@ -355,6 +466,8 @@ ecspi@83fac000 { /* ECSPI2 */
|
|||
compatible = "fsl,imx51-ecspi";
|
||||
reg = <0x83fac000 0x4000>;
|
||||
interrupts = <37>;
|
||||
clocks = <&clks 53>, <&clks 54>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -362,6 +475,8 @@ sdma@83fb0000 {
|
|||
compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
|
||||
reg = <0x83fb0000 0x4000>;
|
||||
interrupts = <6>;
|
||||
clocks = <&clks 56>, <&clks 56>;
|
||||
clock-names = "ipg", "ahb";
|
||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
|
||||
};
|
||||
|
||||
|
|
@ -371,6 +486,8 @@ cspi@83fc0000 {
|
|||
compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
|
||||
reg = <0x83fc0000 0x4000>;
|
||||
interrupts = <38>;
|
||||
clocks = <&clks 55>, <&clks 0>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -380,6 +497,7 @@ i2c@83fc4000 { /* I2C2 */
|
|||
compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x83fc4000 0x4000>;
|
||||
interrupts = <63>;
|
||||
clocks = <&clks 35>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -389,6 +507,7 @@ i2c@83fc8000 { /* I2C1 */
|
|||
compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x83fc8000 0x4000>;
|
||||
interrupts = <62>;
|
||||
clocks = <&clks 34>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -396,6 +515,7 @@ ssi1: ssi@83fcc000 {
|
|||
compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
|
||||
reg = <0x83fcc000 0x4000>;
|
||||
interrupts = <29>;
|
||||
clocks = <&clks 48>;
|
||||
fsl,fifo-depth = <15>;
|
||||
fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
|
||||
status = "disabled";
|
||||
|
|
@ -411,6 +531,7 @@ nand@83fdb000 {
|
|||
compatible = "fsl,imx51-nand";
|
||||
reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
|
||||
interrupts = <8>;
|
||||
clocks = <&clks 60>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -418,6 +539,7 @@ ssi3: ssi@83fe8000 {
|
|||
compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
|
||||
reg = <0x83fe8000 0x4000>;
|
||||
interrupts = <96>;
|
||||
clocks = <&clks 50>;
|
||||
fsl,fifo-depth = <15>;
|
||||
fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
|
||||
status = "disabled";
|
||||
|
|
@ -427,6 +549,8 @@ ethernet@83fec000 {
|
|||
compatible = "fsl,imx51-fec", "fsl,imx27-fec";
|
||||
reg = <0x83fec000 0x4000>;
|
||||
interrupts = <87>;
|
||||
clocks = <&clks 42>, <&clks 42>, <&clks 42>;
|
||||
clock-names = "ipg", "ahb", "ptp";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -67,6 +67,13 @@ soc {
|
|||
interrupt-parent = <&tzic>;
|
||||
ranges;
|
||||
|
||||
ipu: ipu@18000000 {
|
||||
#crtc-cells = <1>;
|
||||
compatible = "fsl,imx53-ipu";
|
||||
reg = <0x18000000 0x080000000>;
|
||||
interrupts = <11 10>;
|
||||
};
|
||||
|
||||
aips@50000000 { /* AIPS1 */
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
|
|
@ -85,6 +92,8 @@ esdhc@50004000 { /* ESDHC1 */
|
|||
compatible = "fsl,imx53-esdhc";
|
||||
reg = <0x50004000 0x4000>;
|
||||
interrupts = <1>;
|
||||
clocks = <&clks 44>, <&clks 0>, <&clks 71>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -92,6 +101,8 @@ esdhc@50008000 { /* ESDHC2 */
|
|||
compatible = "fsl,imx53-esdhc";
|
||||
reg = <0x50008000 0x4000>;
|
||||
interrupts = <2>;
|
||||
clocks = <&clks 45>, <&clks 0>, <&clks 72>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -99,6 +110,8 @@ uart3: serial@5000c000 {
|
|||
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
|
||||
reg = <0x5000c000 0x4000>;
|
||||
interrupts = <33>;
|
||||
clocks = <&clks 32>, <&clks 33>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -108,6 +121,8 @@ ecspi@50010000 { /* ECSPI1 */
|
|||
compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x50010000 0x4000>;
|
||||
interrupts = <36>;
|
||||
clocks = <&clks 51>, <&clks 52>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -115,6 +130,7 @@ ssi2: ssi@50014000 {
|
|||
compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
|
||||
reg = <0x50014000 0x4000>;
|
||||
interrupts = <30>;
|
||||
clocks = <&clks 49>;
|
||||
fsl,fifo-depth = <15>;
|
||||
fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
|
||||
status = "disabled";
|
||||
|
|
@ -124,6 +140,8 @@ esdhc@50020000 { /* ESDHC3 */
|
|||
compatible = "fsl,imx53-esdhc";
|
||||
reg = <0x50020000 0x4000>;
|
||||
interrupts = <3>;
|
||||
clocks = <&clks 46>, <&clks 0>, <&clks 73>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -131,6 +149,8 @@ esdhc@50024000 { /* ESDHC4 */
|
|||
compatible = "fsl,imx53-esdhc";
|
||||
reg = <0x50024000 0x4000>;
|
||||
interrupts = <4>;
|
||||
clocks = <&clks 47>, <&clks 0>, <&clks 74>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
@ -207,12 +227,14 @@ wdog@53f98000 { /* WDOG1 */
|
|||
compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x53f98000 0x4000>;
|
||||
interrupts = <58>;
|
||||
clocks = <&clks 0>;
|
||||
};
|
||||
|
||||
wdog@53f9c000 { /* WDOG2 */
|
||||
compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x53f9c000 0x4000>;
|
||||
interrupts = <59>;
|
||||
clocks = <&clks 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -371,10 +393,30 @@ pinctrl_uart3_1: uart3grp-1 {
|
|||
};
|
||||
};
|
||||
|
||||
pwm1: pwm@53fb4000 {
|
||||
#pwm-cells = <2>;
|
||||
compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x53fb4000 0x4000>;
|
||||
clocks = <&clks 37>, <&clks 38>;
|
||||
clock-names = "ipg", "per";
|
||||
interrupts = <61>;
|
||||
};
|
||||
|
||||
pwm2: pwm@53fb8000 {
|
||||
#pwm-cells = <2>;
|
||||
compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x53fb8000 0x4000>;
|
||||
clocks = <&clks 39>, <&clks 40>;
|
||||
clock-names = "ipg", "per";
|
||||
interrupts = <94>;
|
||||
};
|
||||
|
||||
uart1: serial@53fbc000 {
|
||||
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
|
||||
reg = <0x53fbc000 0x4000>;
|
||||
interrupts = <31>;
|
||||
clocks = <&clks 28>, <&clks 29>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -382,6 +424,8 @@ uart2: serial@53fc0000 {
|
|||
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
|
||||
reg = <0x53fc0000 0x4000>;
|
||||
interrupts = <32>;
|
||||
clocks = <&clks 30>, <&clks 31>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -389,6 +433,8 @@ can1: can@53fc8000 {
|
|||
compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
|
||||
reg = <0x53fc8000 0x4000>;
|
||||
interrupts = <82>;
|
||||
clocks = <&clks 158>, <&clks 157>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -396,9 +442,18 @@ can2: can@53fcc000 {
|
|||
compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
|
||||
reg = <0x53fcc000 0x4000>;
|
||||
interrupts = <83>;
|
||||
clocks = <&clks 158>, <&clks 157>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
clks: ccm@53fd4000{
|
||||
compatible = "fsl,imx53-ccm";
|
||||
reg = <0x53fd4000 0x4000>;
|
||||
interrupts = <0 71 0x04 0 72 0x04>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
gpio5: gpio@53fdc000 {
|
||||
compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x53fdc000 0x4000>;
|
||||
|
|
@ -435,6 +490,7 @@ i2c@53fec000 { /* I2C3 */
|
|||
compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x53fec000 0x4000>;
|
||||
interrupts = <64>;
|
||||
clocks = <&clks 88>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -442,6 +498,8 @@ uart4: serial@53ff0000 {
|
|||
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
|
||||
reg = <0x53ff0000 0x4000>;
|
||||
interrupts = <13>;
|
||||
clocks = <&clks 65>, <&clks 66>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
@ -457,6 +515,8 @@ uart5: serial@63f90000 {
|
|||
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
|
||||
reg = <0x63f90000 0x4000>;
|
||||
interrupts = <86>;
|
||||
clocks = <&clks 67>, <&clks 68>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -466,6 +526,8 @@ ecspi@63fac000 { /* ECSPI2 */
|
|||
compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x63fac000 0x4000>;
|
||||
interrupts = <37>;
|
||||
clocks = <&clks 53>, <&clks 54>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -473,6 +535,8 @@ sdma@63fb0000 {
|
|||
compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
|
||||
reg = <0x63fb0000 0x4000>;
|
||||
interrupts = <6>;
|
||||
clocks = <&clks 56>, <&clks 56>;
|
||||
clock-names = "ipg", "ahb";
|
||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
|
||||
};
|
||||
|
||||
|
|
@ -482,6 +546,8 @@ cspi@63fc0000 {
|
|||
compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
|
||||
reg = <0x63fc0000 0x4000>;
|
||||
interrupts = <38>;
|
||||
clocks = <&clks 55>, <&clks 0>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -491,6 +557,7 @@ i2c@63fc4000 { /* I2C2 */
|
|||
compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x63fc4000 0x4000>;
|
||||
interrupts = <63>;
|
||||
clocks = <&clks 35>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -500,6 +567,7 @@ i2c@63fc8000 { /* I2C1 */
|
|||
compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x63fc8000 0x4000>;
|
||||
interrupts = <62>;
|
||||
clocks = <&clks 34>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -507,6 +575,7 @@ ssi1: ssi@63fcc000 {
|
|||
compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
|
||||
reg = <0x63fcc000 0x4000>;
|
||||
interrupts = <29>;
|
||||
clocks = <&clks 48>;
|
||||
fsl,fifo-depth = <15>;
|
||||
fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
|
||||
status = "disabled";
|
||||
|
|
@ -522,6 +591,7 @@ nand@63fdb000 {
|
|||
compatible = "fsl,imx53-nand";
|
||||
reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
|
||||
interrupts = <8>;
|
||||
clocks = <&clks 60>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -529,6 +599,7 @@ ssi3: ssi@63fe8000 {
|
|||
compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
|
||||
reg = <0x63fe8000 0x4000>;
|
||||
interrupts = <96>;
|
||||
clocks = <&clks 50>;
|
||||
fsl,fifo-depth = <15>;
|
||||
fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
|
||||
status = "disabled";
|
||||
|
|
@ -538,6 +609,8 @@ ethernet@63fec000 {
|
|||
compatible = "fsl,imx53-fec", "fsl,imx25-fec";
|
||||
reg = <0x63fec000 0x4000>;
|
||||
interrupts = <87>;
|
||||
clocks = <&clks 42>, <&clks 42>, <&clks 42>;
|
||||
clock-names = "ipg", "ahb", "ptp";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -268,23 +268,39 @@ aipstz@0207c000 { /* AIPSTZ1 */
|
|||
};
|
||||
|
||||
pwm@02080000 { /* PWM1 */
|
||||
#pwm-cells = <2>;
|
||||
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x02080000 0x4000>;
|
||||
interrupts = <0 83 0x04>;
|
||||
clocks = <&clks 62>, <&clks 145>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
pwm@02084000 { /* PWM2 */
|
||||
#pwm-cells = <2>;
|
||||
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x02084000 0x4000>;
|
||||
interrupts = <0 84 0x04>;
|
||||
clocks = <&clks 62>, <&clks 146>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
pwm@02088000 { /* PWM3 */
|
||||
#pwm-cells = <2>;
|
||||
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x02088000 0x4000>;
|
||||
interrupts = <0 85 0x04>;
|
||||
clocks = <&clks 62>, <&clks 147>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
pwm@0208c000 { /* PWM4 */
|
||||
#pwm-cells = <2>;
|
||||
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x0208c000 0x4000>;
|
||||
interrupts = <0 86 0x04>;
|
||||
clocks = <&clks 62>, <&clks 148>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
flexcan@02090000 { /* CAN1 */
|
||||
|
|
@ -1001,5 +1017,23 @@ uart5: serial@021f4000 {
|
|||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
ipu1: ipu@02400000 {
|
||||
#crtc-cells = <1>;
|
||||
compatible = "fsl,imx6q-ipu";
|
||||
reg = <0x02400000 0x400000>;
|
||||
interrupts = <0 6 0x4 0 5 0x4>;
|
||||
clocks = <&clks 130>, <&clks 131>, <&clks 132>;
|
||||
clock-names = "bus", "di0", "di1";
|
||||
};
|
||||
|
||||
ipu2: ipu@02800000 {
|
||||
#crtc-cells = <1>;
|
||||
compatible = "fsl,imx6q-ipu";
|
||||
reg = <0x02800000 0x400000>;
|
||||
interrupts = <0 8 0x4 0 7 0x4>;
|
||||
clocks = <&clks 133>, <&clks 134>, <&clks 137>;
|
||||
clock-names = "bus", "di0", "di1";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,21 +0,0 @@
|
|||
/*
|
||||
* Device Tree Source for the sh7377 SoC
|
||||
*
|
||||
* Copyright (C) 2012 Renesas Solutions Corp.
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "renesas,sh7377";
|
||||
|
||||
cpus {
|
||||
cpu@0 {
|
||||
compatible = "arm,cortex-a8";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
/*
|
||||
* Copyright 2012 Stefan Roese
|
||||
* Stefan Roese <sr@denx.de>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "sun4i.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Cubietech Cubieboard";
|
||||
compatible = "cubietech,cubieboard", "allwinner,sun4i";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "earlyprintk console=ttyS0,115200";
|
||||
};
|
||||
|
||||
soc {
|
||||
uart0: uart@01c28000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
uart1: uart@01c28400 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
/*
|
||||
* Copyright 2012 Stefan Roese
|
||||
* Stefan Roese <sr@denx.de>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/include/ "sunxi.dtsi"
|
||||
|
||||
/ {
|
||||
memory {
|
||||
reg = <0x40000000 0x80000000>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/*
|
||||
* Copyright 2012 Maxime Ripard
|
||||
*
|
||||
* Maxime Ripard <maxime.ripard@free-electrons.com>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "sun5i.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Olimex A13-Olinuxino";
|
||||
compatible = "olimex,a13-olinuxino", "allwinner,sun5i";
|
||||
|
||||
chosen {
|
||||
bootargs = "earlyprintk console=ttyS0,115200";
|
||||
};
|
||||
|
||||
soc {
|
||||
uart1: uart@01c28400 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/*
|
||||
* Copyright 2012 Maxime Ripard
|
||||
*
|
||||
* Maxime Ripard <maxime.ripard@free-electrons.com>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/include/ "sunxi.dtsi"
|
||||
|
||||
/ {
|
||||
memory {
|
||||
reg = <0x40000000 0x20000000>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,80 @@
|
|||
/*
|
||||
* Copyright 2012 Maxime Ripard
|
||||
*
|
||||
* Maxime Ripard <maxime.ripard@free-electrons.com>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
cpus {
|
||||
cpu@0 {
|
||||
compatible = "arm,cortex-a8";
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
osc: oscillator {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x01c20000 0x300000>;
|
||||
ranges;
|
||||
|
||||
timer@01c20c00 {
|
||||
compatible = "allwinner,sunxi-timer";
|
||||
reg = <0x01c20c00 0x90>;
|
||||
interrupts = <22>;
|
||||
clocks = <&osc>;
|
||||
};
|
||||
|
||||
wdt: watchdog@01c20c90 {
|
||||
compatible = "allwinner,sunxi-wdt";
|
||||
reg = <0x01c20c90 0x10>;
|
||||
};
|
||||
|
||||
intc: interrupt-controller@01c20400 {
|
||||
compatible = "allwinner,sunxi-ic";
|
||||
reg = <0x01c20400 0x400>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
uart0: uart@01c28000 {
|
||||
compatible = "ns8250";
|
||||
reg = <0x01c28000 0x400>;
|
||||
interrupts = <1>;
|
||||
reg-shift = <2>;
|
||||
clock-frequency = <24000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: uart@01c28400 {
|
||||
compatible = "ns8250";
|
||||
reg = <0x01c28400 0x400>;
|
||||
interrupts = <2>;
|
||||
reg-shift = <2>;
|
||||
clock-frequency = <24000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -4,6 +4,15 @@ / {
|
|||
compatible = "nvidia,tegra20";
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
cache-controller@50043000 {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0x50043000 0x1000>;
|
||||
arm,data-latency = <5 5 2>;
|
||||
arm,tag-latency = <4 4 2>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
intc: interrupt-controller {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
reg = <0x50041000 0x1000
|
||||
|
|
|
|||
|
|
@ -4,6 +4,15 @@ / {
|
|||
compatible = "nvidia,tegra30";
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
cache-controller@50043000 {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0x50043000 0x1000>;
|
||||
arm,data-latency = <6 6 2>;
|
||||
arm,tag-latency = <5 5 2>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
intc: interrupt-controller {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
reg = <0x50041000 0x1000
|
||||
|
|
|
|||
|
|
@ -17,17 +17,16 @@
|
|||
* CHANGES TO vexpress-v2m.dtsi!
|
||||
*/
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
arm,v2m_timer = &v2m_timer01;
|
||||
};
|
||||
|
||||
motherboard {
|
||||
compatible = "simple-bus";
|
||||
model = "V2M-P1";
|
||||
arm,hbi = <0x190>;
|
||||
arm,vexpress,site = <0>;
|
||||
arm,v2m-memory-map = "rs1";
|
||||
compatible = "arm,vexpress,v2m-p1", "simple-bus";
|
||||
#address-cells = <2>; /* SMB chipselect number and offset */
|
||||
#size-cells = <1>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
|
||||
flash@0,00000000 {
|
||||
compatible = "arm,vexpress-flash", "cfi-flash";
|
||||
|
|
@ -72,14 +71,20 @@ iofpga@3,00000000 {
|
|||
#size-cells = <1>;
|
||||
ranges = <0 3 0 0x200000>;
|
||||
|
||||
sysreg@010000 {
|
||||
v2m_sysreg: sysreg@010000 {
|
||||
compatible = "arm,vexpress-sysreg";
|
||||
reg = <0x010000 0x1000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
sysctl@020000 {
|
||||
v2m_sysctl: sysctl@020000 {
|
||||
compatible = "arm,sp810", "arm,primecell";
|
||||
reg = <0x020000 0x1000>;
|
||||
clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
|
||||
clock-names = "refclk", "timclk", "apb_pclk";
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
|
||||
};
|
||||
|
||||
/* PCI-E I2C bus */
|
||||
|
|
@ -100,66 +105,92 @@ aaci@040000 {
|
|||
compatible = "arm,pl041", "arm,primecell";
|
||||
reg = <0x040000 0x1000>;
|
||||
interrupts = <11>;
|
||||
clocks = <&smbclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
mmci@050000 {
|
||||
compatible = "arm,pl180", "arm,primecell";
|
||||
reg = <0x050000 0x1000>;
|
||||
interrupts = <9 10>;
|
||||
cd-gpios = <&v2m_sysreg 0 0>;
|
||||
wp-gpios = <&v2m_sysreg 1 0>;
|
||||
max-frequency = <12000000>;
|
||||
vmmc-supply = <&v2m_fixed_3v3>;
|
||||
clocks = <&v2m_clk24mhz>, <&smbclk>;
|
||||
clock-names = "mclk", "apb_pclk";
|
||||
};
|
||||
|
||||
kmi@060000 {
|
||||
compatible = "arm,pl050", "arm,primecell";
|
||||
reg = <0x060000 0x1000>;
|
||||
interrupts = <12>;
|
||||
clocks = <&v2m_clk24mhz>, <&smbclk>;
|
||||
clock-names = "KMIREFCLK", "apb_pclk";
|
||||
};
|
||||
|
||||
kmi@070000 {
|
||||
compatible = "arm,pl050", "arm,primecell";
|
||||
reg = <0x070000 0x1000>;
|
||||
interrupts = <13>;
|
||||
clocks = <&v2m_clk24mhz>, <&smbclk>;
|
||||
clock-names = "KMIREFCLK", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_serial0: uart@090000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x090000 0x1000>;
|
||||
interrupts = <5>;
|
||||
clocks = <&v2m_oscclk2>, <&smbclk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_serial1: uart@0a0000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x0a0000 0x1000>;
|
||||
interrupts = <6>;
|
||||
clocks = <&v2m_oscclk2>, <&smbclk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_serial2: uart@0b0000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x0b0000 0x1000>;
|
||||
interrupts = <7>;
|
||||
clocks = <&v2m_oscclk2>, <&smbclk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_serial3: uart@0c0000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x0c0000 0x1000>;
|
||||
interrupts = <8>;
|
||||
clocks = <&v2m_oscclk2>, <&smbclk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
wdt@0f0000 {
|
||||
compatible = "arm,sp805", "arm,primecell";
|
||||
reg = <0x0f0000 0x1000>;
|
||||
interrupts = <0>;
|
||||
clocks = <&v2m_refclk32khz>, <&smbclk>;
|
||||
clock-names = "wdogclk", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_timer01: timer@110000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x110000 0x1000>;
|
||||
interrupts = <2>;
|
||||
clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
|
||||
clock-names = "timclken1", "timclken2", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_timer23: timer@120000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x120000 0x1000>;
|
||||
interrupts = <3>;
|
||||
clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
|
||||
clock-names = "timclken1", "timclken2", "apb_pclk";
|
||||
};
|
||||
|
||||
/* DVI I2C bus */
|
||||
|
|
@ -185,6 +216,8 @@ rtc@170000 {
|
|||
compatible = "arm,pl031", "arm,primecell";
|
||||
reg = <0x170000 0x1000>;
|
||||
interrupts = <4>;
|
||||
clocks = <&smbclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
compact-flash@1a0000 {
|
||||
|
|
@ -198,6 +231,8 @@ clcd@1f0000 {
|
|||
compatible = "arm,pl111", "arm,primecell";
|
||||
reg = <0x1f0000 0x1000>;
|
||||
interrupts = <14>;
|
||||
clocks = <&v2m_oscclk1>, <&smbclk>;
|
||||
clock-names = "clcdclk", "apb_pclk";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -208,5 +243,98 @@ v2m_fixed_3v3: fixedregulator@0 {
|
|||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
v2m_clk24mhz: clk24mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "v2m:clk24mhz";
|
||||
};
|
||||
|
||||
v2m_refclk1mhz: refclk1mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <1000000>;
|
||||
clock-output-names = "v2m:refclk1mhz";
|
||||
};
|
||||
|
||||
v2m_refclk32khz: refclk32khz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "v2m:refclk32khz";
|
||||
};
|
||||
|
||||
mcc {
|
||||
compatible = "arm,vexpress,config-bus";
|
||||
arm,vexpress,config-bridge = <&v2m_sysreg>;
|
||||
|
||||
osc@0 {
|
||||
/* MCC static memory clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 0>;
|
||||
freq-range = <25000000 60000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "v2m:oscclk0";
|
||||
};
|
||||
|
||||
v2m_oscclk1: osc@1 {
|
||||
/* CLCD clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 1>;
|
||||
freq-range = <23750000 63500000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "v2m:oscclk1";
|
||||
};
|
||||
|
||||
v2m_oscclk2: osc@2 {
|
||||
/* IO FPGA peripheral clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 2>;
|
||||
freq-range = <24000000 24000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "v2m:oscclk2";
|
||||
};
|
||||
|
||||
volt@0 {
|
||||
/* Logic level voltage */
|
||||
compatible = "arm,vexpress-volt";
|
||||
arm,vexpress-sysreg,func = <2 0>;
|
||||
regulator-name = "VIO";
|
||||
regulator-always-on;
|
||||
label = "VIO";
|
||||
};
|
||||
|
||||
temp@0 {
|
||||
/* MCC internal operating temperature */
|
||||
compatible = "arm,vexpress-temp";
|
||||
arm,vexpress-sysreg,func = <4 0>;
|
||||
label = "MCC";
|
||||
};
|
||||
|
||||
reset@0 {
|
||||
compatible = "arm,vexpress-reset";
|
||||
arm,vexpress-sysreg,func = <5 0>;
|
||||
};
|
||||
|
||||
muxfpga@0 {
|
||||
compatible = "arm,vexpress-muxfpga";
|
||||
arm,vexpress-sysreg,func = <7 0>;
|
||||
};
|
||||
|
||||
shutdown@0 {
|
||||
compatible = "arm,vexpress-shutdown";
|
||||
arm,vexpress-sysreg,func = <8 0>;
|
||||
};
|
||||
|
||||
reboot@0 {
|
||||
compatible = "arm,vexpress-reboot";
|
||||
arm,vexpress-sysreg,func = <9 0>;
|
||||
};
|
||||
|
||||
dvimode@0 {
|
||||
compatible = "arm,vexpress-dvimode";
|
||||
arm,vexpress-sysreg,func = <11 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -17,16 +17,15 @@
|
|||
* CHANGES TO vexpress-v2m-rs1.dtsi!
|
||||
*/
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
arm,v2m_timer = &v2m_timer01;
|
||||
};
|
||||
|
||||
motherboard {
|
||||
compatible = "simple-bus";
|
||||
model = "V2M-P1";
|
||||
arm,hbi = <0x190>;
|
||||
arm,vexpress,site = <0>;
|
||||
compatible = "arm,vexpress,v2m-p1", "simple-bus";
|
||||
#address-cells = <2>; /* SMB chipselect number and offset */
|
||||
#size-cells = <1>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
|
||||
flash@0,00000000 {
|
||||
compatible = "arm,vexpress-flash", "cfi-flash";
|
||||
|
|
@ -71,14 +70,20 @@ iofpga@7,00000000 {
|
|||
#size-cells = <1>;
|
||||
ranges = <0 7 0 0x20000>;
|
||||
|
||||
sysreg@00000 {
|
||||
v2m_sysreg: sysreg@00000 {
|
||||
compatible = "arm,vexpress-sysreg";
|
||||
reg = <0x00000 0x1000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
sysctl@01000 {
|
||||
v2m_sysctl: sysctl@01000 {
|
||||
compatible = "arm,sp810", "arm,primecell";
|
||||
reg = <0x01000 0x1000>;
|
||||
clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
|
||||
clock-names = "refclk", "timclk", "apb_pclk";
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
|
||||
};
|
||||
|
||||
/* PCI-E I2C bus */
|
||||
|
|
@ -99,66 +104,92 @@ aaci@04000 {
|
|||
compatible = "arm,pl041", "arm,primecell";
|
||||
reg = <0x04000 0x1000>;
|
||||
interrupts = <11>;
|
||||
clocks = <&smbclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
mmci@05000 {
|
||||
compatible = "arm,pl180", "arm,primecell";
|
||||
reg = <0x05000 0x1000>;
|
||||
interrupts = <9 10>;
|
||||
cd-gpios = <&v2m_sysreg 0 0>;
|
||||
wp-gpios = <&v2m_sysreg 1 0>;
|
||||
max-frequency = <12000000>;
|
||||
vmmc-supply = <&v2m_fixed_3v3>;
|
||||
clocks = <&v2m_clk24mhz>, <&smbclk>;
|
||||
clock-names = "mclk", "apb_pclk";
|
||||
};
|
||||
|
||||
kmi@06000 {
|
||||
compatible = "arm,pl050", "arm,primecell";
|
||||
reg = <0x06000 0x1000>;
|
||||
interrupts = <12>;
|
||||
clocks = <&v2m_clk24mhz>, <&smbclk>;
|
||||
clock-names = "KMIREFCLK", "apb_pclk";
|
||||
};
|
||||
|
||||
kmi@07000 {
|
||||
compatible = "arm,pl050", "arm,primecell";
|
||||
reg = <0x07000 0x1000>;
|
||||
interrupts = <13>;
|
||||
clocks = <&v2m_clk24mhz>, <&smbclk>;
|
||||
clock-names = "KMIREFCLK", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_serial0: uart@09000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x09000 0x1000>;
|
||||
interrupts = <5>;
|
||||
clocks = <&v2m_oscclk2>, <&smbclk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_serial1: uart@0a000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x0a000 0x1000>;
|
||||
interrupts = <6>;
|
||||
clocks = <&v2m_oscclk2>, <&smbclk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_serial2: uart@0b000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x0b000 0x1000>;
|
||||
interrupts = <7>;
|
||||
clocks = <&v2m_oscclk2>, <&smbclk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_serial3: uart@0c000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x0c000 0x1000>;
|
||||
interrupts = <8>;
|
||||
clocks = <&v2m_oscclk2>, <&smbclk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
wdt@0f000 {
|
||||
compatible = "arm,sp805", "arm,primecell";
|
||||
reg = <0x0f000 0x1000>;
|
||||
interrupts = <0>;
|
||||
clocks = <&v2m_refclk32khz>, <&smbclk>;
|
||||
clock-names = "wdogclk", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_timer01: timer@11000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x11000 0x1000>;
|
||||
interrupts = <2>;
|
||||
clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
|
||||
clock-names = "timclken1", "timclken2", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_timer23: timer@12000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x12000 0x1000>;
|
||||
interrupts = <3>;
|
||||
clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
|
||||
clock-names = "timclken1", "timclken2", "apb_pclk";
|
||||
};
|
||||
|
||||
/* DVI I2C bus */
|
||||
|
|
@ -184,6 +215,8 @@ rtc@17000 {
|
|||
compatible = "arm,pl031", "arm,primecell";
|
||||
reg = <0x17000 0x1000>;
|
||||
interrupts = <4>;
|
||||
clocks = <&smbclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
compact-flash@1a000 {
|
||||
|
|
@ -197,6 +230,8 @@ clcd@1f000 {
|
|||
compatible = "arm,pl111", "arm,primecell";
|
||||
reg = <0x1f000 0x1000>;
|
||||
interrupts = <14>;
|
||||
clocks = <&v2m_oscclk1>, <&smbclk>;
|
||||
clock-names = "clcdclk", "apb_pclk";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -207,5 +242,98 @@ v2m_fixed_3v3: fixedregulator@0 {
|
|||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
v2m_clk24mhz: clk24mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "v2m:clk24mhz";
|
||||
};
|
||||
|
||||
v2m_refclk1mhz: refclk1mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <1000000>;
|
||||
clock-output-names = "v2m:refclk1mhz";
|
||||
};
|
||||
|
||||
v2m_refclk32khz: refclk32khz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "v2m:refclk32khz";
|
||||
};
|
||||
|
||||
mcc {
|
||||
compatible = "arm,vexpress,config-bus";
|
||||
arm,vexpress,config-bridge = <&v2m_sysreg>;
|
||||
|
||||
osc@0 {
|
||||
/* MCC static memory clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 0>;
|
||||
freq-range = <25000000 60000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "v2m:oscclk0";
|
||||
};
|
||||
|
||||
v2m_oscclk1: osc@1 {
|
||||
/* CLCD clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 1>;
|
||||
freq-range = <23750000 63500000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "v2m:oscclk1";
|
||||
};
|
||||
|
||||
v2m_oscclk2: osc@2 {
|
||||
/* IO FPGA peripheral clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 2>;
|
||||
freq-range = <24000000 24000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "v2m:oscclk2";
|
||||
};
|
||||
|
||||
volt@0 {
|
||||
/* Logic level voltage */
|
||||
compatible = "arm,vexpress-volt";
|
||||
arm,vexpress-sysreg,func = <2 0>;
|
||||
regulator-name = "VIO";
|
||||
regulator-always-on;
|
||||
label = "VIO";
|
||||
};
|
||||
|
||||
temp@0 {
|
||||
/* MCC internal operating temperature */
|
||||
compatible = "arm,vexpress-temp";
|
||||
arm,vexpress-sysreg,func = <4 0>;
|
||||
label = "MCC";
|
||||
};
|
||||
|
||||
reset@0 {
|
||||
compatible = "arm,vexpress-reset";
|
||||
arm,vexpress-sysreg,func = <5 0>;
|
||||
};
|
||||
|
||||
muxfpga@0 {
|
||||
compatible = "arm,vexpress-muxfpga";
|
||||
arm,vexpress-sysreg,func = <7 0>;
|
||||
};
|
||||
|
||||
shutdown@0 {
|
||||
compatible = "arm,vexpress-shutdown";
|
||||
arm,vexpress-sysreg,func = <8 0>;
|
||||
};
|
||||
|
||||
reboot@0 {
|
||||
compatible = "arm,vexpress-reboot";
|
||||
arm,vexpress-sysreg,func = <9 0>;
|
||||
};
|
||||
|
||||
dvimode@0 {
|
||||
compatible = "arm,vexpress-dvimode";
|
||||
arm,vexpress-sysreg,func = <11 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@
|
|||
/ {
|
||||
model = "V2P-CA15";
|
||||
arm,hbi = <0x237>;
|
||||
arm,vexpress,site = <0xf>;
|
||||
compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
|
|
@ -54,17 +55,24 @@ hdlcd@2b000000 {
|
|||
compatible = "arm,hdlcd";
|
||||
reg = <0 0x2b000000 0 0x1000>;
|
||||
interrupts = <0 85 4>;
|
||||
clocks = <&oscclk5>;
|
||||
clock-names = "pxlclk";
|
||||
};
|
||||
|
||||
memory-controller@2b0a0000 {
|
||||
compatible = "arm,pl341", "arm,primecell";
|
||||
reg = <0 0x2b0a0000 0 0x1000>;
|
||||
clocks = <&oscclk7>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
wdt@2b060000 {
|
||||
compatible = "arm,sp805", "arm,primecell";
|
||||
status = "disabled";
|
||||
reg = <0 0x2b060000 0 0x1000>;
|
||||
interrupts = <98>;
|
||||
clocks = <&oscclk7>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@2c001000 {
|
||||
|
|
@ -84,6 +92,8 @@ memory-controller@7ffd0000 {
|
|||
reg = <0 0x7ffd0000 0 0x1000>;
|
||||
interrupts = <0 86 4>,
|
||||
<0 87 4>;
|
||||
clocks = <&oscclk7>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
dma@7ffb0000 {
|
||||
|
|
@ -94,6 +104,8 @@ dma@7ffb0000 {
|
|||
<0 89 4>,
|
||||
<0 90 4>,
|
||||
<0 91 4>;
|
||||
clocks = <&oscclk7>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
timer {
|
||||
|
|
@ -110,7 +122,109 @@ pmu {
|
|||
<0 69 4>;
|
||||
};
|
||||
|
||||
motherboard {
|
||||
dcc {
|
||||
compatible = "arm,vexpress,config-bus";
|
||||
arm,vexpress,config-bridge = <&v2m_sysreg>;
|
||||
|
||||
osc@0 {
|
||||
/* CPU PLL reference clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 0>;
|
||||
freq-range = <50000000 60000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk0";
|
||||
};
|
||||
|
||||
osc@4 {
|
||||
/* Multiplexed AXI master clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 4>;
|
||||
freq-range = <20000000 40000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk4";
|
||||
};
|
||||
|
||||
oscclk5: osc@5 {
|
||||
/* HDLCD PLL reference clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 5>;
|
||||
freq-range = <23750000 165000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk5";
|
||||
};
|
||||
|
||||
smbclk: osc@6 {
|
||||
/* SMB clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 6>;
|
||||
freq-range = <20000000 50000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk6";
|
||||
};
|
||||
|
||||
oscclk7: osc@7 {
|
||||
/* SYS PLL reference clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 7>;
|
||||
freq-range = <20000000 60000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk7";
|
||||
};
|
||||
|
||||
osc@8 {
|
||||
/* DDR2 PLL reference clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 8>;
|
||||
freq-range = <40000000 40000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk8";
|
||||
};
|
||||
|
||||
volt@0 {
|
||||
/* CPU core voltage */
|
||||
compatible = "arm,vexpress-volt";
|
||||
arm,vexpress-sysreg,func = <2 0>;
|
||||
regulator-name = "Cores";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1050000>;
|
||||
regulator-always-on;
|
||||
label = "Cores";
|
||||
};
|
||||
|
||||
amp@0 {
|
||||
/* Total current for the two cores */
|
||||
compatible = "arm,vexpress-amp";
|
||||
arm,vexpress-sysreg,func = <3 0>;
|
||||
label = "Cores";
|
||||
};
|
||||
|
||||
temp@0 {
|
||||
/* DCC internal temperature */
|
||||
compatible = "arm,vexpress-temp";
|
||||
arm,vexpress-sysreg,func = <4 0>;
|
||||
label = "DCC";
|
||||
};
|
||||
|
||||
power@0 {
|
||||
/* Total power */
|
||||
compatible = "arm,vexpress-power";
|
||||
arm,vexpress-sysreg,func = <12 0>;
|
||||
label = "Cores";
|
||||
};
|
||||
|
||||
energy@0 {
|
||||
/* Total energy */
|
||||
compatible = "arm,vexpress-energy";
|
||||
arm,vexpress-sysreg,func = <13 0>;
|
||||
label = "Cores";
|
||||
};
|
||||
};
|
||||
|
||||
smb {
|
||||
compatible = "simple-bus";
|
||||
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0 0x08000000 0x04000000>,
|
||||
<1 0 0 0x14000000 0x04000000>,
|
||||
<2 0 0 0x18000000 0x04000000>,
|
||||
|
|
@ -118,6 +232,7 @@ motherboard {
|
|||
<4 0 0 0x0c000000 0x04000000>,
|
||||
<5 0 0 0x10000000 0x04000000>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 63>;
|
||||
interrupt-map = <0 0 0 &gic 0 0 4>,
|
||||
<0 0 1 &gic 0 1 4>,
|
||||
|
|
@ -162,7 +277,7 @@ motherboard {
|
|||
<0 0 40 &gic 0 40 4>,
|
||||
<0 0 41 &gic 0 41 4>,
|
||||
<0 0 42 &gic 0 42 4>;
|
||||
|
||||
/include/ "vexpress-v2m-rs1.dtsi"
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "vexpress-v2m-rs1.dtsi"
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@
|
|||
/ {
|
||||
model = "V2P-CA15_CA7";
|
||||
arm,hbi = <0x249>;
|
||||
arm,vexpress,site = <0xf>;
|
||||
compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
|
|
@ -74,17 +75,23 @@ wdt@2a490000 {
|
|||
compatible = "arm,sp805", "arm,primecell";
|
||||
reg = <0 0x2a490000 0 0x1000>;
|
||||
interrupts = <98>;
|
||||
clocks = <&oscclk6a>, <&oscclk6a>;
|
||||
clock-names = "wdogclk", "apb_pclk";
|
||||
};
|
||||
|
||||
hdlcd@2b000000 {
|
||||
compatible = "arm,hdlcd";
|
||||
reg = <0 0x2b000000 0 0x1000>;
|
||||
interrupts = <0 85 4>;
|
||||
clocks = <&oscclk5>;
|
||||
clock-names = "pxlclk";
|
||||
};
|
||||
|
||||
memory-controller@2b0a0000 {
|
||||
compatible = "arm,pl341", "arm,primecell";
|
||||
reg = <0 0x2b0a0000 0 0x1000>;
|
||||
clocks = <&oscclk6a>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@2c001000 {
|
||||
|
|
@ -104,6 +111,8 @@ memory-controller@7ffd0000 {
|
|||
reg = <0 0x7ffd0000 0 0x1000>;
|
||||
interrupts = <0 86 4>,
|
||||
<0 87 4>;
|
||||
clocks = <&oscclk6a>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
dma@7ff00000 {
|
||||
|
|
@ -114,6 +123,8 @@ dma@7ff00000 {
|
|||
<0 89 4>,
|
||||
<0 90 4>,
|
||||
<0 91 4>;
|
||||
clocks = <&oscclk6a>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
timer {
|
||||
|
|
@ -130,7 +141,175 @@ pmu {
|
|||
<0 69 4>;
|
||||
};
|
||||
|
||||
motherboard {
|
||||
oscclk6a: oscclk6a {
|
||||
/* Reference 24MHz clock */
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "oscclk6a";
|
||||
};
|
||||
|
||||
dcc {
|
||||
compatible = "arm,vexpress,config-bus";
|
||||
arm,vexpress,config-bridge = <&v2m_sysreg>;
|
||||
|
||||
osc@0 {
|
||||
/* A15 PLL 0 reference clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 0>;
|
||||
freq-range = <17000000 50000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk0";
|
||||
};
|
||||
|
||||
osc@1 {
|
||||
/* A15 PLL 1 reference clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 1>;
|
||||
freq-range = <17000000 50000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk1";
|
||||
};
|
||||
|
||||
osc@2 {
|
||||
/* A7 PLL 0 reference clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 2>;
|
||||
freq-range = <17000000 50000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk2";
|
||||
};
|
||||
|
||||
osc@3 {
|
||||
/* A7 PLL 1 reference clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 3>;
|
||||
freq-range = <17000000 50000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk3";
|
||||
};
|
||||
|
||||
osc@4 {
|
||||
/* External AXI master clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 4>;
|
||||
freq-range = <20000000 40000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk4";
|
||||
};
|
||||
|
||||
oscclk5: osc@5 {
|
||||
/* HDLCD PLL reference clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 5>;
|
||||
freq-range = <23750000 165000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk5";
|
||||
};
|
||||
|
||||
smbclk: osc@6 {
|
||||
/* Static memory controller clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 6>;
|
||||
freq-range = <20000000 40000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk6";
|
||||
};
|
||||
|
||||
osc@7 {
|
||||
/* SYS PLL reference clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 7>;
|
||||
freq-range = <17000000 50000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk7";
|
||||
};
|
||||
|
||||
osc@8 {
|
||||
/* DDR2 PLL reference clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 8>;
|
||||
freq-range = <20000000 50000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk8";
|
||||
};
|
||||
|
||||
volt@0 {
|
||||
/* A15 CPU core voltage */
|
||||
compatible = "arm,vexpress-volt";
|
||||
arm,vexpress-sysreg,func = <2 0>;
|
||||
regulator-name = "A15 Vcore";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1050000>;
|
||||
regulator-always-on;
|
||||
label = "A15 Vcore";
|
||||
};
|
||||
|
||||
volt@1 {
|
||||
/* A7 CPU core voltage */
|
||||
compatible = "arm,vexpress-volt";
|
||||
arm,vexpress-sysreg,func = <2 1>;
|
||||
regulator-name = "A7 Vcore";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1050000>;
|
||||
regulator-always-on;
|
||||
label = "A7 Vcore";
|
||||
};
|
||||
|
||||
amp@0 {
|
||||
/* Total current for the two A15 cores */
|
||||
compatible = "arm,vexpress-amp";
|
||||
arm,vexpress-sysreg,func = <3 0>;
|
||||
label = "A15 Icore";
|
||||
};
|
||||
|
||||
amp@1 {
|
||||
/* Total current for the three A7 cores */
|
||||
compatible = "arm,vexpress-amp";
|
||||
arm,vexpress-sysreg,func = <3 1>;
|
||||
label = "A7 Icore";
|
||||
};
|
||||
|
||||
temp@0 {
|
||||
/* DCC internal temperature */
|
||||
compatible = "arm,vexpress-temp";
|
||||
arm,vexpress-sysreg,func = <4 0>;
|
||||
label = "DCC";
|
||||
};
|
||||
|
||||
power@0 {
|
||||
/* Total power for the two A15 cores */
|
||||
compatible = "arm,vexpress-power";
|
||||
arm,vexpress-sysreg,func = <12 0>;
|
||||
label = "A15 Pcore";
|
||||
};
|
||||
power@1 {
|
||||
/* Total power for the three A7 cores */
|
||||
compatible = "arm,vexpress-power";
|
||||
arm,vexpress-sysreg,func = <12 1>;
|
||||
label = "A7 Pcore";
|
||||
};
|
||||
|
||||
energy@0 {
|
||||
/* Total energy for the two A15 cores */
|
||||
compatible = "arm,vexpress-energy";
|
||||
arm,vexpress-sysreg,func = <13 0>;
|
||||
label = "A15 Jcore";
|
||||
};
|
||||
|
||||
energy@2 {
|
||||
/* Total energy for the three A7 cores */
|
||||
compatible = "arm,vexpress-energy";
|
||||
arm,vexpress-sysreg,func = <13 2>;
|
||||
label = "A7 Jcore";
|
||||
};
|
||||
};
|
||||
|
||||
smb {
|
||||
compatible = "simple-bus";
|
||||
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0 0x08000000 0x04000000>,
|
||||
<1 0 0 0x14000000 0x04000000>,
|
||||
<2 0 0 0x18000000 0x04000000>,
|
||||
|
|
@ -138,6 +317,7 @@ motherboard {
|
|||
<4 0 0 0x0c000000 0x04000000>,
|
||||
<5 0 0 0x10000000 0x04000000>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 63>;
|
||||
interrupt-map = <0 0 0 &gic 0 0 4>,
|
||||
<0 0 1 &gic 0 1 4>,
|
||||
|
|
@ -182,7 +362,7 @@ motherboard {
|
|||
<0 0 40 &gic 0 40 4>,
|
||||
<0 0 41 &gic 0 41 4>,
|
||||
<0 0 42 &gic 0 42 4>;
|
||||
|
||||
/include/ "vexpress-v2m-rs1.dtsi"
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "vexpress-v2m-rs1.dtsi"
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@
|
|||
/ {
|
||||
model = "V2P-CA5s";
|
||||
arm,hbi = <0x225>;
|
||||
arm,vexpress,site = <0xf>;
|
||||
compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <1>;
|
||||
|
|
@ -56,11 +57,15 @@ hdlcd@2a110000 {
|
|||
compatible = "arm,hdlcd";
|
||||
reg = <0x2a110000 0x1000>;
|
||||
interrupts = <0 85 4>;
|
||||
clocks = <&oscclk3>;
|
||||
clock-names = "pxlclk";
|
||||
};
|
||||
|
||||
memory-controller@2a150000 {
|
||||
compatible = "arm,pl341", "arm,primecell";
|
||||
reg = <0x2a150000 0x1000>;
|
||||
clocks = <&oscclk1>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
memory-controller@2a190000 {
|
||||
|
|
@ -68,6 +73,8 @@ memory-controller@2a190000 {
|
|||
reg = <0x2a190000 0x1000>;
|
||||
interrupts = <0 86 4>,
|
||||
<0 87 4>;
|
||||
clocks = <&oscclk1>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
scu@2c000000 {
|
||||
|
|
@ -109,7 +116,77 @@ pmu {
|
|||
<0 69 4>;
|
||||
};
|
||||
|
||||
motherboard {
|
||||
dcc {
|
||||
compatible = "arm,vexpress,config-bus";
|
||||
arm,vexpress,config-bridge = <&v2m_sysreg>;
|
||||
|
||||
osc@0 {
|
||||
/* CPU and internal AXI reference clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 0>;
|
||||
freq-range = <50000000 100000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk0";
|
||||
};
|
||||
|
||||
oscclk1: osc@1 {
|
||||
/* Multiplexed AXI master clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 1>;
|
||||
freq-range = <5000000 50000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk1";
|
||||
};
|
||||
|
||||
osc@2 {
|
||||
/* DDR2 */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 2>;
|
||||
freq-range = <80000000 120000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk2";
|
||||
};
|
||||
|
||||
oscclk3: osc@3 {
|
||||
/* HDLCD */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 3>;
|
||||
freq-range = <23750000 165000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk3";
|
||||
};
|
||||
|
||||
osc@4 {
|
||||
/* Test chip gate configuration */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 4>;
|
||||
freq-range = <80000000 80000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk4";
|
||||
};
|
||||
|
||||
smbclk: osc@5 {
|
||||
/* SMB clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 5>;
|
||||
freq-range = <25000000 60000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk5";
|
||||
};
|
||||
|
||||
temp@0 {
|
||||
/* DCC internal operating temperature */
|
||||
compatible = "arm,vexpress-temp";
|
||||
arm,vexpress-sysreg,func = <4 0>;
|
||||
label = "DCC";
|
||||
};
|
||||
};
|
||||
|
||||
smb {
|
||||
compatible = "simple-bus";
|
||||
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x08000000 0x04000000>,
|
||||
<1 0 0x14000000 0x04000000>,
|
||||
<2 0 0x18000000 0x04000000>,
|
||||
|
|
@ -117,6 +194,7 @@ motherboard {
|
|||
<4 0 0x0c000000 0x04000000>,
|
||||
<5 0 0x10000000 0x04000000>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 63>;
|
||||
interrupt-map = <0 0 0 &gic 0 0 4>,
|
||||
<0 0 1 &gic 0 1 4>,
|
||||
|
|
@ -161,7 +239,7 @@ motherboard {
|
|||
<0 0 40 &gic 0 40 4>,
|
||||
<0 0 41 &gic 0 41 4>,
|
||||
<0 0 42 &gic 0 42 4>;
|
||||
|
||||
/include/ "vexpress-v2m-rs1.dtsi"
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "vexpress-v2m-rs1.dtsi"
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@
|
|||
/ {
|
||||
model = "V2P-CA9";
|
||||
arm,hbi = <0x191>;
|
||||
arm,vexpress,site = <0xf>;
|
||||
compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <1>;
|
||||
|
|
@ -70,11 +71,15 @@ clcd@10020000 {
|
|||
compatible = "arm,pl111", "arm,primecell";
|
||||
reg = <0x10020000 0x1000>;
|
||||
interrupts = <0 44 4>;
|
||||
clocks = <&oscclk1>, <&oscclk2>;
|
||||
clock-names = "clcdclk", "apb_pclk";
|
||||
};
|
||||
|
||||
memory-controller@100e0000 {
|
||||
compatible = "arm,pl341", "arm,primecell";
|
||||
reg = <0x100e0000 0x1000>;
|
||||
clocks = <&oscclk2>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
memory-controller@100e1000 {
|
||||
|
|
@ -82,6 +87,8 @@ memory-controller@100e1000 {
|
|||
reg = <0x100e1000 0x1000>;
|
||||
interrupts = <0 45 4>,
|
||||
<0 46 4>;
|
||||
clocks = <&oscclk2>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
timer@100e4000 {
|
||||
|
|
@ -89,12 +96,16 @@ timer@100e4000 {
|
|||
reg = <0x100e4000 0x1000>;
|
||||
interrupts = <0 48 4>,
|
||||
<0 49 4>;
|
||||
clocks = <&oscclk2>, <&oscclk2>;
|
||||
clock-names = "timclk", "apb_pclk";
|
||||
};
|
||||
|
||||
watchdog@100e5000 {
|
||||
compatible = "arm,sp805", "arm,primecell";
|
||||
reg = <0x100e5000 0x1000>;
|
||||
interrupts = <0 51 4>;
|
||||
clocks = <&oscclk2>, <&oscclk2>;
|
||||
clock-names = "wdogclk", "apb_pclk";
|
||||
};
|
||||
|
||||
scu@1e000000 {
|
||||
|
|
@ -140,13 +151,132 @@ pmu {
|
|||
<0 63 4>;
|
||||
};
|
||||
|
||||
motherboard {
|
||||
dcc {
|
||||
compatible = "arm,vexpress,config-bus";
|
||||
arm,vexpress,config-bridge = <&v2m_sysreg>;
|
||||
|
||||
osc@0 {
|
||||
/* ACLK clock to the AXI master port on the test chip */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 0>;
|
||||
freq-range = <30000000 50000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "extsaxiclk";
|
||||
};
|
||||
|
||||
oscclk1: osc@1 {
|
||||
/* Reference clock for the CLCD */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 1>;
|
||||
freq-range = <10000000 80000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "clcdclk";
|
||||
};
|
||||
|
||||
smbclk: oscclk2: osc@2 {
|
||||
/* Reference clock for the test chip internal PLLs */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 2>;
|
||||
freq-range = <33000000 100000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "tcrefclk";
|
||||
};
|
||||
|
||||
volt@0 {
|
||||
/* Test Chip internal logic voltage */
|
||||
compatible = "arm,vexpress-volt";
|
||||
arm,vexpress-sysreg,func = <2 0>;
|
||||
regulator-name = "VD10";
|
||||
regulator-always-on;
|
||||
label = "VD10";
|
||||
};
|
||||
|
||||
volt@1 {
|
||||
/* PL310, L2 cache, RAM cell supply (not PL310 logic) */
|
||||
compatible = "arm,vexpress-volt";
|
||||
arm,vexpress-sysreg,func = <2 1>;
|
||||
regulator-name = "VD10_S2";
|
||||
regulator-always-on;
|
||||
label = "VD10_S2";
|
||||
};
|
||||
|
||||
volt@2 {
|
||||
/* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
|
||||
compatible = "arm,vexpress-volt";
|
||||
arm,vexpress-sysreg,func = <2 2>;
|
||||
regulator-name = "VD10_S3";
|
||||
regulator-always-on;
|
||||
label = "VD10_S3";
|
||||
};
|
||||
|
||||
volt@3 {
|
||||
/* DDR2 SDRAM and Test Chip DDR2 I/O supply */
|
||||
compatible = "arm,vexpress-volt";
|
||||
arm,vexpress-sysreg,func = <2 3>;
|
||||
regulator-name = "VCC1V8";
|
||||
regulator-always-on;
|
||||
label = "VCC1V8";
|
||||
};
|
||||
|
||||
volt@4 {
|
||||
/* DDR2 SDRAM VTT termination voltage */
|
||||
compatible = "arm,vexpress-volt";
|
||||
arm,vexpress-sysreg,func = <2 4>;
|
||||
regulator-name = "DDR2VTT";
|
||||
regulator-always-on;
|
||||
label = "DDR2VTT";
|
||||
};
|
||||
|
||||
volt@5 {
|
||||
/* Local board supply for miscellaneous logic external to the Test Chip */
|
||||
arm,vexpress-sysreg,func = <2 5>;
|
||||
compatible = "arm,vexpress-volt";
|
||||
regulator-name = "VCC3V3";
|
||||
regulator-always-on;
|
||||
label = "VCC3V3";
|
||||
};
|
||||
|
||||
amp@0 {
|
||||
/* PL310, L2 cache, RAM cell supply (not PL310 logic) */
|
||||
compatible = "arm,vexpress-amp";
|
||||
arm,vexpress-sysreg,func = <3 0>;
|
||||
label = "VD10_S2";
|
||||
};
|
||||
|
||||
amp@1 {
|
||||
/* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
|
||||
compatible = "arm,vexpress-amp";
|
||||
arm,vexpress-sysreg,func = <3 1>;
|
||||
label = "VD10_S3";
|
||||
};
|
||||
|
||||
power@0 {
|
||||
/* PL310, L2 cache, RAM cell supply (not PL310 logic) */
|
||||
compatible = "arm,vexpress-power";
|
||||
arm,vexpress-sysreg,func = <12 0>;
|
||||
label = "PVD10_S2";
|
||||
};
|
||||
|
||||
power@1 {
|
||||
/* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
|
||||
compatible = "arm,vexpress-power";
|
||||
arm,vexpress-sysreg,func = <12 1>;
|
||||
label = "PVD10_S3";
|
||||
};
|
||||
};
|
||||
|
||||
smb {
|
||||
compatible = "simple-bus";
|
||||
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x40000000 0x04000000>,
|
||||
<1 0 0x44000000 0x04000000>,
|
||||
<2 0 0x48000000 0x04000000>,
|
||||
<3 0 0x4c000000 0x04000000>,
|
||||
<7 0 0x10000000 0x00020000>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 63>;
|
||||
interrupt-map = <0 0 0 &gic 0 0 4>,
|
||||
<0 0 1 &gic 0 1 4>,
|
||||
|
|
@ -191,7 +321,7 @@ motherboard {
|
|||
<0 0 40 &gic 0 40 4>,
|
||||
<0 0 41 &gic 0 41 4>,
|
||||
<0 0 42 &gic 0 42 4>;
|
||||
|
||||
/include/ "vexpress-v2m.dtsi"
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "vexpress-v2m.dtsi"
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@ CONFIG_LOG_BUF_SHIFT=16
|
|||
# CONFIG_IPC_NS is not set
|
||||
# CONFIG_PID_NS is not set
|
||||
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
|
||||
CONFIG_PERF_EVENTS=y
|
||||
CONFIG_SLAB=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
|
|
|
|||
|
|
@ -66,8 +66,6 @@ CONFIG_TTY_PRINTK=y
|
|||
# CONFIG_FILE_LOCKING is not set
|
||||
# CONFIG_DNOTIFY is not set
|
||||
# CONFIG_INOTIFY_USER is not set
|
||||
# CONFIG_PROC_FS is not set
|
||||
# CONFIG_SYSFS is not set
|
||||
# CONFIG_MISC_FILESYSTEMS is not set
|
||||
CONFIG_PRINTK_TIME=y
|
||||
# CONFIG_ENABLE_WARN_DEPRECATED is not set
|
||||
|
|
|
|||
|
|
@ -0,0 +1,114 @@
|
|||
CONFIG_EXPERIMENTAL=y
|
||||
# CONFIG_LOCALVERSION_AUTO is not set
|
||||
# CONFIG_SWAP is not set
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_BSD_PROCESS_ACCT=y
|
||||
CONFIG_BSD_PROCESS_ACCT_V3=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_LOG_BUF_SHIFT=19
|
||||
CONFIG_CGROUPS=y
|
||||
CONFIG_CGROUP_FREEZER=y
|
||||
CONFIG_CGROUP_DEVICE=y
|
||||
CONFIG_CGROUP_CPUACCT=y
|
||||
CONFIG_RESOURCE_COUNTERS=y
|
||||
CONFIG_CGROUP_SCHED=y
|
||||
CONFIG_BLK_CGROUP=y
|
||||
CONFIG_NAMESPACES=y
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_SYSCTL_SYSCALL=y
|
||||
CONFIG_EMBEDDED=y
|
||||
# CONFIG_COMPAT_BRK is not set
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
CONFIG_EFI_PARTITION=y
|
||||
CONFIG_ARCH_BCM=y
|
||||
CONFIG_ARM_THUMBEE=y
|
||||
CONFIG_ARM_ERRATA_743622=y
|
||||
CONFIG_PREEMPT=y
|
||||
CONFIG_AEABI=y
|
||||
# CONFIG_OABI_COMPAT is not set
|
||||
# CONFIG_COMPACTION is not set
|
||||
CONFIG_ZBOOT_ROM_TEXT=0x0
|
||||
CONFIG_ZBOOT_ROM_BSS=0x0
|
||||
CONFIG_ARM_APPENDED_DTB=y
|
||||
CONFIG_CMDLINE="console=ttyS0,115200n8 mem=128M"
|
||||
CONFIG_CPU_IDLE=y
|
||||
CONFIG_VFP=y
|
||||
CONFIG_NEON=y
|
||||
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
|
||||
CONFIG_PM_RUNTIME=y
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_DEVTMPFS_MOUNT=y
|
||||
CONFIG_PROC_DEVICETREE=y
|
||||
# CONFIG_BLK_DEV is not set
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_CHR_DEV_SG=y
|
||||
CONFIG_SCSI_MULTI_LUN=y
|
||||
CONFIG_SCSI_SCAN_ASYNC=y
|
||||
CONFIG_INPUT_FF_MEMLESS=y
|
||||
CONFIG_INPUT_JOYDEV=y
|
||||
CONFIG_INPUT_EVDEV=y
|
||||
# CONFIG_KEYBOARD_ATKBD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
CONFIG_INPUT_TOUCHSCREEN=y
|
||||
CONFIG_INPUT_MISC=y
|
||||
CONFIG_INPUT_UINPUT=y
|
||||
# CONFIG_SERIO is not set
|
||||
# CONFIG_LEGACY_PTYS is not set
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_SERIAL_8250_EXTENDED=y
|
||||
CONFIG_SERIAL_8250_MANY_PORTS=y
|
||||
CONFIG_SERIAL_8250_SHARE_IRQ=y
|
||||
CONFIG_SERIAL_8250_RSA=y
|
||||
CONFIG_SERIAL_8250_DW=y
|
||||
CONFIG_HW_RANDOM=y
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_VIDEO_OUTPUT_CONTROL=y
|
||||
CONFIG_FB=y
|
||||
CONFIG_BACKLIGHT_LCD_SUPPORT=y
|
||||
CONFIG_LCD_CLASS_DEVICE=y
|
||||
CONFIG_BACKLIGHT_CLASS_DEVICE=y
|
||||
# CONFIG_USB_SUPPORT is not set
|
||||
CONFIG_NEW_LEDS=y
|
||||
CONFIG_LEDS_CLASS=y
|
||||
CONFIG_LEDS_TRIGGERS=y
|
||||
CONFIG_LEDS_TRIGGER_TIMER=y
|
||||
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
|
||||
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_EXT4_FS_POSIX_ACL=y
|
||||
CONFIG_EXT4_FS_SECURITY=y
|
||||
CONFIG_AUTOFS4_FS=y
|
||||
CONFIG_FUSE_FS=y
|
||||
CONFIG_MSDOS_FS=y
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_TMPFS_POSIX_ACL=y
|
||||
CONFIG_CONFIGFS_FS=y
|
||||
# CONFIG_MISC_FILESYSTEMS is not set
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_PRINTK_TIME=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_DEBUG_FS=y
|
||||
CONFIG_DETECT_HUNG_TASK=y
|
||||
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=110
|
||||
CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y
|
||||
CONFIG_DEBUG_INFO=y
|
||||
# CONFIG_FTRACE is not set
|
||||
CONFIG_DEBUG_LL=y
|
||||
CONFIG_CRC_CCITT=y
|
||||
CONFIG_CRC_T10DIF=y
|
||||
CONFIG_CRC_ITU_T=y
|
||||
CONFIG_CRC7=y
|
||||
CONFIG_XZ_DEC=y
|
||||
CONFIG_AVERAGE=y
|
||||
|
|
@ -0,0 +1,90 @@
|
|||
CONFIG_KERNEL_LZMA=y
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_RD_LZMA=y
|
||||
CONFIG_EMBEDDED=y
|
||||
CONFIG_SLOB=y
|
||||
CONFIG_JUMP_LABEL=y
|
||||
# CONFIG_LBDAF is not set
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
# CONFIG_IOSCHED_CFQ is not set
|
||||
CONFIG_ARCH_CLPS711X=y
|
||||
CONFIG_ARCH_AUTCPU12=y
|
||||
CONFIG_ARCH_CDB89712=y
|
||||
CONFIG_ARCH_CLEP7312=y
|
||||
CONFIG_ARCH_EDB7211=y
|
||||
CONFIG_ARCH_P720T=y
|
||||
CONFIG_ARCH_FORTUNET=y
|
||||
CONFIG_AEABI=y
|
||||
CONFIG_ZBOOT_ROM_TEXT=0x0
|
||||
CONFIG_ZBOOT_ROM_BSS=0x0
|
||||
# CONFIG_COREDUMP is not set
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_INET=y
|
||||
# CONFIG_IPV6 is not set
|
||||
CONFIG_IRDA=y
|
||||
CONFIG_IRTTY_SIR=y
|
||||
CONFIG_EP7211_DONGLE=y
|
||||
# CONFIG_WIRELESS is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
CONFIG_MTD_CHAR=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_CFI=y
|
||||
CONFIG_MTD_JEDECPROBE=y
|
||||
CONFIG_MTD_CFI_INTELEXT=y
|
||||
CONFIG_MTD_CFI_AMDSTD=y
|
||||
CONFIG_MTD_CFI_STAA=y
|
||||
CONFIG_MTD_AUTCPU12=y
|
||||
CONFIG_MTD_PLATRAM=y
|
||||
CONFIG_MTD_NAND=y
|
||||
CONFIG_MTD_NAND_GPIO=y
|
||||
CONFIG_NETDEVICES=y
|
||||
# CONFIG_NET_CADENCE is not set
|
||||
# CONFIG_NET_VENDOR_BROADCOM is not set
|
||||
# CONFIG_NET_VENDOR_CHELSIO is not set
|
||||
CONFIG_CS89x0=y
|
||||
CONFIG_CS89x0_PLATFORM=y
|
||||
# CONFIG_NET_VENDOR_FARADAY is not set
|
||||
# CONFIG_NET_VENDOR_INTEL is not set
|
||||
# CONFIG_NET_VENDOR_MARVELL is not set
|
||||
# CONFIG_NET_VENDOR_MICREL is not set
|
||||
# CONFIG_NET_VENDOR_NATSEMI is not set
|
||||
# CONFIG_NET_VENDOR_SEEQ is not set
|
||||
# CONFIG_NET_VENDOR_SMSC is not set
|
||||
# CONFIG_NET_VENDOR_STMICRO is not set
|
||||
# CONFIG_NET_VENDOR_WIZNET is not set
|
||||
# CONFIG_WLAN is not set
|
||||
# CONFIG_INPUT is not set
|
||||
# CONFIG_SERIO is not set
|
||||
# CONFIG_VT is not set
|
||||
CONFIG_SERIAL_CLPS711X_CONSOLE=y
|
||||
# CONFIG_HW_RANDOM is not set
|
||||
CONFIG_SPI=y
|
||||
CONFIG_GPIO_GENERIC_PLATFORM=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_FB=y
|
||||
CONFIG_FB_CLPS711X=y
|
||||
CONFIG_BACKLIGHT_LCD_SUPPORT=y
|
||||
CONFIG_LCD_PLATFORM=y
|
||||
# CONFIG_USB_SUPPORT is not set
|
||||
CONFIG_NEW_LEDS=y
|
||||
CONFIG_LEDS_CLASS=y
|
||||
CONFIG_LEDS_GPIO=y
|
||||
CONFIG_LEDS_TRIGGERS=y
|
||||
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
|
||||
# CONFIG_IOMMU_SUPPORT is not set
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_CRAMFS=y
|
||||
CONFIG_MINIX_FS=y
|
||||
# CONFIG_NETWORK_FILESYSTEMS is not set
|
||||
# CONFIG_FTRACE is not set
|
||||
CONFIG_DEBUG_USER=y
|
||||
CONFIG_DEBUG_LL=y
|
||||
CONFIG_EARLY_PRINTK=y
|
||||
# CONFIG_CRYPTO_ANSI_CPRNG is not set
|
||||
# CONFIG_CRYPTO_HW is not set
|
||||
# CONFIG_CRC32 is not set
|
||||
|
|
@ -1,27 +0,0 @@
|
|||
CONFIG_EXPERIMENTAL=y
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_EXPERT=y
|
||||
# CONFIG_HOTPLUG is not set
|
||||
CONFIG_ARCH_CLPS711X=y
|
||||
CONFIG_ARCH_EDB7211=y
|
||||
CONFIG_ZBOOT_ROM_TEXT=0x0
|
||||
CONFIG_ZBOOT_ROM_BSS=0x0
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_INET=y
|
||||
# CONFIG_IPV6 is not set
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_NETDEVICES=y
|
||||
# CONFIG_INPUT is not set
|
||||
CONFIG_SERIO_LIBPS2=y
|
||||
# CONFIG_VT is not set
|
||||
CONFIG_SERIAL_CLPS711X=y
|
||||
CONFIG_SERIAL_CLPS711X_CONSOLE=y
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_MINIX_FS=y
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
# CONFIG_MSDOS_PARTITION is not set
|
||||
CONFIG_DEBUG_USER=y
|
||||
|
|
@ -1,28 +0,0 @@
|
|||
CONFIG_EXPERIMENTAL=y
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_EXPERT=y
|
||||
# CONFIG_HOTPLUG is not set
|
||||
CONFIG_ARCH_CLPS711X=y
|
||||
CONFIG_ARCH_FORTUNET=y
|
||||
# CONFIG_ARM_THUMB is not set
|
||||
CONFIG_ZBOOT_ROM_TEXT=0x0
|
||||
CONFIG_ZBOOT_ROM_BSS=0x0
|
||||
CONFIG_FPE_FASTFPE=y
|
||||
CONFIG_BINFMT_AOUT=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_CHAR=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_CFI=y
|
||||
CONFIG_MTD_CFI_INTELEXT=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
# CONFIG_INPUT is not set
|
||||
# CONFIG_SERIO is not set
|
||||
# CONFIG_VT is not set
|
||||
CONFIG_SERIAL_CLPS711X=y
|
||||
CONFIG_SERIAL_CLPS711X_CONSOLE=y
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_DEBUG_USER=y
|
||||
|
|
@ -69,6 +69,8 @@ CONFIG_SERIAL_SH_SCI=y
|
|||
CONFIG_SERIAL_SH_SCI_NR_UARTS=6
|
||||
CONFIG_SERIAL_SH_SCI_CONSOLE=y
|
||||
# CONFIG_HW_RANDOM is not set
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_RCAR=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_THERMAL=y
|
||||
|
|
|
|||
|
|
@ -80,6 +80,10 @@ CONFIG_RFKILL_GPIO=y
|
|||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_DEVTMPFS_MOUNT=y
|
||||
# CONFIG_FIRMWARE_IN_KERNEL is not set
|
||||
CONFIG_CMA=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_CHAR=y
|
||||
CONFIG_MTD_M25P80=y
|
||||
CONFIG_PROC_DEVICETREE=y
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_AD525X_DPOT=y
|
||||
|
|
@ -98,12 +102,12 @@ CONFIG_USB_PEGASUS=y
|
|||
CONFIG_USB_USBNET=y
|
||||
CONFIG_USB_NET_SMSC75XX=y
|
||||
CONFIG_USB_NET_SMSC95XX=y
|
||||
CONFIG_BRCMFMAC=m
|
||||
CONFIG_RT2X00=y
|
||||
CONFIG_RT2800USB=m
|
||||
CONFIG_INPUT_EVDEV=y
|
||||
CONFIG_INPUT_MISC=y
|
||||
CONFIG_INPUT_MPU3050=y
|
||||
# CONFIG_VT is not set
|
||||
# CONFIG_LEGACY_PTYS is not set
|
||||
# CONFIG_DEVKMEM is not set
|
||||
CONFIG_SERIAL_8250=y
|
||||
|
|
@ -116,7 +120,8 @@ CONFIG_I2C_MUX=y
|
|||
CONFIG_I2C_MUX_PINCTRL=y
|
||||
CONFIG_I2C_TEGRA=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_TEGRA=y
|
||||
CONFIG_SPI_TEGRA20_SFLASH=y
|
||||
CONFIG_SPI_TEGRA20_SLINK=y
|
||||
CONFIG_GPIO_PCA953X_IRQ=y
|
||||
CONFIG_GPIO_TPS6586X=y
|
||||
CONFIG_GPIO_TPS65910=y
|
||||
|
|
@ -138,6 +143,15 @@ CONFIG_MEDIA_SUPPORT=y
|
|||
CONFIG_MEDIA_CAMERA_SUPPORT=y
|
||||
CONFIG_MEDIA_USB_SUPPORT=y
|
||||
CONFIG_USB_VIDEO_CLASS=m
|
||||
CONFIG_DRM=y
|
||||
CONFIG_DRM_TEGRA=y
|
||||
CONFIG_BACKLIGHT_LCD_SUPPORT=y
|
||||
# CONFIG_LCD_CLASS_DEVICE is not set
|
||||
CONFIG_BACKLIGHT_CLASS_DEVICE=y
|
||||
# CONFIG_BACKLIGHT_GENERIC is not set
|
||||
CONFIG_BACKLIGHT_PWM=y
|
||||
CONFIG_FRAMEBUFFER_CONSOLE=y
|
||||
CONFIG_LOGO=y
|
||||
CONFIG_SOUND=y
|
||||
CONFIG_SND=y
|
||||
# CONFIG_SND_SUPPORT_OLD_API is not set
|
||||
|
|
@ -205,6 +219,9 @@ CONFIG_EXT4_FS=y
|
|||
CONFIG_VFAT_FS=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_TMPFS_POSIX_ACL=y
|
||||
CONFIG_SQUASHFS=y
|
||||
CONFIG_SQUASHFS_LZO=y
|
||||
CONFIG_SQUASHFS_XZ=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
|
|
|
|||
|
|
@ -50,12 +50,6 @@
|
|||
#define SCPCELLID2 0xFF8
|
||||
#define SCPCELLID3 0xFFC
|
||||
|
||||
#define SCCTRL_TIMEREN0SEL_REFCLK (0 << 15)
|
||||
#define SCCTRL_TIMEREN0SEL_TIMCLK (1 << 15)
|
||||
|
||||
#define SCCTRL_TIMEREN1SEL_REFCLK (0 << 17)
|
||||
#define SCCTRL_TIMEREN1SEL_TIMCLK (1 << 17)
|
||||
|
||||
#define SCCTRL_TIMERENnSEL_SHIFT(n) (15 + ((n) * 2))
|
||||
|
||||
static inline void sysctl_soft_reset(void __iomem *base)
|
||||
|
|
|
|||
|
|
@ -40,6 +40,13 @@ extern void iotable_init(struct map_desc *, int);
|
|||
extern void vm_reserve_area_early(unsigned long addr, unsigned long size,
|
||||
void *caller);
|
||||
|
||||
#ifdef CONFIG_DEBUG_LL
|
||||
extern void debug_ll_addr(unsigned long *paddr, unsigned long *vaddr);
|
||||
extern void debug_ll_io_init(void);
|
||||
#else
|
||||
static inline void debug_ll_io_init(void) {}
|
||||
#endif
|
||||
|
||||
struct mem_type;
|
||||
extern const struct mem_type *get_mem_type(unsigned int type);
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -0,0 +1,27 @@
|
|||
/*
|
||||
* Early serial output macro for Allwinner A1X SoCs
|
||||
*
|
||||
* Copyright (C) 2012 Maxime Ripard
|
||||
*
|
||||
* Maxime Ripard <maxime.ripard@free-electrons.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_DEBUG_SUNXI_UART0)
|
||||
#define SUNXI_UART_DEBUG_PHYS_BASE 0x01c28000
|
||||
#define SUNXI_UART_DEBUG_VIRT_BASE 0xf1c28000
|
||||
#elif defined(CONFIG_DEBUG_SUNXI_UART1)
|
||||
#define SUNXI_UART_DEBUG_PHYS_BASE 0x01c28400
|
||||
#define SUNXI_UART_DEBUG_VIRT_BASE 0xf1c28400
|
||||
#endif
|
||||
|
||||
.macro addruart, rp, rv, tmp
|
||||
ldr \rp, =SUNXI_UART_DEBUG_PHYS_BASE
|
||||
ldr \rv, =SUNXI_UART_DEBUG_VIRT_BASE
|
||||
.endm
|
||||
|
||||
#define UART_SHIFT 2
|
||||
#include <asm/hardware/debug-8250.S>
|
||||
|
|
@ -100,6 +100,13 @@ ENTRY(printch)
|
|||
b 1b
|
||||
ENDPROC(printch)
|
||||
|
||||
ENTRY(debug_ll_addr)
|
||||
addruart r2, r3, ip
|
||||
str r2, [r0]
|
||||
str r3, [r1]
|
||||
mov pc, lr
|
||||
ENDPROC(debug_ll_addr)
|
||||
|
||||
#else
|
||||
|
||||
ENTRY(printascii)
|
||||
|
|
@ -119,4 +126,11 @@ ENTRY(printch)
|
|||
mov pc, lr
|
||||
ENDPROC(printch)
|
||||
|
||||
ENTRY(debug_ll_addr)
|
||||
mov r2, #0
|
||||
str r2, [r0]
|
||||
str r2, [r1]
|
||||
mov pc, lr
|
||||
ENDPROC(debug_ll_addr)
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -390,10 +390,8 @@ void __init twd_local_timer_of_register(void)
|
|||
int err;
|
||||
|
||||
np = of_find_matching_node(NULL, twd_of_match);
|
||||
if (!np) {
|
||||
err = -ENODEV;
|
||||
goto out;
|
||||
}
|
||||
if (!np)
|
||||
return;
|
||||
|
||||
twd_ppi = irq_of_parse_and_map(np, 0);
|
||||
if (!twd_ppi) {
|
||||
|
|
|
|||
|
|
@ -0,0 +1,19 @@
|
|||
config ARCH_BCM
|
||||
bool "Broadcom SoC" if ARCH_MULTI_V7
|
||||
depends on MMU
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select ARM_ERRATA_754322
|
||||
select ARM_ERRATA_764369 if SMP
|
||||
select ARM_GIC
|
||||
select CPU_V7
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select GENERIC_GPIO
|
||||
select GENERIC_TIME
|
||||
select GPIO_BCM
|
||||
select SPARSE_IRQ
|
||||
select TICK_ONESHOT
|
||||
help
|
||||
This enables support for system based on Broadcom SoCs.
|
||||
It currently supports the 'BCM281XX' family, which includes
|
||||
BCM11130, BCM11140, BCM11351, BCM28145 and
|
||||
BCM28155 variants.
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
#
|
||||
# Copyright (C) 2012 Broadcom Corporation
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation version 2.
|
||||
#
|
||||
# This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
# kind, whether express or implied; without even the implied warranty
|
||||
# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
|
||||
obj-$(CONFIG_ARCH_BCM) := board_bcm.o
|
||||
|
|
@ -0,0 +1,57 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Broadcom Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
|
||||
#include <asm/mach/time.h>
|
||||
|
||||
static const struct of_device_id irq_match[] = {
|
||||
{.compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
|
||||
{}
|
||||
};
|
||||
|
||||
static void timer_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
static struct sys_timer timer = {
|
||||
.init = timer_init,
|
||||
};
|
||||
|
||||
static void __init init_irq(void)
|
||||
{
|
||||
of_irq_init(irq_match);
|
||||
}
|
||||
|
||||
static void __init board_init(void)
|
||||
{
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL,
|
||||
&platform_bus);
|
||||
}
|
||||
|
||||
static const char * const bcm11351_dt_compat[] = { "bcm,bcm11351", NULL, };
|
||||
|
||||
DT_MACHINE_START(BCM11351_DT, "Broadcom Application Processor")
|
||||
.init_irq = init_irq,
|
||||
.timer = &timer,
|
||||
.init_machine = board_init,
|
||||
.dt_compat = bcm11351_dt_compat,
|
||||
.handle_irq = gic_handle_irq,
|
||||
MACHINE_END
|
||||
|
|
@ -12,8 +12,10 @@
|
|||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/delay.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/irqchip/bcm2835.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/bcm2835_timer.h>
|
||||
#include <linux/clk/bcm2835.h>
|
||||
|
|
@ -23,6 +25,48 @@
|
|||
|
||||
#include <mach/bcm2835_soc.h>
|
||||
|
||||
#define PM_RSTC 0x1c
|
||||
#define PM_WDOG 0x24
|
||||
|
||||
#define PM_PASSWORD 0x5a000000
|
||||
#define PM_RSTC_WRCFG_MASK 0x00000030
|
||||
#define PM_RSTC_WRCFG_FULL_RESET 0x00000020
|
||||
|
||||
static void __iomem *wdt_regs;
|
||||
|
||||
/*
|
||||
* The machine restart method can be called from an atomic context so we won't
|
||||
* be able to ioremap the regs then.
|
||||
*/
|
||||
static void bcm2835_setup_restart(void)
|
||||
{
|
||||
struct device_node *np = of_find_compatible_node(NULL, NULL,
|
||||
"brcm,bcm2835-pm-wdt");
|
||||
if (WARN(!np, "unable to setup watchdog restart"))
|
||||
return;
|
||||
|
||||
wdt_regs = of_iomap(np, 0);
|
||||
WARN(!wdt_regs, "failed to remap watchdog regs");
|
||||
}
|
||||
|
||||
static void bcm2835_restart(char mode, const char *cmd)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
if (!wdt_regs)
|
||||
return;
|
||||
|
||||
/* use a timeout of 10 ticks (~150us) */
|
||||
writel_relaxed(10 | PM_PASSWORD, wdt_regs + PM_WDOG);
|
||||
val = readl_relaxed(wdt_regs + PM_RSTC);
|
||||
val &= ~PM_RSTC_WRCFG_MASK;
|
||||
val |= PM_PASSWORD | PM_RSTC_WRCFG_FULL_RESET;
|
||||
writel_relaxed(val, wdt_regs + PM_RSTC);
|
||||
|
||||
/* No sleeping, possibly atomic. */
|
||||
mdelay(1);
|
||||
}
|
||||
|
||||
static struct map_desc io_map __initdata = {
|
||||
.virtual = BCM2835_PERIPH_VIRT,
|
||||
.pfn = __phys_to_pfn(BCM2835_PERIPH_PHYS),
|
||||
|
|
@ -39,6 +83,7 @@ static void __init bcm2835_init(void)
|
|||
{
|
||||
int ret;
|
||||
|
||||
bcm2835_setup_restart();
|
||||
bcm2835_init_clocks();
|
||||
|
||||
ret = of_platform_populate(NULL, of_default_bus_match_table, NULL,
|
||||
|
|
@ -60,5 +105,6 @@ DT_MACHINE_START(BCM2835, "BCM2835")
|
|||
.handle_irq = bcm2835_handle_irq,
|
||||
.init_machine = bcm2835_init,
|
||||
.timer = &bcm2835_timer,
|
||||
.restart = bcm2835_restart,
|
||||
.dt_compat = bcm2835_compat
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -0,0 +1 @@
|
|||
/* empty */
|
||||
|
|
@ -10,7 +10,6 @@ config ARCH_AUTCPU12
|
|||
|
||||
config ARCH_CDB89712
|
||||
bool "CDB89712"
|
||||
select ISA
|
||||
help
|
||||
This is an evaluation board from Cirrus for the CS89712 processor.
|
||||
The board includes 2 serial ports, Ethernet, IRDA, and expansion
|
||||
|
|
@ -25,7 +24,6 @@ config ARCH_EDB7211
|
|||
bool "EDB7211"
|
||||
select ARCH_SELECT_MEMORY_MODEL
|
||||
select ARCH_SPARSEMEM_ENABLE
|
||||
select ISA
|
||||
help
|
||||
Say Y here if you intend to run this kernel on a Cirrus Logic EDB-7211
|
||||
evaluation board.
|
||||
|
|
|
|||
|
|
@ -9,9 +9,9 @@ obj-m :=
|
|||
obj-n :=
|
||||
obj- :=
|
||||
|
||||
obj-$(CONFIG_ARCH_AUTCPU12) += autcpu12.o
|
||||
obj-$(CONFIG_ARCH_CDB89712) += cdb89712.o
|
||||
obj-$(CONFIG_ARCH_CLEP7312) += clep7312.o
|
||||
obj-$(CONFIG_ARCH_EDB7211) += edb7211-arch.o edb7211-mm.o
|
||||
obj-$(CONFIG_ARCH_FORTUNET) += fortunet.o
|
||||
obj-$(CONFIG_ARCH_P720T) += p720t.o
|
||||
obj-$(CONFIG_ARCH_AUTCPU12) += board-autcpu12.o
|
||||
obj-$(CONFIG_ARCH_CDB89712) += board-cdb89712.o
|
||||
obj-$(CONFIG_ARCH_CLEP7312) += board-clep7312.o
|
||||
obj-$(CONFIG_ARCH_EDB7211) += board-edb7211.o
|
||||
obj-$(CONFIG_ARCH_FORTUNET) += board-fortunet.o
|
||||
obj-$(CONFIG_ARCH_P720T) += board-p720t.o
|
||||
|
|
|
|||
|
|
@ -1,5 +1,4 @@
|
|||
# The standard locations for stuff on CLPS711x type processors
|
||||
zreladdr-y += 0xc0028000
|
||||
params_phys-y := 0xc0000100
|
||||
# Should probably have some agreement on these...
|
||||
initrd_phys-$(CONFIG_ARCH_P720T) := 0xc0400000
|
||||
|
|
|
|||
|
|
@ -1,92 +0,0 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-clps711x/autcpu12.c
|
||||
*
|
||||
* (c) 2001 Thomas Gleixner, autronix automation <gleixner@autronix.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/sizes.h>
|
||||
#include <asm/setup.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/page.h>
|
||||
|
||||
#include <asm/mach/map.h>
|
||||
#include <mach/autcpu12.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
/*
|
||||
* The on-chip registers are given a size of 1MB so that a section can
|
||||
* be used to map them; this saves a page table. This is the place to
|
||||
* add mappings for ROM, expansion memory, PCMCIA, etc. (if static
|
||||
* mappings are chosen for those areas).
|
||||
*
|
||||
*/
|
||||
|
||||
static struct map_desc autcpu12_io_desc[] __initdata = {
|
||||
/* memory-mapped extra io and CS8900A Ethernet chip */
|
||||
/* ethernet chip */
|
||||
{
|
||||
.virtual = AUTCPU12_VIRT_CS8900A,
|
||||
.pfn = __phys_to_pfn(AUTCPU12_PHYS_CS8900A),
|
||||
.length = SZ_1M,
|
||||
.type = MT_DEVICE
|
||||
}
|
||||
};
|
||||
|
||||
void __init autcpu12_map_io(void)
|
||||
{
|
||||
clps711x_map_io();
|
||||
iotable_init(autcpu12_io_desc, ARRAY_SIZE(autcpu12_io_desc));
|
||||
}
|
||||
|
||||
static struct resource autcpu12_nvram_resource[] __initdata = {
|
||||
DEFINE_RES_MEM_NAMED(AUTCPU12_PHYS_NVRAM, SZ_128K, "SRAM"),
|
||||
};
|
||||
|
||||
static struct platform_device autcpu12_nvram_pdev __initdata = {
|
||||
.name = "autcpu12_nvram",
|
||||
.id = -1,
|
||||
.resource = autcpu12_nvram_resource,
|
||||
.num_resources = ARRAY_SIZE(autcpu12_nvram_resource),
|
||||
};
|
||||
|
||||
static void __init autcpu12_init(void)
|
||||
{
|
||||
platform_device_register(&autcpu12_nvram_pdev);
|
||||
}
|
||||
|
||||
MACHINE_START(AUTCPU12, "autronix autcpu12")
|
||||
/* Maintainer: Thomas Gleixner */
|
||||
.atag_offset = 0x20000,
|
||||
.init_machine = autcpu12_init,
|
||||
.map_io = autcpu12_map_io,
|
||||
.init_irq = clps711x_init_irq,
|
||||
.timer = &clps711x_timer,
|
||||
.restart = clps711x_restart,
|
||||
MACHINE_END
|
||||
|
||||
|
|
@ -0,0 +1,179 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-clps711x/autcpu12.c
|
||||
*
|
||||
* (c) 2001 Thomas Gleixner, autronix automation <gleixner@autronix.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/mtd/partitions.h>
|
||||
#include <linux/mtd/nand-gpio.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/basic_mmio_gpio.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/sizes.h>
|
||||
#include <asm/setup.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/page.h>
|
||||
|
||||
#include <asm/mach/map.h>
|
||||
#include <mach/autcpu12.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
#define AUTCPU12_CS8900_BASE (CS2_PHYS_BASE + 0x300)
|
||||
#define AUTCPU12_CS8900_IRQ (IRQ_EINT3)
|
||||
|
||||
#define AUTCPU12_SMC_BASE (CS1_PHYS_BASE + 0x06000000)
|
||||
#define AUTCPU12_SMC_SEL_BASE (AUTCPU12_SMC_BASE + 0x10)
|
||||
|
||||
#define AUTCPU12_MMGPIO_BASE (CLPS711X_NR_GPIO)
|
||||
#define AUTCPU12_SMC_NCE (AUTCPU12_MMGPIO_BASE + 0) /* Bit 0 */
|
||||
#define AUTCPU12_SMC_RDY CLPS711X_GPIO(1, 2)
|
||||
#define AUTCPU12_SMC_ALE CLPS711X_GPIO(1, 3)
|
||||
#define AUTCPU12_SMC_CLE CLPS711X_GPIO(1, 3)
|
||||
|
||||
static struct resource autcpu12_cs8900_resource[] __initdata = {
|
||||
DEFINE_RES_MEM(AUTCPU12_CS8900_BASE, SZ_1K),
|
||||
DEFINE_RES_IRQ(AUTCPU12_CS8900_IRQ),
|
||||
};
|
||||
|
||||
static struct resource autcpu12_nvram_resource[] __initdata = {
|
||||
DEFINE_RES_MEM_NAMED(AUTCPU12_PHYS_NVRAM, SZ_128K, "SRAM"),
|
||||
};
|
||||
|
||||
static struct platform_device autcpu12_nvram_pdev __initdata = {
|
||||
.name = "autcpu12_nvram",
|
||||
.id = -1,
|
||||
.resource = autcpu12_nvram_resource,
|
||||
.num_resources = ARRAY_SIZE(autcpu12_nvram_resource),
|
||||
};
|
||||
|
||||
static struct resource autcpu12_nand_resource[] __initdata = {
|
||||
DEFINE_RES_MEM(AUTCPU12_SMC_BASE, SZ_16),
|
||||
};
|
||||
|
||||
static struct mtd_partition autcpu12_nand_parts[] __initdata = {
|
||||
{
|
||||
.name = "Flash partition 1",
|
||||
.offset = 0,
|
||||
.size = SZ_8M,
|
||||
},
|
||||
{
|
||||
.name = "Flash partition 2",
|
||||
.offset = MTDPART_OFS_APPEND,
|
||||
.size = MTDPART_SIZ_FULL,
|
||||
},
|
||||
};
|
||||
|
||||
static void __init autcpu12_adjust_parts(struct gpio_nand_platdata *pdata,
|
||||
size_t sz)
|
||||
{
|
||||
switch (sz) {
|
||||
case SZ_16M:
|
||||
case SZ_32M:
|
||||
break;
|
||||
case SZ_64M:
|
||||
case SZ_128M:
|
||||
pdata->parts[0].size = SZ_16M;
|
||||
break;
|
||||
default:
|
||||
pr_warn("Unsupported SmartMedia device size %u\n", sz);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static struct gpio_nand_platdata autcpu12_nand_pdata __initdata = {
|
||||
.gpio_rdy = AUTCPU12_SMC_RDY,
|
||||
.gpio_nce = AUTCPU12_SMC_NCE,
|
||||
.gpio_ale = AUTCPU12_SMC_ALE,
|
||||
.gpio_cle = AUTCPU12_SMC_CLE,
|
||||
.gpio_nwp = -1,
|
||||
.chip_delay = 20,
|
||||
.parts = autcpu12_nand_parts,
|
||||
.num_parts = ARRAY_SIZE(autcpu12_nand_parts),
|
||||
.adjust_parts = autcpu12_adjust_parts,
|
||||
};
|
||||
|
||||
static struct platform_device autcpu12_nand_pdev __initdata = {
|
||||
.name = "gpio-nand",
|
||||
.id = -1,
|
||||
.resource = autcpu12_nand_resource,
|
||||
.num_resources = ARRAY_SIZE(autcpu12_nand_resource),
|
||||
.dev = {
|
||||
.platform_data = &autcpu12_nand_pdata,
|
||||
},
|
||||
};
|
||||
|
||||
static struct resource autcpu12_mmgpio_resource[] __initdata = {
|
||||
DEFINE_RES_MEM_NAMED(AUTCPU12_SMC_SEL_BASE, SZ_1, "dat"),
|
||||
};
|
||||
|
||||
static struct bgpio_pdata autcpu12_mmgpio_pdata __initdata = {
|
||||
.base = AUTCPU12_MMGPIO_BASE,
|
||||
.ngpio = 8,
|
||||
};
|
||||
|
||||
static struct platform_device autcpu12_mmgpio_pdev __initdata = {
|
||||
.name = "basic-mmio-gpio",
|
||||
.id = -1,
|
||||
.resource = autcpu12_mmgpio_resource,
|
||||
.num_resources = ARRAY_SIZE(autcpu12_mmgpio_resource),
|
||||
.dev = {
|
||||
.platform_data = &autcpu12_mmgpio_pdata,
|
||||
},
|
||||
};
|
||||
|
||||
static void __init autcpu12_init(void)
|
||||
{
|
||||
platform_device_register_simple("video-clps711x", 0, NULL, 0);
|
||||
platform_device_register_simple("cs89x0", 0, autcpu12_cs8900_resource,
|
||||
ARRAY_SIZE(autcpu12_cs8900_resource));
|
||||
platform_device_register(&autcpu12_mmgpio_pdev);
|
||||
platform_device_register(&autcpu12_nvram_pdev);
|
||||
}
|
||||
|
||||
static void __init autcpu12_init_late(void)
|
||||
{
|
||||
if (IS_ENABLED(MTD_NAND_GPIO) && IS_ENABLED(GPIO_GENERIC_PLATFORM)) {
|
||||
/* We are need both drivers to handle NAND */
|
||||
platform_device_register(&autcpu12_nand_pdev);
|
||||
}
|
||||
}
|
||||
|
||||
MACHINE_START(AUTCPU12, "autronix autcpu12")
|
||||
/* Maintainer: Thomas Gleixner */
|
||||
.atag_offset = 0x20000,
|
||||
.nr_irqs = CLPS711X_NR_IRQS,
|
||||
.map_io = clps711x_map_io,
|
||||
.init_irq = clps711x_init_irq,
|
||||
.timer = &clps711x_timer,
|
||||
.init_machine = autcpu12_init,
|
||||
.init_late = autcpu12_init_late,
|
||||
.handle_irq = clps711x_handle_irq,
|
||||
.restart = clps711x_restart,
|
||||
MACHINE_END
|
||||
|
||||
|
|
@ -0,0 +1,147 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-clps711x/cdb89712.c
|
||||
*
|
||||
* Copyright (C) 2000-2001 Deep Blue Solutions Ltd
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <linux/mtd/physmap.h>
|
||||
#include <linux/mtd/plat-ram.h>
|
||||
#include <linux/mtd/partitions.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/setup.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
#define CDB89712_CS8900_BASE (CS2_PHYS_BASE + 0x300)
|
||||
#define CDB89712_CS8900_IRQ (IRQ_EINT3)
|
||||
|
||||
static struct resource cdb89712_cs8900_resource[] __initdata = {
|
||||
DEFINE_RES_MEM(CDB89712_CS8900_BASE, SZ_1K),
|
||||
DEFINE_RES_IRQ(CDB89712_CS8900_IRQ),
|
||||
};
|
||||
|
||||
static struct mtd_partition cdb89712_flash_partitions[] __initdata = {
|
||||
{
|
||||
.name = "Flash",
|
||||
.offset = 0,
|
||||
.size = MTDPART_SIZ_FULL,
|
||||
},
|
||||
};
|
||||
|
||||
static struct physmap_flash_data cdb89712_flash_pdata __initdata = {
|
||||
.width = 4,
|
||||
.probe_type = "map_rom",
|
||||
.parts = cdb89712_flash_partitions,
|
||||
.nr_parts = ARRAY_SIZE(cdb89712_flash_partitions),
|
||||
};
|
||||
|
||||
static struct resource cdb89712_flash_resources[] __initdata = {
|
||||
DEFINE_RES_MEM(CS0_PHYS_BASE, SZ_8M),
|
||||
};
|
||||
|
||||
static struct platform_device cdb89712_flash_pdev __initdata = {
|
||||
.name = "physmap-flash",
|
||||
.id = 0,
|
||||
.resource = cdb89712_flash_resources,
|
||||
.num_resources = ARRAY_SIZE(cdb89712_flash_resources),
|
||||
.dev = {
|
||||
.platform_data = &cdb89712_flash_pdata,
|
||||
},
|
||||
};
|
||||
|
||||
static struct mtd_partition cdb89712_bootrom_partitions[] __initdata = {
|
||||
{
|
||||
.name = "BootROM",
|
||||
.offset = 0,
|
||||
.size = MTDPART_SIZ_FULL,
|
||||
},
|
||||
};
|
||||
|
||||
static struct physmap_flash_data cdb89712_bootrom_pdata __initdata = {
|
||||
.width = 4,
|
||||
.probe_type = "map_rom",
|
||||
.parts = cdb89712_bootrom_partitions,
|
||||
.nr_parts = ARRAY_SIZE(cdb89712_bootrom_partitions),
|
||||
};
|
||||
|
||||
static struct resource cdb89712_bootrom_resources[] __initdata = {
|
||||
DEFINE_RES_NAMED(CS7_PHYS_BASE, SZ_128, "BOOTROM", IORESOURCE_MEM |
|
||||
IORESOURCE_CACHEABLE | IORESOURCE_READONLY),
|
||||
};
|
||||
|
||||
static struct platform_device cdb89712_bootrom_pdev __initdata = {
|
||||
.name = "physmap-flash",
|
||||
.id = 1,
|
||||
.resource = cdb89712_bootrom_resources,
|
||||
.num_resources = ARRAY_SIZE(cdb89712_bootrom_resources),
|
||||
.dev = {
|
||||
.platform_data = &cdb89712_bootrom_pdata,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platdata_mtd_ram cdb89712_sram_pdata __initdata = {
|
||||
.bankwidth = 4,
|
||||
};
|
||||
|
||||
static struct resource cdb89712_sram_resources[] __initdata = {
|
||||
DEFINE_RES_MEM(CLPS711X_SRAM_BASE, CLPS711X_SRAM_SIZE),
|
||||
};
|
||||
|
||||
static struct platform_device cdb89712_sram_pdev __initdata = {
|
||||
.name = "mtd-ram",
|
||||
.id = 0,
|
||||
.resource = cdb89712_sram_resources,
|
||||
.num_resources = ARRAY_SIZE(cdb89712_sram_resources),
|
||||
.dev = {
|
||||
.platform_data = &cdb89712_sram_pdata,
|
||||
},
|
||||
};
|
||||
|
||||
static void __init cdb89712_init(void)
|
||||
{
|
||||
platform_device_register(&cdb89712_flash_pdev);
|
||||
platform_device_register(&cdb89712_bootrom_pdev);
|
||||
platform_device_register(&cdb89712_sram_pdev);
|
||||
platform_device_register_simple("cs89x0", 0, cdb89712_cs8900_resource,
|
||||
ARRAY_SIZE(cdb89712_cs8900_resource));
|
||||
}
|
||||
|
||||
MACHINE_START(CDB89712, "Cirrus-CDB89712")
|
||||
/* Maintainer: Ray Lehtiniemi */
|
||||
.atag_offset = 0x100,
|
||||
.nr_irqs = CLPS711X_NR_IRQS,
|
||||
.map_io = clps711x_map_io,
|
||||
.init_irq = clps711x_init_irq,
|
||||
.timer = &clps711x_timer,
|
||||
.init_machine = cdb89712_init,
|
||||
.handle_irq = clps711x_handle_irq,
|
||||
.restart = clps711x_restart,
|
||||
MACHINE_END
|
||||
|
|
@ -33,14 +33,14 @@ fixup_clep7312(struct tag *tags, char **cmdline, struct meminfo *mi)
|
|||
mi->bank[0].size = 0x01000000;
|
||||
}
|
||||
|
||||
|
||||
MACHINE_START(CLEP7212, "Cirrus Logic 7212/7312")
|
||||
/* Maintainer: Nobody */
|
||||
.atag_offset = 0x0100,
|
||||
.nr_irqs = CLPS711X_NR_IRQS,
|
||||
.fixup = fixup_clep7312,
|
||||
.map_io = clps711x_map_io,
|
||||
.init_irq = clps711x_init_irq,
|
||||
.timer = &clps711x_timer,
|
||||
.handle_irq = clps711x_handle_irq,
|
||||
.restart = clps711x_restart,
|
||||
MACHINE_END
|
||||
|
||||
|
|
@ -0,0 +1,180 @@
|
|||
/*
|
||||
* Copyright (C) 2000, 2001 Blue Mug, Inc. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/memblock.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/backlight.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <linux/mtd/physmap.h>
|
||||
#include <linux/mtd/partitions.h>
|
||||
|
||||
#include <asm/setup.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
#include <video/platform_lcd.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
#define VIDEORAM_SIZE SZ_128K
|
||||
|
||||
#define EDB7211_LCD_DC_DC_EN CLPS711X_GPIO(3, 1)
|
||||
#define EDB7211_LCDEN CLPS711X_GPIO(3, 2)
|
||||
#define EDB7211_LCDBL CLPS711X_GPIO(3, 3)
|
||||
|
||||
#define EDB7211_FLASH0_BASE (CS0_PHYS_BASE)
|
||||
#define EDB7211_FLASH1_BASE (CS1_PHYS_BASE)
|
||||
#define EDB7211_CS8900_BASE (CS2_PHYS_BASE + 0x300)
|
||||
#define EDB7211_CS8900_IRQ (IRQ_EINT3)
|
||||
|
||||
static struct resource edb7211_cs8900_resource[] __initdata = {
|
||||
DEFINE_RES_MEM(EDB7211_CS8900_BASE, SZ_1K),
|
||||
DEFINE_RES_IRQ(EDB7211_CS8900_IRQ),
|
||||
};
|
||||
|
||||
static struct mtd_partition edb7211_flash_partitions[] __initdata = {
|
||||
{
|
||||
.name = "Flash",
|
||||
.offset = 0,
|
||||
.size = MTDPART_SIZ_FULL,
|
||||
},
|
||||
};
|
||||
|
||||
static struct physmap_flash_data edb7211_flash_pdata __initdata = {
|
||||
.width = 4,
|
||||
.parts = edb7211_flash_partitions,
|
||||
.nr_parts = ARRAY_SIZE(edb7211_flash_partitions),
|
||||
};
|
||||
|
||||
static struct resource edb7211_flash_resources[] __initdata = {
|
||||
DEFINE_RES_MEM(EDB7211_FLASH0_BASE, SZ_8M),
|
||||
DEFINE_RES_MEM(EDB7211_FLASH1_BASE, SZ_8M),
|
||||
};
|
||||
|
||||
static struct platform_device edb7211_flash_pdev __initdata = {
|
||||
.name = "physmap-flash",
|
||||
.id = 0,
|
||||
.resource = edb7211_flash_resources,
|
||||
.num_resources = ARRAY_SIZE(edb7211_flash_resources),
|
||||
.dev = {
|
||||
.platform_data = &edb7211_flash_pdata,
|
||||
},
|
||||
};
|
||||
|
||||
static void edb7211_lcd_power_set(struct plat_lcd_data *pd, unsigned int power)
|
||||
{
|
||||
if (power) {
|
||||
gpio_set_value(EDB7211_LCDEN, 1);
|
||||
udelay(100);
|
||||
gpio_set_value(EDB7211_LCD_DC_DC_EN, 1);
|
||||
} else {
|
||||
gpio_set_value(EDB7211_LCD_DC_DC_EN, 0);
|
||||
udelay(100);
|
||||
gpio_set_value(EDB7211_LCDEN, 0);
|
||||
}
|
||||
}
|
||||
|
||||
static struct plat_lcd_data edb7211_lcd_power_pdata = {
|
||||
.set_power = edb7211_lcd_power_set,
|
||||
};
|
||||
|
||||
static void edb7211_lcd_backlight_set_intensity(int intensity)
|
||||
{
|
||||
gpio_set_value(EDB7211_LCDBL, intensity);
|
||||
}
|
||||
|
||||
static struct generic_bl_info edb7211_lcd_backlight_pdata = {
|
||||
.name = "lcd-backlight.0",
|
||||
.default_intensity = 0x01,
|
||||
.max_intensity = 0x01,
|
||||
.set_bl_intensity = edb7211_lcd_backlight_set_intensity,
|
||||
};
|
||||
|
||||
static struct gpio edb7211_gpios[] __initconst = {
|
||||
{ EDB7211_LCD_DC_DC_EN, GPIOF_OUT_INIT_LOW, "LCD DC-DC" },
|
||||
{ EDB7211_LCDEN, GPIOF_OUT_INIT_LOW, "LCD POWER" },
|
||||
{ EDB7211_LCDBL, GPIOF_OUT_INIT_LOW, "LCD BACKLIGHT" },
|
||||
};
|
||||
|
||||
static struct map_desc edb7211_io_desc[] __initdata = {
|
||||
{ /* Memory-mapped extra keyboard row */
|
||||
.virtual = IO_ADDRESS(EP7211_PHYS_EXTKBD),
|
||||
.pfn = __phys_to_pfn(EP7211_PHYS_EXTKBD),
|
||||
.length = SZ_1M,
|
||||
.type = MT_DEVICE,
|
||||
},
|
||||
};
|
||||
|
||||
void __init edb7211_map_io(void)
|
||||
{
|
||||
clps711x_map_io();
|
||||
iotable_init(edb7211_io_desc, ARRAY_SIZE(edb7211_io_desc));
|
||||
}
|
||||
|
||||
/* Reserve screen memory region at the start of main system memory. */
|
||||
static void __init edb7211_reserve(void)
|
||||
{
|
||||
memblock_reserve(PHYS_OFFSET, VIDEORAM_SIZE);
|
||||
}
|
||||
|
||||
static void __init
|
||||
fixup_edb7211(struct tag *tags, char **cmdline, struct meminfo *mi)
|
||||
{
|
||||
/*
|
||||
* Bank start addresses are not present in the information
|
||||
* passed in from the boot loader. We could potentially
|
||||
* detect them, but instead we hard-code them.
|
||||
*
|
||||
* Banks sizes _are_ present in the param block, but we're
|
||||
* not using that information yet.
|
||||
*/
|
||||
mi->bank[0].start = 0xc0000000;
|
||||
mi->bank[0].size = SZ_8M;
|
||||
mi->bank[1].start = 0xc1000000;
|
||||
mi->bank[1].size = SZ_8M;
|
||||
mi->nr_banks = 2;
|
||||
}
|
||||
|
||||
static void __init edb7211_init(void)
|
||||
{
|
||||
gpio_request_array(edb7211_gpios, ARRAY_SIZE(edb7211_gpios));
|
||||
|
||||
platform_device_register(&edb7211_flash_pdev);
|
||||
platform_device_register_data(&platform_bus, "platform-lcd", 0,
|
||||
&edb7211_lcd_power_pdata,
|
||||
sizeof(edb7211_lcd_power_pdata));
|
||||
platform_device_register_data(&platform_bus, "generic-bl", 0,
|
||||
&edb7211_lcd_backlight_pdata,
|
||||
sizeof(edb7211_lcd_backlight_pdata));
|
||||
platform_device_register_simple("video-clps711x", 0, NULL, 0);
|
||||
platform_device_register_simple("cs89x0", 0, edb7211_cs8900_resource,
|
||||
ARRAY_SIZE(edb7211_cs8900_resource));
|
||||
}
|
||||
|
||||
MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)")
|
||||
/* Maintainer: Jon McClintock */
|
||||
.atag_offset = VIDEORAM_SIZE + 0x100,
|
||||
.nr_irqs = CLPS711X_NR_IRQS,
|
||||
.fixup = fixup_edb7211,
|
||||
.reserve = edb7211_reserve,
|
||||
.map_io = edb7211_map_io,
|
||||
.init_irq = clps711x_init_irq,
|
||||
.timer = &clps711x_timer,
|
||||
.init_machine = edb7211_init,
|
||||
.handle_irq = clps711x_handle_irq,
|
||||
.restart = clps711x_restart,
|
||||
MACHINE_END
|
||||
|
|
@ -74,9 +74,11 @@ fortunet_fixup(struct tag *tags, char **cmdline, struct meminfo *mi)
|
|||
|
||||
MACHINE_START(FORTUNET, "ARM-FortuNet")
|
||||
/* Maintainer: FortuNet Inc. */
|
||||
.nr_irqs = CLPS711X_NR_IRQS,
|
||||
.fixup = fortunet_fixup,
|
||||
.map_io = clps711x_map_io,
|
||||
.init_irq = clps711x_init_irq,
|
||||
.timer = &clps711x_timer,
|
||||
.handle_irq = clps711x_handle_irq,
|
||||
.restart = clps711x_restart,
|
||||
MACHINE_END
|
||||
|
|
@ -0,0 +1,232 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-clps711x/p720t.c
|
||||
*
|
||||
* Copyright (C) 2000-2001 Deep Blue Solutions Ltd
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/leds.h>
|
||||
#include <linux/sizes.h>
|
||||
#include <linux/backlight.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/mtd/partitions.h>
|
||||
#include <linux/mtd/nand-gpio.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/setup.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <mach/syspld.h>
|
||||
|
||||
#include <video/platform_lcd.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
#define P720T_USERLED CLPS711X_GPIO(3, 0)
|
||||
#define P720T_NAND_CLE CLPS711X_GPIO(4, 0)
|
||||
#define P720T_NAND_ALE CLPS711X_GPIO(4, 1)
|
||||
#define P720T_NAND_NCE CLPS711X_GPIO(4, 2)
|
||||
|
||||
#define P720T_NAND_BASE (CLPS711X_SDRAM1_BASE)
|
||||
|
||||
static struct resource p720t_nand_resource[] __initdata = {
|
||||
DEFINE_RES_MEM(P720T_NAND_BASE, SZ_4),
|
||||
};
|
||||
|
||||
static struct mtd_partition p720t_nand_parts[] __initdata = {
|
||||
{
|
||||
.name = "Flash partition 1",
|
||||
.offset = 0,
|
||||
.size = SZ_2M,
|
||||
},
|
||||
{
|
||||
.name = "Flash partition 2",
|
||||
.offset = MTDPART_OFS_APPEND,
|
||||
.size = MTDPART_SIZ_FULL,
|
||||
},
|
||||
};
|
||||
|
||||
static struct gpio_nand_platdata p720t_nand_pdata __initdata = {
|
||||
.gpio_rdy = -1,
|
||||
.gpio_nce = P720T_NAND_NCE,
|
||||
.gpio_ale = P720T_NAND_ALE,
|
||||
.gpio_cle = P720T_NAND_CLE,
|
||||
.gpio_nwp = -1,
|
||||
.chip_delay = 15,
|
||||
.parts = p720t_nand_parts,
|
||||
.num_parts = ARRAY_SIZE(p720t_nand_parts),
|
||||
};
|
||||
|
||||
static struct platform_device p720t_nand_pdev __initdata = {
|
||||
.name = "gpio-nand",
|
||||
.id = -1,
|
||||
.resource = p720t_nand_resource,
|
||||
.num_resources = ARRAY_SIZE(p720t_nand_resource),
|
||||
.dev = {
|
||||
.platform_data = &p720t_nand_pdata,
|
||||
},
|
||||
};
|
||||
|
||||
static void p720t_lcd_power_set(struct plat_lcd_data *pd, unsigned int power)
|
||||
{
|
||||
if (power) {
|
||||
PLD_LCDEN = PLD_LCDEN_EN;
|
||||
PLD_PWR |= PLD_S4_ON | PLD_S2_ON | PLD_S1_ON;
|
||||
} else {
|
||||
PLD_PWR &= ~(PLD_S4_ON | PLD_S2_ON | PLD_S1_ON);
|
||||
PLD_LCDEN = 0;
|
||||
}
|
||||
}
|
||||
|
||||
static struct plat_lcd_data p720t_lcd_power_pdata = {
|
||||
.set_power = p720t_lcd_power_set,
|
||||
};
|
||||
|
||||
static void p720t_lcd_backlight_set_intensity(int intensity)
|
||||
{
|
||||
if (intensity)
|
||||
PLD_PWR |= PLD_S3_ON;
|
||||
else
|
||||
PLD_PWR = 0;
|
||||
}
|
||||
|
||||
static struct generic_bl_info p720t_lcd_backlight_pdata = {
|
||||
.name = "lcd-backlight.0",
|
||||
.default_intensity = 0x01,
|
||||
.max_intensity = 0x01,
|
||||
.set_bl_intensity = p720t_lcd_backlight_set_intensity,
|
||||
};
|
||||
|
||||
/*
|
||||
* Map the P720T system PLD. It occupies two address spaces:
|
||||
* 0x10000000 and 0x10400000. We map both regions as one.
|
||||
*/
|
||||
static struct map_desc p720t_io_desc[] __initdata = {
|
||||
{
|
||||
.virtual = SYSPLD_VIRT_BASE,
|
||||
.pfn = __phys_to_pfn(SYSPLD_PHYS_BASE),
|
||||
.length = SZ_8M,
|
||||
.type = MT_DEVICE,
|
||||
},
|
||||
};
|
||||
|
||||
static void __init
|
||||
fixup_p720t(struct tag *tag, char **cmdline, struct meminfo *mi)
|
||||
{
|
||||
/*
|
||||
* Our bootloader doesn't setup any tags (yet).
|
||||
*/
|
||||
if (tag->hdr.tag != ATAG_CORE) {
|
||||
tag->hdr.tag = ATAG_CORE;
|
||||
tag->hdr.size = tag_size(tag_core);
|
||||
tag->u.core.flags = 0;
|
||||
tag->u.core.pagesize = PAGE_SIZE;
|
||||
tag->u.core.rootdev = 0x0100;
|
||||
|
||||
tag = tag_next(tag);
|
||||
tag->hdr.tag = ATAG_MEM;
|
||||
tag->hdr.size = tag_size(tag_mem32);
|
||||
tag->u.mem.size = 4096;
|
||||
tag->u.mem.start = PHYS_OFFSET;
|
||||
|
||||
tag = tag_next(tag);
|
||||
tag->hdr.tag = ATAG_NONE;
|
||||
tag->hdr.size = 0;
|
||||
}
|
||||
}
|
||||
|
||||
static void __init p720t_map_io(void)
|
||||
{
|
||||
clps711x_map_io();
|
||||
iotable_init(p720t_io_desc, ARRAY_SIZE(p720t_io_desc));
|
||||
}
|
||||
|
||||
static void __init p720t_init_early(void)
|
||||
{
|
||||
/*
|
||||
* Power down as much as possible in case we don't
|
||||
* have the drivers loaded.
|
||||
*/
|
||||
PLD_LCDEN = 0;
|
||||
PLD_PWR &= ~(PLD_S4_ON|PLD_S3_ON|PLD_S2_ON|PLD_S1_ON);
|
||||
|
||||
PLD_KBD = 0;
|
||||
PLD_IO = 0;
|
||||
PLD_IRDA = 0;
|
||||
PLD_CODEC = 0;
|
||||
PLD_TCH = 0;
|
||||
PLD_SPI = 0;
|
||||
if (!IS_ENABLED(CONFIG_DEBUG_LL)) {
|
||||
PLD_COM2 = 0;
|
||||
PLD_COM1 = 0;
|
||||
}
|
||||
}
|
||||
|
||||
static struct gpio_led p720t_gpio_leds[] = {
|
||||
{
|
||||
.name = "User LED",
|
||||
.default_trigger = "heartbeat",
|
||||
.gpio = P720T_USERLED,
|
||||
},
|
||||
};
|
||||
|
||||
static struct gpio_led_platform_data p720t_gpio_led_pdata __initdata = {
|
||||
.leds = p720t_gpio_leds,
|
||||
.num_leds = ARRAY_SIZE(p720t_gpio_leds),
|
||||
};
|
||||
|
||||
static void __init p720t_init(void)
|
||||
{
|
||||
platform_device_register(&p720t_nand_pdev);
|
||||
platform_device_register_data(&platform_bus, "platform-lcd", 0,
|
||||
&p720t_lcd_power_pdata,
|
||||
sizeof(p720t_lcd_power_pdata));
|
||||
platform_device_register_data(&platform_bus, "generic-bl", 0,
|
||||
&p720t_lcd_backlight_pdata,
|
||||
sizeof(p720t_lcd_backlight_pdata));
|
||||
platform_device_register_simple("video-clps711x", 0, NULL, 0);
|
||||
}
|
||||
|
||||
static void __init p720t_init_late(void)
|
||||
{
|
||||
platform_device_register_data(&platform_bus, "leds-gpio", 0,
|
||||
&p720t_gpio_led_pdata,
|
||||
sizeof(p720t_gpio_led_pdata));
|
||||
}
|
||||
|
||||
MACHINE_START(P720T, "ARM-Prospector720T")
|
||||
/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
|
||||
.atag_offset = 0x100,
|
||||
.nr_irqs = CLPS711X_NR_IRQS,
|
||||
.fixup = fixup_p720t,
|
||||
.map_io = p720t_map_io,
|
||||
.init_early = p720t_init_early,
|
||||
.init_irq = clps711x_init_irq,
|
||||
.timer = &clps711x_timer,
|
||||
.init_machine = p720t_init,
|
||||
.init_late = p720t_init_late,
|
||||
.handle_irq = clps711x_handle_irq,
|
||||
.restart = clps711x_restart,
|
||||
MACHINE_END
|
||||
|
|
@ -1,63 +0,0 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-clps711x/cdb89712.c
|
||||
*
|
||||
* Copyright (C) 2000-2001 Deep Blue Solutions Ltd
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/setup.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
/*
|
||||
* Map the CS89712 Ethernet port. That should be moved to the
|
||||
* ethernet driver, perhaps.
|
||||
*/
|
||||
static struct map_desc cdb89712_io_desc[] __initdata = {
|
||||
{
|
||||
.virtual = ETHER_BASE,
|
||||
.pfn =__phys_to_pfn(ETHER_START),
|
||||
.length = ETHER_SIZE,
|
||||
.type = MT_DEVICE
|
||||
}
|
||||
};
|
||||
|
||||
static void __init cdb89712_map_io(void)
|
||||
{
|
||||
clps711x_map_io();
|
||||
iotable_init(cdb89712_io_desc, ARRAY_SIZE(cdb89712_io_desc));
|
||||
}
|
||||
|
||||
MACHINE_START(CDB89712, "Cirrus-CDB89712")
|
||||
/* Maintainer: Ray Lehtiniemi */
|
||||
.atag_offset = 0x100,
|
||||
.map_io = cdb89712_map_io,
|
||||
.init_irq = clps711x_init_irq,
|
||||
.timer = &clps711x_timer,
|
||||
.restart = clps711x_restart,
|
||||
MACHINE_END
|
||||
|
|
@ -21,13 +21,16 @@
|
|||
*/
|
||||
#include <linux/io.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/sizes.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/clockchips.h>
|
||||
#include <linux/clk-provider.h>
|
||||
|
||||
#include <asm/sizes.h>
|
||||
#include <asm/exception.h>
|
||||
#include <asm/mach/irq.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <asm/system_misc.h>
|
||||
|
|
@ -36,7 +39,6 @@
|
|||
|
||||
static struct clk *clk_pll, *clk_bus, *clk_uart, *clk_timerl, *clk_timerh,
|
||||
*clk_tint, *clk_spi;
|
||||
static unsigned long latch;
|
||||
|
||||
/*
|
||||
* This maps the generic CLPS711x registers
|
||||
|
|
@ -45,7 +47,7 @@ static struct map_desc clps711x_io_desc[] __initdata = {
|
|||
{
|
||||
.virtual = (unsigned long)CLPS711X_VIRT_BASE,
|
||||
.pfn = __phys_to_pfn(CLPS711X_PHYS_BASE),
|
||||
.length = SZ_1M,
|
||||
.length = SZ_64K,
|
||||
.type = MT_DEVICE
|
||||
}
|
||||
};
|
||||
|
|
@ -64,7 +66,7 @@ static void int1_mask(struct irq_data *d)
|
|||
clps_writel(intmr1, INTMR1);
|
||||
}
|
||||
|
||||
static void int1_ack(struct irq_data *d)
|
||||
static void int1_eoi(struct irq_data *d)
|
||||
{
|
||||
switch (d->irq) {
|
||||
case IRQ_CSINT: clps_writel(0, COEOI); break;
|
||||
|
|
@ -86,7 +88,8 @@ static void int1_unmask(struct irq_data *d)
|
|||
}
|
||||
|
||||
static struct irq_chip int1_chip = {
|
||||
.irq_ack = int1_ack,
|
||||
.name = "Interrupt Vector 1",
|
||||
.irq_eoi = int1_eoi,
|
||||
.irq_mask = int1_mask,
|
||||
.irq_unmask = int1_unmask,
|
||||
};
|
||||
|
|
@ -100,7 +103,7 @@ static void int2_mask(struct irq_data *d)
|
|||
clps_writel(intmr2, INTMR2);
|
||||
}
|
||||
|
||||
static void int2_ack(struct irq_data *d)
|
||||
static void int2_eoi(struct irq_data *d)
|
||||
{
|
||||
switch (d->irq) {
|
||||
case IRQ_KBDINT: clps_writel(0, KBDEOI); break;
|
||||
|
|
@ -117,73 +120,160 @@ static void int2_unmask(struct irq_data *d)
|
|||
}
|
||||
|
||||
static struct irq_chip int2_chip = {
|
||||
.irq_ack = int2_ack,
|
||||
.name = "Interrupt Vector 2",
|
||||
.irq_eoi = int2_eoi,
|
||||
.irq_mask = int2_mask,
|
||||
.irq_unmask = int2_unmask,
|
||||
};
|
||||
|
||||
static void int3_mask(struct irq_data *d)
|
||||
{
|
||||
u32 intmr3;
|
||||
|
||||
intmr3 = clps_readl(INTMR3);
|
||||
intmr3 &= ~(1 << (d->irq - 32));
|
||||
clps_writel(intmr3, INTMR3);
|
||||
}
|
||||
|
||||
static void int3_unmask(struct irq_data *d)
|
||||
{
|
||||
u32 intmr3;
|
||||
|
||||
intmr3 = clps_readl(INTMR3);
|
||||
intmr3 |= 1 << (d->irq - 32);
|
||||
clps_writel(intmr3, INTMR3);
|
||||
}
|
||||
|
||||
static struct irq_chip int3_chip = {
|
||||
.name = "Interrupt Vector 3",
|
||||
.irq_mask = int3_mask,
|
||||
.irq_unmask = int3_unmask,
|
||||
};
|
||||
|
||||
static struct {
|
||||
int nr;
|
||||
struct irq_chip *chip;
|
||||
irq_flow_handler_t handle;
|
||||
} clps711x_irqdescs[] __initdata = {
|
||||
{ IRQ_CSINT, &int1_chip, handle_fasteoi_irq, },
|
||||
{ IRQ_EINT1, &int1_chip, handle_level_irq, },
|
||||
{ IRQ_EINT2, &int1_chip, handle_level_irq, },
|
||||
{ IRQ_EINT3, &int1_chip, handle_level_irq, },
|
||||
{ IRQ_TC1OI, &int1_chip, handle_fasteoi_irq, },
|
||||
{ IRQ_TC2OI, &int1_chip, handle_fasteoi_irq, },
|
||||
{ IRQ_RTCMI, &int1_chip, handle_fasteoi_irq, },
|
||||
{ IRQ_TINT, &int1_chip, handle_fasteoi_irq, },
|
||||
{ IRQ_UTXINT1, &int1_chip, handle_level_irq, },
|
||||
{ IRQ_URXINT1, &int1_chip, handle_level_irq, },
|
||||
{ IRQ_UMSINT, &int1_chip, handle_fasteoi_irq, },
|
||||
{ IRQ_SSEOTI, &int1_chip, handle_level_irq, },
|
||||
{ IRQ_KBDINT, &int2_chip, handle_fasteoi_irq, },
|
||||
{ IRQ_SS2RX, &int2_chip, handle_level_irq, },
|
||||
{ IRQ_SS2TX, &int2_chip, handle_level_irq, },
|
||||
{ IRQ_UTXINT2, &int2_chip, handle_level_irq, },
|
||||
{ IRQ_URXINT2, &int2_chip, handle_level_irq, },
|
||||
};
|
||||
|
||||
void __init clps711x_init_irq(void)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < NR_IRQS; i++) {
|
||||
if (INT1_IRQS & (1 << i)) {
|
||||
irq_set_chip_and_handler(i, &int1_chip,
|
||||
handle_level_irq);
|
||||
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
|
||||
}
|
||||
if (INT2_IRQS & (1 << i)) {
|
||||
irq_set_chip_and_handler(i, &int2_chip,
|
||||
handle_level_irq);
|
||||
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Disable interrupts
|
||||
*/
|
||||
/* Disable interrupts */
|
||||
clps_writel(0, INTMR1);
|
||||
clps_writel(0, INTMR2);
|
||||
clps_writel(0, INTMR3);
|
||||
|
||||
/*
|
||||
* Clear down any pending interrupts
|
||||
*/
|
||||
/* Clear down any pending interrupts */
|
||||
clps_writel(0, BLEOI);
|
||||
clps_writel(0, MCEOI);
|
||||
clps_writel(0, COEOI);
|
||||
clps_writel(0, TC1EOI);
|
||||
clps_writel(0, TC2EOI);
|
||||
clps_writel(0, RTCEOI);
|
||||
clps_writel(0, TEOI);
|
||||
clps_writel(0, UMSEOI);
|
||||
clps_writel(0, SYNCIO);
|
||||
clps_writel(0, KBDEOI);
|
||||
clps_writel(0, SRXEOF);
|
||||
clps_writel(0xffffffff, DAISR);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clps711x_irqdescs); i++) {
|
||||
irq_set_chip_and_handler(clps711x_irqdescs[i].nr,
|
||||
clps711x_irqdescs[i].chip,
|
||||
clps711x_irqdescs[i].handle);
|
||||
set_irq_flags(clps711x_irqdescs[i].nr,
|
||||
IRQF_VALID | IRQF_PROBE);
|
||||
}
|
||||
|
||||
if (IS_ENABLED(CONFIG_FIQ)) {
|
||||
init_FIQ(0);
|
||||
irq_set_chip_and_handler(IRQ_DAIINT, &int3_chip,
|
||||
handle_bad_irq);
|
||||
set_irq_flags(IRQ_DAIINT,
|
||||
IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* gettimeoffset() returns time since last timer tick, in usecs.
|
||||
*
|
||||
* 'LATCH' is hwclock ticks (see CLOCK_TICK_RATE in timex.h) per jiffy.
|
||||
* 'tick' is usecs per jiffy.
|
||||
*/
|
||||
static unsigned long clps711x_gettimeoffset(void)
|
||||
inline u32 fls16(u32 x)
|
||||
{
|
||||
unsigned long hwticks;
|
||||
hwticks = latch - (clps_readl(TC2D) & 0xffff);
|
||||
return (hwticks * (tick_nsec / 1000)) / latch;
|
||||
u32 r = 15;
|
||||
|
||||
if (!(x & 0xff00)) {
|
||||
x <<= 8;
|
||||
r -= 8;
|
||||
}
|
||||
if (!(x & 0xf000)) {
|
||||
x <<= 4;
|
||||
r -= 4;
|
||||
}
|
||||
if (!(x & 0xc000)) {
|
||||
x <<= 2;
|
||||
r -= 2;
|
||||
}
|
||||
if (!(x & 0x8000))
|
||||
r--;
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
/*
|
||||
* IRQ handler for the timer
|
||||
*/
|
||||
static irqreturn_t p720t_timer_interrupt(int irq, void *dev_id)
|
||||
asmlinkage void __exception_irq_entry clps711x_handle_irq(struct pt_regs *regs)
|
||||
{
|
||||
timer_tick();
|
||||
u32 irqstat;
|
||||
void __iomem *base = CLPS711X_VIRT_BASE;
|
||||
|
||||
irqstat = readl_relaxed(base + INTSR1) & readl_relaxed(base + INTMR1);
|
||||
if (irqstat) {
|
||||
handle_IRQ(fls16(irqstat), regs);
|
||||
return;
|
||||
}
|
||||
|
||||
irqstat = readl_relaxed(base + INTSR2) & readl_relaxed(base + INTMR2);
|
||||
if (likely(irqstat))
|
||||
handle_IRQ(fls16(irqstat) + 16, regs);
|
||||
}
|
||||
|
||||
static void clps711x_clockevent_set_mode(enum clock_event_mode mode,
|
||||
struct clock_event_device *evt)
|
||||
{
|
||||
}
|
||||
|
||||
static struct clock_event_device clockevent_clps711x = {
|
||||
.name = "CLPS711x Clockevents",
|
||||
.rating = 300,
|
||||
.features = CLOCK_EVT_FEAT_PERIODIC,
|
||||
.set_mode = clps711x_clockevent_set_mode,
|
||||
};
|
||||
|
||||
static irqreturn_t clps711x_timer_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
clockevent_clps711x.event_handler(&clockevent_clps711x);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static struct irqaction clps711x_timer_irq = {
|
||||
.name = "CLPS711x Timer Tick",
|
||||
.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
|
||||
.handler = p720t_timer_interrupt,
|
||||
.handler = clps711x_timer_interrupt,
|
||||
};
|
||||
|
||||
static void add_fixed_clk(struct clk *clk, const char *name, int rate)
|
||||
|
|
@ -244,20 +334,19 @@ static void __init clps711x_timer_init(void)
|
|||
|
||||
pr_info("CPU frequency set at %i Hz.\n", cpu);
|
||||
|
||||
latch = (timh + HZ / 2) / HZ;
|
||||
clps_writew(DIV_ROUND_CLOSEST(timh, HZ), TC2D);
|
||||
|
||||
tmp = clps_readl(SYSCON1);
|
||||
tmp |= SYSCON1_TC2S | SYSCON1_TC2M;
|
||||
clps_writel(tmp, SYSCON1);
|
||||
|
||||
clps_writel(latch - 1, TC2D);
|
||||
clockevents_config_and_register(&clockevent_clps711x, timh, 1, 0xffff);
|
||||
|
||||
setup_irq(IRQ_TC2OI, &clps711x_timer_irq);
|
||||
}
|
||||
|
||||
struct sys_timer clps711x_timer = {
|
||||
.init = clps711x_timer_init,
|
||||
.offset = clps711x_gettimeoffset,
|
||||
};
|
||||
|
||||
void clps711x_restart(char mode, const char *cmd)
|
||||
|
|
|
|||
|
|
@ -4,9 +4,14 @@
|
|||
* Common bits.
|
||||
*/
|
||||
|
||||
#define CLPS711X_NR_IRQS (33)
|
||||
#define CLPS711X_NR_GPIO (4 * 8 + 3)
|
||||
#define CLPS711X_GPIO(prt, bit) ((prt) * 8 + (bit))
|
||||
|
||||
struct sys_timer;
|
||||
|
||||
extern void clps711x_map_io(void);
|
||||
extern void clps711x_init_irq(void);
|
||||
extern struct sys_timer clps711x_timer;
|
||||
extern void clps711x_handle_irq(struct pt_regs *regs);
|
||||
extern void clps711x_restart(char mode, const char *cmd);
|
||||
extern struct sys_timer clps711x_timer;
|
||||
|
|
|
|||
|
|
@ -1,66 +0,0 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-clps711x/arch-edb7211.c
|
||||
*
|
||||
* Copyright (C) 2000, 2001 Blue Mug, Inc. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/memblock.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/string.h>
|
||||
|
||||
#include <asm/setup.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
extern void edb7211_map_io(void);
|
||||
|
||||
/* Reserve screen memory region at the start of main system memory. */
|
||||
static void __init edb7211_reserve(void)
|
||||
{
|
||||
memblock_reserve(PHYS_OFFSET, 0x00020000);
|
||||
}
|
||||
|
||||
static void __init
|
||||
fixup_edb7211(struct tag *tags, char **cmdline, struct meminfo *mi)
|
||||
{
|
||||
/*
|
||||
* Bank start addresses are not present in the information
|
||||
* passed in from the boot loader. We could potentially
|
||||
* detect them, but instead we hard-code them.
|
||||
*
|
||||
* Banks sizes _are_ present in the param block, but we're
|
||||
* not using that information yet.
|
||||
*/
|
||||
mi->bank[0].start = 0xc0000000;
|
||||
mi->bank[0].size = 8*1024*1024;
|
||||
mi->bank[1].start = 0xc1000000;
|
||||
mi->bank[1].size = 8*1024*1024;
|
||||
mi->nr_banks = 2;
|
||||
}
|
||||
|
||||
MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)")
|
||||
/* Maintainer: Jon McClintock */
|
||||
.atag_offset = 0x20100, /* 0xc0000000 - 0xc001ffff can be video RAM */
|
||||
.fixup = fixup_edb7211,
|
||||
.map_io = edb7211_map_io,
|
||||
.reserve = edb7211_reserve,
|
||||
.init_irq = clps711x_init_irq,
|
||||
.timer = &clps711x_timer,
|
||||
.restart = clps711x_restart,
|
||||
MACHINE_END
|
||||
|
|
@ -1,82 +0,0 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-clps711x/mm.c
|
||||
*
|
||||
* Extra MM routines for the EDB7211 board
|
||||
*
|
||||
* Copyright (C) 2000, 2001 Blue Mug, Inc. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/bug.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/sizes.h>
|
||||
|
||||
#include <asm/mach/map.h>
|
||||
|
||||
extern void clps711x_map_io(void);
|
||||
|
||||
/*
|
||||
* The on-chip registers are given a size of 1MB so that a section can
|
||||
* be used to map them; this saves a page table. This is the place to
|
||||
* add mappings for ROM, expansion memory, PCMCIA, etc. (if static
|
||||
* mappings are chosen for those areas).
|
||||
*
|
||||
* Here is a physical memory map (to be fleshed out later):
|
||||
*
|
||||
* Physical Address Size Description
|
||||
* ----------------- ----- ---------------------------------
|
||||
* c0000000-c001ffff 128KB reserved for video RAM [1]
|
||||
* c0020000-c0023fff 16KB parameters (see Documentation/arm/Setup)
|
||||
* c0024000-c0027fff 16KB swapper_pg_dir (task 0 page directory)
|
||||
* c0028000-... kernel image (TEXTADDR)
|
||||
*
|
||||
* [1] Unused pages should be given back to the VM; they are not yet.
|
||||
* The parameter block should also be released (not sure if this
|
||||
* happens).
|
||||
*/
|
||||
static struct map_desc edb7211_io_desc[] __initdata = {
|
||||
{ /* memory-mapped extra keyboard row */
|
||||
.virtual = EP7211_VIRT_EXTKBD,
|
||||
.pfn = __phys_to_pfn(EP7211_PHYS_EXTKBD),
|
||||
.length = SZ_1M,
|
||||
.type = MT_DEVICE,
|
||||
}, { /* and CS8900A Ethernet chip */
|
||||
.virtual = EP7211_VIRT_CS8900A,
|
||||
.pfn = __phys_to_pfn(EP7211_PHYS_CS8900A),
|
||||
.length = SZ_1M,
|
||||
.type = MT_DEVICE,
|
||||
}, { /* flash banks */
|
||||
.virtual = EP7211_VIRT_FLASH1,
|
||||
.pfn = __phys_to_pfn(EP7211_PHYS_FLASH1),
|
||||
.length = SZ_8M,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = EP7211_VIRT_FLASH2,
|
||||
.pfn = __phys_to_pfn(EP7211_PHYS_FLASH2),
|
||||
.length = SZ_8M,
|
||||
.type = MT_DEVICE,
|
||||
}
|
||||
};
|
||||
|
||||
void __init edb7211_map_io(void)
|
||||
{
|
||||
clps711x_map_io();
|
||||
iotable_init(edb7211_io_desc, ARRAY_SIZE(edb7211_io_desc));
|
||||
}
|
||||
|
||||
|
|
@ -20,13 +20,6 @@
|
|||
#ifndef __ASM_ARCH_AUTCPU12_H
|
||||
#define __ASM_ARCH_AUTCPU12_H
|
||||
|
||||
/*
|
||||
* The CS8900A ethernet chip has its I/O registers wired to chip select 2
|
||||
* (nCS2). This is the mapping for it.
|
||||
*/
|
||||
#define AUTCPU12_PHYS_CS8900A CS2_PHYS_BASE /* physical */
|
||||
#define AUTCPU12_VIRT_CS8900A (0xfe000000) /* virtual */
|
||||
|
||||
/*
|
||||
* The flash bank is wired to chip select 0
|
||||
*/
|
||||
|
|
@ -34,11 +27,9 @@
|
|||
|
||||
/* offset for device specific information structure */
|
||||
#define AUTCPU12_LCDINFO_OFFS (0x00010000)
|
||||
/*
|
||||
* Videomemory is the internal SRAM (CS 6)
|
||||
*/
|
||||
|
||||
/* Videomemory in the internal SRAM (CS 6) */
|
||||
#define AUTCPU12_PHYS_VIDEO CS6_PHYS_BASE
|
||||
#define AUTCPU12_VIRT_VIDEO (0xfd000000)
|
||||
|
||||
/*
|
||||
* All special IO's are tied to CS1
|
||||
|
|
@ -49,8 +40,6 @@
|
|||
|
||||
#define AUTCPU12_PHYS_CSAUX1 CS1_PHYS_BASE +0x04000000 /* physical */
|
||||
|
||||
#define AUTCPU12_PHYS_SMC CS1_PHYS_BASE +0x06000000 /* physical */
|
||||
|
||||
#define AUTCPU12_PHYS_CAN CS1_PHYS_BASE +0x08000000 /* physical */
|
||||
|
||||
#define AUTCPU12_PHYS_TOUCH CS1_PHYS_BASE +0x0A000000 /* physical */
|
||||
|
|
@ -59,14 +48,6 @@
|
|||
|
||||
#define AUTCPU12_PHYS_LPT CS1_PHYS_BASE +0x0E000000 /* physical */
|
||||
|
||||
/*
|
||||
* defines for smartmedia card access
|
||||
*/
|
||||
#define AUTCPU12_SMC_RDY (1<<2)
|
||||
#define AUTCPU12_SMC_ALE (1<<3)
|
||||
#define AUTCPU12_SMC_CLE (1<<4)
|
||||
#define AUTCPU12_SMC_PORT_OFFSET PBDR
|
||||
#define AUTCPU12_SMC_SELECT_OFFSET 0x10
|
||||
/*
|
||||
* defines for lcd contrast
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -257,6 +257,9 @@
|
|||
#define MEMCFG_BUS_WIDTH_16 (0)
|
||||
#define MEMCFG_BUS_WIDTH_8 (3)
|
||||
|
||||
#define MEMCFG_SQAEN (1 << 6)
|
||||
#define MEMCFG_CLKENB (1 << 7)
|
||||
|
||||
#define MEMCFG_WAITSTATE_8_3 (0 << 2)
|
||||
#define MEMCFG_WAITSTATE_7_3 (1 << 2)
|
||||
#define MEMCFG_WAITSTATE_6_3 (2 << 2)
|
||||
|
|
@ -274,4 +277,28 @@
|
|||
#define MEMCFG_WAITSTATE_2_0 (14 << 2)
|
||||
#define MEMCFG_WAITSTATE_1_0 (15 << 2)
|
||||
|
||||
/* INTSR1 Interrupts */
|
||||
#define IRQ_CSINT (4)
|
||||
#define IRQ_EINT1 (5)
|
||||
#define IRQ_EINT2 (6)
|
||||
#define IRQ_EINT3 (7)
|
||||
#define IRQ_TC1OI (8)
|
||||
#define IRQ_TC2OI (9)
|
||||
#define IRQ_RTCMI (10)
|
||||
#define IRQ_TINT (11)
|
||||
#define IRQ_UTXINT1 (12)
|
||||
#define IRQ_URXINT1 (13)
|
||||
#define IRQ_UMSINT (14)
|
||||
#define IRQ_SSEOTI (15)
|
||||
|
||||
/* INTSR2 Interrupts */
|
||||
#define IRQ_KBDINT (16 + 0)
|
||||
#define IRQ_SS2RX (16 + 1)
|
||||
#define IRQ_SS2TX (16 + 2)
|
||||
#define IRQ_UTXINT2 (16 + 12)
|
||||
#define IRQ_URXINT2 (16 + 13)
|
||||
|
||||
/* INTSR3 Interrupts */
|
||||
#define IRQ_DAIINT (32 + 0)
|
||||
|
||||
#endif /* __MACH_CLPS711X_H */
|
||||
|
|
|
|||
|
|
@ -1,51 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-clps711x/include/mach/entry-macro.S
|
||||
*
|
||||
* Low-level IRQ helper macros for CLPS711X-based platforms
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
#include <mach/hardware.h>
|
||||
|
||||
.macro get_irqnr_preamble, base, tmp
|
||||
.endm
|
||||
|
||||
#if (INTSR2 - INTSR1) != (INTMR2 - INTMR1)
|
||||
#error INTSR stride != INTMR stride
|
||||
#endif
|
||||
|
||||
.macro get_irqnr_and_base, irqnr, stat, base, mask
|
||||
mov \base, #CLPS711X_VIRT_BASE
|
||||
ldr \stat, [\base, #INTSR1]
|
||||
ldr \mask, [\base, #INTMR1]
|
||||
mov \irqnr, #4
|
||||
mov \mask, \mask, lsl #16
|
||||
and \stat, \stat, \mask, lsr #16
|
||||
movs \stat, \stat, lsr #4
|
||||
bne 1001f
|
||||
|
||||
add \base, \base, #INTSR2 - INTSR1
|
||||
ldr \stat, [\base, #INTSR1]
|
||||
ldr \mask, [\base, #INTMR1]
|
||||
mov \irqnr, #16
|
||||
mov \mask, \mask, lsl #16
|
||||
and \stat, \stat, \mask, lsr #16
|
||||
|
||||
1001: tst \stat, #255
|
||||
addeq \irqnr, \irqnr, #8
|
||||
moveq \stat, \stat, lsr #8
|
||||
tst \stat, #15
|
||||
addeq \irqnr, \irqnr, #4
|
||||
moveq \stat, \stat, lsr #4
|
||||
tst \stat, #3
|
||||
addeq \irqnr, \irqnr, #2
|
||||
moveq \stat, \stat, lsr #2
|
||||
tst \stat, #1
|
||||
addeq \irqnr, \irqnr, #1
|
||||
moveq \stat, \stat, lsr #1
|
||||
tst \stat, #1 @ bit 0 should be set
|
||||
.endm
|
||||
|
||||
|
||||
|
|
@ -24,7 +24,10 @@
|
|||
|
||||
#include <mach/clps711x.h>
|
||||
|
||||
#define CLPS711X_VIRT_BASE IOMEM(0xff000000)
|
||||
#define IO_ADDRESS(x) (0xdc000000 + (((x) & 0x03ffffff) | \
|
||||
(((x) >> 2) & 0x3c000000)))
|
||||
|
||||
#define CLPS711X_VIRT_BASE IOMEM(IO_ADDRESS(CLPS711X_PHYS_BASE))
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#define clps_readb(off) readb(CLPS711X_VIRT_BASE + (off))
|
||||
|
|
@ -61,67 +64,17 @@
|
|||
#define CS7_PHYS_BASE (0x00000000)
|
||||
#endif
|
||||
|
||||
#define SYSPLD_VIRT_BASE 0xfe000000
|
||||
#define SYSPLD_BASE SYSPLD_VIRT_BASE
|
||||
|
||||
#if defined (CONFIG_ARCH_CDB89712)
|
||||
|
||||
#define ETHER_START 0x20000000
|
||||
#define ETHER_SIZE 0x1000
|
||||
#define ETHER_BASE 0xfe000000
|
||||
|
||||
#endif
|
||||
#define CLPS711X_SRAM_BASE CS6_PHYS_BASE
|
||||
#define CLPS711X_SRAM_SIZE (48 * 1024)
|
||||
|
||||
#define CLPS711X_SDRAM0_BASE (0xc0000000)
|
||||
#define CLPS711X_SDRAM1_BASE (0xd0000000)
|
||||
|
||||
#if defined (CONFIG_ARCH_EDB7211)
|
||||
|
||||
/*
|
||||
* The extra 8 lines of the keyboard matrix are wired to chip select 3 (nCS3)
|
||||
* and repeat across it. This is the mapping for it.
|
||||
*
|
||||
* In jumpered boot mode, nCS3 is mapped to 0x4000000, not 0x3000000. This
|
||||
* was cause for much consternation and headscratching. This should probably
|
||||
* be made a compile/run time kernel option.
|
||||
*/
|
||||
#define EP7211_PHYS_EXTKBD CS3_PHYS_BASE /* physical */
|
||||
|
||||
#define EP7211_VIRT_EXTKBD (0xfd000000) /* virtual */
|
||||
|
||||
|
||||
/*
|
||||
* The CS8900A ethernet chip has its I/O registers wired to chip select 2
|
||||
* (nCS2). This is the mapping for it.
|
||||
*
|
||||
* In jumpered boot mode, nCS2 is mapped to 0x5000000, not 0x2000000. This
|
||||
* was cause for much consternation and headscratching. This should probably
|
||||
* be made a compile/run time kernel option.
|
||||
*/
|
||||
#define EP7211_PHYS_CS8900A CS2_PHYS_BASE /* physical */
|
||||
|
||||
#define EP7211_VIRT_CS8900A (0xfc000000) /* virtual */
|
||||
|
||||
|
||||
/*
|
||||
* The two flash banks are wired to chip selects 0 and 1. This is the mapping
|
||||
* for them.
|
||||
*
|
||||
* nCS0 and nCS1 are at 0x70000000 and 0x60000000, respectively, when running
|
||||
* in jumpered boot mode.
|
||||
*/
|
||||
#define EP7211_PHYS_FLASH1 CS0_PHYS_BASE /* physical */
|
||||
#define EP7211_PHYS_FLASH2 CS1_PHYS_BASE /* physical */
|
||||
|
||||
#define EP7211_VIRT_FLASH1 (0xfa000000) /* virtual */
|
||||
#define EP7211_VIRT_FLASH2 (0xfb000000) /* virtual */
|
||||
/* The extra 8 lines of the keyboard matrix are wired to chip select 3 */
|
||||
#define EP7211_PHYS_EXTKBD CS3_PHYS_BASE
|
||||
|
||||
#endif /* CONFIG_ARCH_EDB7211 */
|
||||
|
||||
/*
|
||||
* Relevant bits in port D, which controls power to the various parts of
|
||||
* the LCD on the EDB7211.
|
||||
*/
|
||||
#define EDB_PD1_LCD_DC_DC_EN (1<<1)
|
||||
#define EDB_PD2_LCDEN (1<<2)
|
||||
#define EDB_PD3_LCDBL (1<<3)
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,50 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-clps711x/include/mach/irqs.h
|
||||
*
|
||||
* Copyright (C) 2000 Deep Blue Solutions Ltd.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* Interrupts from INTSR1
|
||||
*/
|
||||
#define IRQ_CSINT 4
|
||||
#define IRQ_EINT1 5
|
||||
#define IRQ_EINT2 6
|
||||
#define IRQ_EINT3 7
|
||||
#define IRQ_TC1OI 8
|
||||
#define IRQ_TC2OI 9
|
||||
#define IRQ_RTCMI 10
|
||||
#define IRQ_TINT 11
|
||||
#define IRQ_UTXINT1 12
|
||||
#define IRQ_URXINT1 13
|
||||
#define IRQ_UMSINT 14
|
||||
#define IRQ_SSEOTI 15
|
||||
|
||||
#define INT1_IRQS (0x0000fff0)
|
||||
|
||||
/*
|
||||
* Interrupts from INTSR2
|
||||
*/
|
||||
#define IRQ_KBDINT (16+0) /* bit 0 */
|
||||
#define IRQ_SS2RX (16+1) /* bit 1 */
|
||||
#define IRQ_SS2TX (16+2) /* bit 2 */
|
||||
#define IRQ_UTXINT2 (16+12) /* bit 12 */
|
||||
#define IRQ_URXINT2 (16+13) /* bit 13 */
|
||||
|
||||
#define INT2_IRQS (0x30070000)
|
||||
|
||||
#define NR_IRQS 30
|
||||
|
|
@ -23,14 +23,9 @@
|
|||
#define __ASM_ARCH_SYSPLD_H
|
||||
|
||||
#define SYSPLD_PHYS_BASE (0x10000000)
|
||||
#define SYSPLD_VIRT_BASE IO_ADDRESS(SYSPLD_PHYS_BASE)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <asm/types.h>
|
||||
|
||||
#define SYSPLD_REG(type,off) (*(volatile type *)(SYSPLD_BASE + off))
|
||||
#else
|
||||
#define SYSPLD_REG(type,off) (off)
|
||||
#endif
|
||||
#define SYSPLD_REG(type, off) (*(volatile type *)(SYSPLD_VIRT_BASE + (off)))
|
||||
|
||||
#define PLD_INT SYSPLD_REG(u32, 0x000000)
|
||||
#define PLD_INT_PENIRQ (1 << 5)
|
||||
|
|
|
|||
|
|
@ -1,181 +0,0 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-clps711x/p720t.c
|
||||
*
|
||||
* Copyright (C) 2000-2001 Deep Blue Solutions Ltd
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/leds.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/setup.h>
|
||||
#include <asm/sizes.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <mach/syspld.h>
|
||||
|
||||
#include <asm/hardware/clps7111.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
/*
|
||||
* Map the P720T system PLD. It occupies two address spaces:
|
||||
* SYSPLD_PHYS_BASE and SYSPLD_PHYS_BASE + 0x00400000
|
||||
* We map both here.
|
||||
*/
|
||||
static struct map_desc p720t_io_desc[] __initdata = {
|
||||
{
|
||||
.virtual = SYSPLD_VIRT_BASE,
|
||||
.pfn = __phys_to_pfn(SYSPLD_PHYS_BASE),
|
||||
.length = SZ_1M,
|
||||
.type = MT_DEVICE
|
||||
}, {
|
||||
.virtual = 0xfe400000,
|
||||
.pfn = __phys_to_pfn(0x10400000),
|
||||
.length = SZ_1M,
|
||||
.type = MT_DEVICE
|
||||
}
|
||||
};
|
||||
|
||||
static void __init
|
||||
fixup_p720t(struct tag *tag, char **cmdline, struct meminfo *mi)
|
||||
{
|
||||
/*
|
||||
* Our bootloader doesn't setup any tags (yet).
|
||||
*/
|
||||
if (tag->hdr.tag != ATAG_CORE) {
|
||||
tag->hdr.tag = ATAG_CORE;
|
||||
tag->hdr.size = tag_size(tag_core);
|
||||
tag->u.core.flags = 0;
|
||||
tag->u.core.pagesize = PAGE_SIZE;
|
||||
tag->u.core.rootdev = 0x0100;
|
||||
|
||||
tag = tag_next(tag);
|
||||
tag->hdr.tag = ATAG_MEM;
|
||||
tag->hdr.size = tag_size(tag_mem32);
|
||||
tag->u.mem.size = 4096;
|
||||
tag->u.mem.start = PHYS_OFFSET;
|
||||
|
||||
tag = tag_next(tag);
|
||||
tag->hdr.tag = ATAG_NONE;
|
||||
tag->hdr.size = 0;
|
||||
}
|
||||
}
|
||||
|
||||
static void __init p720t_map_io(void)
|
||||
{
|
||||
clps711x_map_io();
|
||||
iotable_init(p720t_io_desc, ARRAY_SIZE(p720t_io_desc));
|
||||
}
|
||||
|
||||
static void __init p720t_init_early(void)
|
||||
{
|
||||
/*
|
||||
* Power down as much as possible in case we don't
|
||||
* have the drivers loaded.
|
||||
*/
|
||||
PLD_LCDEN = 0;
|
||||
PLD_PWR &= ~(PLD_S4_ON|PLD_S3_ON|PLD_S2_ON|PLD_S1_ON);
|
||||
|
||||
PLD_KBD = 0;
|
||||
PLD_IO = 0;
|
||||
PLD_IRDA = 0;
|
||||
PLD_CODEC = 0;
|
||||
PLD_TCH = 0;
|
||||
PLD_SPI = 0;
|
||||
if (!IS_ENABLED(CONFIG_DEBUG_LL)) {
|
||||
PLD_COM2 = 0;
|
||||
PLD_COM1 = 0;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* LED controled by CPLD
|
||||
*/
|
||||
#if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS)
|
||||
static void p720t_led_set(struct led_classdev *cdev,
|
||||
enum led_brightness b)
|
||||
{
|
||||
u8 reg = clps_readb(PDDR);
|
||||
|
||||
if (b != LED_OFF)
|
||||
reg |= 0x1;
|
||||
else
|
||||
reg &= ~0x1;
|
||||
|
||||
clps_writeb(reg, PDDR);
|
||||
}
|
||||
|
||||
static enum led_brightness p720t_led_get(struct led_classdev *cdev)
|
||||
{
|
||||
u8 reg = clps_readb(PDDR);
|
||||
|
||||
return (reg & 0x1) ? LED_FULL : LED_OFF;
|
||||
}
|
||||
|
||||
static int __init p720t_leds_init(void)
|
||||
{
|
||||
|
||||
struct led_classdev *cdev;
|
||||
int ret;
|
||||
|
||||
if (!machine_is_p720t())
|
||||
return -ENODEV;
|
||||
|
||||
cdev = kzalloc(sizeof(*cdev), GFP_KERNEL);
|
||||
if (!cdev)
|
||||
return -ENOMEM;
|
||||
|
||||
cdev->name = "p720t:0";
|
||||
cdev->brightness_set = p720t_led_set;
|
||||
cdev->brightness_get = p720t_led_get;
|
||||
cdev->default_trigger = "heartbeat";
|
||||
|
||||
ret = led_classdev_register(NULL, cdev);
|
||||
if (ret < 0) {
|
||||
kfree(cdev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Since we may have triggers on any subsystem, defer registration
|
||||
* until after subsystem_init.
|
||||
*/
|
||||
fs_initcall(p720t_leds_init);
|
||||
#endif
|
||||
|
||||
MACHINE_START(P720T, "ARM-Prospector720T")
|
||||
/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
|
||||
.atag_offset = 0x100,
|
||||
.fixup = fixup_p720t,
|
||||
.init_early = p720t_init_early,
|
||||
.map_io = p720t_map_io,
|
||||
.init_irq = clps711x_init_irq,
|
||||
.timer = &clps711x_timer,
|
||||
.restart = clps711x_restart,
|
||||
MACHINE_END
|
||||
|
|
@ -324,7 +324,7 @@ static __init void dm355_evm_init(void)
|
|||
if (IS_ERR(aemif))
|
||||
WARN("%s: unable to get AEMIF clock\n", __func__);
|
||||
else
|
||||
clk_enable(aemif);
|
||||
clk_prepare_enable(aemif);
|
||||
|
||||
platform_add_devices(davinci_evm_devices,
|
||||
ARRAY_SIZE(davinci_evm_devices));
|
||||
|
|
|
|||
|
|
@ -246,7 +246,7 @@ static __init void dm355_leopard_init(void)
|
|||
if (IS_ERR(aemif))
|
||||
WARN("%s: unable to get AEMIF clock\n", __func__);
|
||||
else
|
||||
clk_enable(aemif);
|
||||
clk_prepare_enable(aemif);
|
||||
|
||||
platform_add_devices(davinci_leopard_devices,
|
||||
ARRAY_SIZE(davinci_leopard_devices));
|
||||
|
|
|
|||
|
|
@ -478,7 +478,7 @@ static void __init evm_init_cpld(void)
|
|||
aemif_clk = clk_get(NULL, "aemif");
|
||||
if (IS_ERR(aemif_clk))
|
||||
return;
|
||||
clk_enable(aemif_clk);
|
||||
clk_prepare_enable(aemif_clk);
|
||||
|
||||
if (request_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE,
|
||||
"cpld") == NULL)
|
||||
|
|
@ -489,7 +489,7 @@ static void __init evm_init_cpld(void)
|
|||
SECTION_SIZE);
|
||||
fail:
|
||||
pr_err("ERROR: can't map CPLD\n");
|
||||
clk_disable(aemif_clk);
|
||||
clk_disable_unprepare(aemif_clk);
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -777,7 +777,7 @@ static __init void davinci_evm_init(void)
|
|||
struct davinci_soc_info *soc_info = &davinci_soc_info;
|
||||
|
||||
aemif_clk = clk_get(NULL, "aemif");
|
||||
clk_enable(aemif_clk);
|
||||
clk_prepare_enable(aemif_clk);
|
||||
|
||||
if (HAS_ATA) {
|
||||
if (HAS_NAND || HAS_NOR)
|
||||
|
|
|
|||
|
|
@ -188,7 +188,7 @@ static __init void davinci_ntosd2_init(void)
|
|||
struct davinci_soc_info *soc_info = &davinci_soc_info;
|
||||
|
||||
aemif_clk = clk_get(NULL, "aemif");
|
||||
clk_enable(aemif_clk);
|
||||
clk_prepare_enable(aemif_clk);
|
||||
|
||||
if (HAS_ATA) {
|
||||
if (HAS_NAND)
|
||||
|
|
|
|||
|
|
@ -212,6 +212,12 @@ static struct clk tptc2_clk = {
|
|||
.flags = ALWAYS_ENABLED,
|
||||
};
|
||||
|
||||
static struct clk pruss_clk = {
|
||||
.name = "pruss",
|
||||
.parent = &pll0_sysclk2,
|
||||
.lpsc = DA8XX_LPSC0_PRUSS,
|
||||
};
|
||||
|
||||
static struct clk uart0_clk = {
|
||||
.name = "uart0",
|
||||
.parent = &pll0_sysclk2,
|
||||
|
|
@ -385,6 +391,7 @@ static struct clk_lookup da850_clks[] = {
|
|||
CLK(NULL, "tptc1", &tptc1_clk),
|
||||
CLK(NULL, "tpcc1", &tpcc1_clk),
|
||||
CLK(NULL, "tptc2", &tptc2_clk),
|
||||
CLK("pruss_uio", "pruss", &pruss_clk),
|
||||
CLK(NULL, "uart0", &uart0_clk),
|
||||
CLK(NULL, "uart1", &uart1_clk),
|
||||
CLK(NULL, "uart2", &uart2_clk),
|
||||
|
|
@ -781,12 +788,6 @@ static struct map_desc da850_io_desc[] = {
|
|||
.length = DA8XX_CP_INTC_SIZE,
|
||||
.type = MT_DEVICE
|
||||
},
|
||||
{
|
||||
.virtual = SRAM_VIRT,
|
||||
.pfn = __phys_to_pfn(DA8XX_ARM_RAM_BASE),
|
||||
.length = SZ_8K,
|
||||
.type = MT_DEVICE
|
||||
},
|
||||
};
|
||||
|
||||
static u32 da850_psc_bases[] = { DA8XX_PSC0_BASE, DA8XX_PSC1_BASE };
|
||||
|
|
@ -1239,8 +1240,8 @@ static struct davinci_soc_info davinci_soc_info_da850 = {
|
|||
.gpio_irq = IRQ_DA8XX_GPIO0,
|
||||
.serial_dev = &da8xx_serial_device,
|
||||
.emac_pdata = &da8xx_emac_pdata,
|
||||
.sram_dma = DA8XX_ARM_RAM_BASE,
|
||||
.sram_len = SZ_8K,
|
||||
.sram_dma = DA8XX_SHARED_RAM_BASE,
|
||||
.sram_len = SZ_128K,
|
||||
};
|
||||
|
||||
void __init da850_init(void)
|
||||
|
|
|
|||
|
|
@ -22,6 +22,7 @@
|
|||
#include <mach/time.h>
|
||||
#include <mach/da8xx.h>
|
||||
#include <mach/cpuidle.h>
|
||||
#include <mach/sram.h>
|
||||
|
||||
#include "clock.h"
|
||||
#include "asp.h"
|
||||
|
|
@ -32,6 +33,7 @@
|
|||
#define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */
|
||||
#define DA8XX_I2C0_BASE 0x01c22000
|
||||
#define DA8XX_RTC_BASE 0x01c23000
|
||||
#define DA8XX_PRUSS_MEM_BASE 0x01c30000
|
||||
#define DA8XX_MMCSD0_BASE 0x01c40000
|
||||
#define DA8XX_SPI0_BASE 0x01c41000
|
||||
#define DA830_SPI1_BASE 0x01e12000
|
||||
|
|
@ -518,6 +520,75 @@ void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
|
|||
}
|
||||
}
|
||||
|
||||
static struct resource da8xx_pruss_resources[] = {
|
||||
{
|
||||
.start = DA8XX_PRUSS_MEM_BASE,
|
||||
.end = DA8XX_PRUSS_MEM_BASE + 0xFFFF,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = IRQ_DA8XX_EVTOUT0,
|
||||
.end = IRQ_DA8XX_EVTOUT0,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_DA8XX_EVTOUT1,
|
||||
.end = IRQ_DA8XX_EVTOUT1,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_DA8XX_EVTOUT2,
|
||||
.end = IRQ_DA8XX_EVTOUT2,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_DA8XX_EVTOUT3,
|
||||
.end = IRQ_DA8XX_EVTOUT3,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_DA8XX_EVTOUT4,
|
||||
.end = IRQ_DA8XX_EVTOUT4,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_DA8XX_EVTOUT5,
|
||||
.end = IRQ_DA8XX_EVTOUT5,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_DA8XX_EVTOUT6,
|
||||
.end = IRQ_DA8XX_EVTOUT6,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_DA8XX_EVTOUT7,
|
||||
.end = IRQ_DA8XX_EVTOUT7,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct uio_pruss_pdata da8xx_uio_pruss_pdata = {
|
||||
.pintc_base = 0x4000,
|
||||
};
|
||||
|
||||
static struct platform_device da8xx_uio_pruss_dev = {
|
||||
.name = "pruss_uio",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(da8xx_pruss_resources),
|
||||
.resource = da8xx_pruss_resources,
|
||||
.dev = {
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
.platform_data = &da8xx_uio_pruss_pdata,
|
||||
}
|
||||
};
|
||||
|
||||
int __init da8xx_register_uio_pruss(void)
|
||||
{
|
||||
da8xx_uio_pruss_pdata.sram_pool = sram_get_gen_pool();
|
||||
return platform_device_register(&da8xx_uio_pruss_dev);
|
||||
}
|
||||
|
||||
static const struct display_panel disp_panel = {
|
||||
QVGA,
|
||||
16,
|
||||
|
|
@ -900,7 +971,7 @@ static int da850_sata_init(struct device *dev, void __iomem *addr)
|
|||
if (IS_ERR(da850_sata_clk))
|
||||
return PTR_ERR(da850_sata_clk);
|
||||
|
||||
ret = clk_enable(da850_sata_clk);
|
||||
ret = clk_prepare_enable(da850_sata_clk);
|
||||
if (ret)
|
||||
goto err0;
|
||||
|
||||
|
|
@ -931,7 +1002,7 @@ static int da850_sata_init(struct device *dev, void __iomem *addr)
|
|||
return 0;
|
||||
|
||||
err1:
|
||||
clk_disable(da850_sata_clk);
|
||||
clk_disable_unprepare(da850_sata_clk);
|
||||
err0:
|
||||
clk_put(da850_sata_clk);
|
||||
return ret;
|
||||
|
|
@ -939,7 +1010,7 @@ static int da850_sata_init(struct device *dev, void __iomem *addr)
|
|||
|
||||
static void da850_sata_exit(struct device *dev)
|
||||
{
|
||||
clk_disable(da850_sata_clk);
|
||||
clk_disable_unprepare(da850_sata_clk);
|
||||
clk_put(da850_sata_clk);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -758,12 +758,6 @@ static struct map_desc dm355_io_desc[] = {
|
|||
.length = IO_SIZE,
|
||||
.type = MT_DEVICE
|
||||
},
|
||||
{
|
||||
.virtual = SRAM_VIRT,
|
||||
.pfn = __phys_to_pfn(0x00010000),
|
||||
.length = SZ_32K,
|
||||
.type = MT_MEMORY_NONCACHED,
|
||||
},
|
||||
};
|
||||
|
||||
/* Contents of JTAG ID register used to identify exact cpu type */
|
||||
|
|
|
|||
|
|
@ -985,12 +985,6 @@ static struct map_desc dm365_io_desc[] = {
|
|||
.length = IO_SIZE,
|
||||
.type = MT_DEVICE
|
||||
},
|
||||
{
|
||||
.virtual = SRAM_VIRT,
|
||||
.pfn = __phys_to_pfn(0x00010000),
|
||||
.length = SZ_32K,
|
||||
.type = MT_MEMORY_NONCACHED,
|
||||
},
|
||||
};
|
||||
|
||||
static struct resource dm365_ks_resources[] = {
|
||||
|
|
|
|||
|
|
@ -785,12 +785,6 @@ static struct map_desc dm644x_io_desc[] = {
|
|||
.length = IO_SIZE,
|
||||
.type = MT_DEVICE
|
||||
},
|
||||
{
|
||||
.virtual = SRAM_VIRT,
|
||||
.pfn = __phys_to_pfn(0x00008000),
|
||||
.length = SZ_16K,
|
||||
.type = MT_MEMORY_NONCACHED,
|
||||
},
|
||||
};
|
||||
|
||||
/* Contents of JTAG ID register used to identify exact cpu type */
|
||||
|
|
|
|||
|
|
@ -756,12 +756,6 @@ static struct map_desc dm646x_io_desc[] = {
|
|||
.length = IO_SIZE,
|
||||
.type = MT_DEVICE
|
||||
},
|
||||
{
|
||||
.virtual = SRAM_VIRT,
|
||||
.pfn = __phys_to_pfn(0x00010000),
|
||||
.length = SZ_32K,
|
||||
.type = MT_MEMORY_NONCACHED,
|
||||
},
|
||||
};
|
||||
|
||||
/* Contents of JTAG ID register used to identify exact cpu type */
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
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Reference in New Issue