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ARM i.MX cleanup patches 

-----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.12 (GNU/Linux)
 
 iQIcBAABCAAGBQJQUGxJAAoJEPFlmONMx+ezLvcP/iQdHZN16q16alaGYFzYiEMO
 9HjqQ5vrdDsijIAmkSwgBdsTQqyQd+decWOD4EGqcx+zWGYDK0gtcLmXGJREGHeP
 WHWWsleynE7eBpUgiC+axT7T/FDseSk4eqJZ9CuNC/A++EYBxnPMpEBEWyTFdjqB
 TCin9BRnPXNepqhzdkkL/ZAhcUu5/TF3Rvnp9btM6uUEhAzNWC+B9EuHk9JwwQV+
 hDs7e7JcV1BBXAXiI5obfgD2W4a5eKZHbce8y7PGn+6jCbXEgICF8woyeTzeaCnG
 K/11zSIlojc9ey/RJCvDzkyskjcyo4UyFX5U9un12BLYLH52saDeINuwbZVEkrV/
 K33QOio6eolPlAsypgQA0f5aZ18oLA1MiRASi4zg5fdDFbpyYxSqo/zMAlseNGrk
 OYvNROVC6VVItnzjvwNPPSdQIZsHTuy9dPOY1YwuhV1BbCyx+h8SOk4PXvn1CqGd
 k9xLo+e3EJrmOUkFP3hfI22tuZ5ljg6mZVUbQ0jyiqL6gLEP/sy2xWmzA9NywVBK
 75vcYwXBsODcaGhacHsiNP630JlEzN0TX1slqtPLC5GLZ/ij9e9xiEKtTHmazyr9
 Ia5vJDv3agDRsQUOjpoQ8AUDFjD2q8wLTHzpVLeNwgzxpQysR650CJOOR0ddCERL
 cedvoX99sFp4xejGoSYT
 =2GuG
 -----END PGP SIGNATURE-----

Merge tag 'imx-cleanup' of git://git.pengutronix.de/git/imx/linux-2.6 into next/cleanup

ARM i.MX cleanup patches

* tag 'imx-cleanup' of git://git.pengutronix.de/git/imx/linux-2.6:
  ARM i.MX53 clk: Fix ldb parent clocks
  serial/imx: fix IMX UART macro usage to reflect correct processor
  ARM: i.MX remove last leftovers from legacy clock support
  ARM: i.MX clk pllv1: move mxc_decode_pll code to its user
  ARM: imx27-phytec-phycore: Fix I2C EEPROM address
  ARM i.MX mx2_camera: Remove MX2_CAMERA_SWAP16 and MX2_CAMERA_PACK_DIR_MSB flags.
  ARM i.MX: remove duplicated include from clk-imx21.c
  ARM: plat-mxc: Remove unused imx_ioremap
This commit is contained in:
Olof Johansson 2012-09-16 16:58:49 -07:00
parent 025c95a682 51f66191cf
commit d0312d7edc
15 changed files with 58 additions and 345 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/boot/dts/imx27-phytec-phycore.dts
View File

@ -49,7 +49,7 @@ ethernet@1002b000 {
i2c@1001d000 {
clock-frequency = <400000>;
status = "okay";
at24@4c {
at24@52 {
compatible = "at,24c32";
pagesize = <32>;
reg = <0x52>;

2
arch/arm/mach-imx/Makefile
View File

@ -13,7 +13,7 @@ imx5-pm-$(CONFIG_PM) += pm-imx5.o
obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o $(imx5-pm-y) cpu_op-mx51.o
obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \
clk-pfd.o clk-busy.o
clk-pfd.o clk-busy.o clk.o
# Support for CMOS sensor interface
obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o

1
arch/arm/mach-imx/clk-imx21.c
View File

@ -23,7 +23,6 @@
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/clkdev.h>
#include <linux/err.h>
#include <mach/hardware.h>

4
arch/arm/mach-imx/clk-imx51-imx53.c
View File

@ -39,10 +39,10 @@ static const char *ssi_ext2_com_sels[] = { "ssi_ext2_podf", "ssi2_root_gate", };
static const char *emi_slow_sel[] = { "main_bus", "ahb", };
static const char *usb_phy_sel_str[] = { "osc", "usb_phy_podf", };
static const char *mx51_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "tve_di", };
static const char *mx53_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "di_pll4_podf", "dummy", "ldb_di0", };
static const char *mx53_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "di_pll4_podf", "dummy", "ldb_di0_gate", };
static const char *mx53_ldb_di0_sel[] = { "pll3_sw", "pll4_sw", };
static const char *mx51_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", };
static const char *mx53_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", "ldb_di1", };
static const char *mx53_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", "ldb_di1_gate", };
static const char *mx53_ldb_di1_sel[] = { "pll3_sw", "pll4_sw", };
static const char *mx51_tve_ext_sel[] = { "osc", "ckih1", };
static const char *mx53_tve_ext_sel[] = { "pll4_sw", "ckih1", };

49
arch/arm/mach-imx/clk-pllv1.c
View File

@ -6,7 +6,7 @@
#include <linux/err.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/clock.h>
#include "clk.h"
/**
@ -29,8 +29,53 @@ static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct clk_pllv1 *pll = to_clk_pllv1(hw);
long long ll;
int mfn_abs;
unsigned int mfi, mfn, mfd, pd;
u32 reg;
unsigned long rate;
return mxc_decode_pll(readl(pll->base), parent_rate);
reg = readl(pll->base);
/*
* Get the resulting clock rate from a PLL register value and the input
* frequency. PLLs with this register layout can be found on i.MX1,
* i.MX21, i.MX27 and i,MX31
*
* mfi + mfn / (mfd + 1)
* f = 2 * f_ref * --------------------
* pd + 1
*/
mfi = (reg >> 10) & 0xf;
mfn = reg & 0x3ff;
mfd = (reg >> 16) & 0x3ff;
pd = (reg >> 26) & 0xf;
mfi = mfi <= 5 ? 5 : mfi;
mfn_abs = mfn;
/*
* On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit
* 2's complements number
*/
if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
mfn_abs = 0x400 - mfn;
rate = parent_rate * 2;
rate /= pd + 1;
ll = (unsigned long long)rate * mfn_abs;
do_div(ll, mfd + 1);
if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
ll = -ll;
ll = (rate * mfi) + ll;
return ll;
}
struct clk_ops clk_pllv1_ops = {

3
arch/arm/mach-imx/clk.c Normal file
View File

@ -0,0 +1,3 @@
#include <linux/spinlock.h>
DEFINE_SPINLOCK(imx_ccm_lock);

3
arch/arm/mach-imx/clk.h
View File

@ -3,7 +3,8 @@
#include <linux/spinlock.h>
#include <linux/clk-provider.h>
#include <mach/clock.h>
extern spinlock_t imx_ccm_lock;
struct clk *imx_clk_pllv1(const char *name, const char *parent,
void __iomem *base);

1
arch/arm/mach-imx/mach-kzm_arm11_01.c
View File

@ -36,7 +36,6 @@
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <mach/clock.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx3.h>

2
arch/arm/plat-mxc/Makefile
View File

@ -3,7 +3,7 @@
#
# Common support
obj-y := clock.o time.o devices.o cpu.o system.o irq-common.o
obj-y := time.o devices.o cpu.o system.o irq-common.o
obj-$(CONFIG_MXC_TZIC) += tzic.o
obj-$(CONFIG_MXC_AVIC) += avic.o

257
arch/arm/plat-mxc/clock.c
View File

@ -1,257 +0,0 @@
/*
* Based on arch/arm/plat-omap/clock.c
*
* Copyright (C) 2004 - 2005 Nokia corporation
* Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
* Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
* Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
/* #define DEBUG */
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/platform_device.h>
#include <linux/proc_fs.h>
#include <linux/semaphore.h>
#include <linux/string.h>
#include <mach/clock.h>
#include <mach/hardware.h>
#ifndef CONFIG_COMMON_CLK
static LIST_HEAD(clocks);
static DEFINE_MUTEX(clocks_mutex);
/*-------------------------------------------------------------------------
* Standard clock functions defined in include/linux/clk.h
*-------------------------------------------------------------------------*/
static void __clk_disable(struct clk *clk)
{
if (clk == NULL || IS_ERR(clk))
return;
WARN_ON(!clk->usecount);
if (!(--clk->usecount)) {
if (clk->disable)
clk->disable(clk);
__clk_disable(clk->parent);
__clk_disable(clk->secondary);
}
}
static int __clk_enable(struct clk *clk)
{
if (clk == NULL || IS_ERR(clk))
return -EINVAL;
if (clk->usecount++ == 0) {
__clk_enable(clk->parent);
__clk_enable(clk->secondary);
if (clk->enable)
clk->enable(clk);
}
return 0;
}
/* This function increments the reference count on the clock and enables the
* clock if not already enabled. The parent clock tree is recursively enabled
*/
int clk_enable(struct clk *clk)
{
int ret = 0;
if (clk == NULL || IS_ERR(clk))
return -EINVAL;
mutex_lock(&clocks_mutex);
ret = __clk_enable(clk);
mutex_unlock(&clocks_mutex);
return ret;
}
EXPORT_SYMBOL(clk_enable);
/* This function decrements the reference count on the clock and disables
* the clock when reference count is 0. The parent clock tree is
* recursively disabled
*/
void clk_disable(struct clk *clk)
{
if (clk == NULL || IS_ERR(clk))
return;
mutex_lock(&clocks_mutex);
__clk_disable(clk);
mutex_unlock(&clocks_mutex);
}
EXPORT_SYMBOL(clk_disable);
/* Retrieve the *current* clock rate. If the clock itself
* does not provide a special calculation routine, ask
* its parent and so on, until one is able to return
* a valid clock rate
*/
unsigned long clk_get_rate(struct clk *clk)
{
if (clk == NULL || IS_ERR(clk))
return 0UL;
if (clk->get_rate)
return clk->get_rate(clk);
return clk_get_rate(clk->parent);
}
EXPORT_SYMBOL(clk_get_rate);
/* Round the requested clock rate to the nearest supported
* rate that is less than or equal to the requested rate.
* This is dependent on the clock's current parent.
*/
long clk_round_rate(struct clk *clk, unsigned long rate)
{
if (clk == NULL || IS_ERR(clk) || !clk->round_rate)
return 0;
return clk->round_rate(clk, rate);
}
EXPORT_SYMBOL(clk_round_rate);
/* Set the clock to the requested clock rate. The rate must
* match a supported rate exactly based on what clk_round_rate returns
*/
int clk_set_rate(struct clk *clk, unsigned long rate)
{
int ret = -EINVAL;
if (clk == NULL || IS_ERR(clk) || clk->set_rate == NULL || rate == 0)
return ret;
mutex_lock(&clocks_mutex);
ret = clk->set_rate(clk, rate);
mutex_unlock(&clocks_mutex);
return ret;
}
EXPORT_SYMBOL(clk_set_rate);
/* Set the clock's parent to another clock source */
int clk_set_parent(struct clk *clk, struct clk *parent)
{
int ret = -EINVAL;
struct clk *old;
if (clk == NULL || IS_ERR(clk) || parent == NULL ||
IS_ERR(parent) || clk->set_parent == NULL)
return ret;
if (clk->usecount)
clk_enable(parent);
mutex_lock(&clocks_mutex);
ret = clk->set_parent(clk, parent);
if (ret == 0) {
old = clk->parent;
clk->parent = parent;
} else {
old = parent;
}
mutex_unlock(&clocks_mutex);
if (clk->usecount)
clk_disable(old);
return ret;
}
EXPORT_SYMBOL(clk_set_parent);
/* Retrieve the clock's parent clock source */
struct clk *clk_get_parent(struct clk *clk)
{
struct clk *ret = NULL;
if (clk == NULL || IS_ERR(clk))
return ret;
return clk->parent;
}
EXPORT_SYMBOL(clk_get_parent);
#else
/*
* Lock to protect the clock module (ccm) registers. Used
* on all i.MXs
*/
DEFINE_SPINLOCK(imx_ccm_lock);
#endif /* CONFIG_COMMON_CLK */
/*
* Get the resulting clock rate from a PLL register value and the input
* frequency. PLLs with this register layout can at least be found on
* MX1, MX21, MX27 and MX31
*
* mfi + mfn / (mfd + 1)
* f = 2 * f_ref * --------------------
* pd + 1
*/
unsigned long mxc_decode_pll(unsigned int reg_val, u32 freq)
{
long long ll;
int mfn_abs;
unsigned int mfi, mfn, mfd, pd;
mfi = (reg_val >> 10) & 0xf;
mfn = reg_val & 0x3ff;
mfd = (reg_val >> 16) & 0x3ff;
pd = (reg_val >> 26) & 0xf;
mfi = mfi <= 5 ? 5 : mfi;
mfn_abs = mfn;
/* On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit
* 2's complements number
*/
if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
mfn_abs = 0x400 - mfn;
freq *= 2;
freq /= pd + 1;
ll = (unsigned long long)freq * mfn_abs;
do_div(ll, mfd + 1);
if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
ll = -ll;
ll = (freq * mfi) + ll;
return ll;
}

1
arch/arm/plat-mxc/cpufreq.c
View File

@ -23,7 +23,6 @@
#include <linux/err.h>
#include <linux/slab.h>
#include <mach/hardware.h>
#include <mach/clock.h>
#define CLK32_FREQ 32768
#define NANOSECOND (1000 * 1000 * 1000)

2
arch/arm/plat-mxc/devices/platform-imx-uart.c
View File

@ -87,7 +87,7 @@ const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst = {
#ifdef CONFIG_SOC_IMX35
const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = {
#define imx35_imx_uart_data_entry(_id, _hwid) \
imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_16K)
imx_imx_uart_1irq_data_entry(MX35, _id, _hwid, SZ_16K)
imx35_imx_uart_data_entry(0, 1),
imx35_imx_uart_data_entry(1, 2),
imx35_imx_uart_data_entry(2, 3),

70
arch/arm/plat-mxc/include/mach/clock.h
View File

@ -1,70 +0,0 @@
/*
* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#ifndef __ASM_ARCH_MXC_CLOCK_H__
#define __ASM_ARCH_MXC_CLOCK_H__
#ifndef __ASSEMBLY__
#include <linux/list.h>
#ifndef CONFIG_COMMON_CLK
struct module;
struct clk {
int id;
/* Source clock this clk depends on */
struct clk *parent;
/* Secondary clock to enable/disable with this clock */
struct clk *secondary;
/* Reference count of clock enable/disable */
__s8 usecount;
/* Register bit position for clock's enable/disable control. */
u8 enable_shift;
/* Register address for clock's enable/disable control. */
void __iomem *enable_reg;
u32 flags;
/* get the current clock rate (always a fresh value) */
unsigned long (*get_rate) (struct clk *);
/* Function ptr to set the clock to a new rate. The rate must match a
supported rate returned from round_rate. Leave blank if clock is not
programmable */
int (*set_rate) (struct clk *, unsigned long);
/* Function ptr to round the requested clock rate to the nearest
supported rate that is less than or equal to the requested rate. */
unsigned long (*round_rate) (struct clk *, unsigned long);
/* Function ptr to enable the clock. Leave blank if clock can not
be gated. */
int (*enable) (struct clk *);
/* Function ptr to disable the clock. Leave blank if clock can not
be gated. */
void (*disable) (struct clk *);
/* Function ptr to set the parent clock of the clock. */
int (*set_parent) (struct clk *, struct clk *);
};
int clk_register(struct clk *clk);
void clk_unregister(struct clk *clk);
#endif /* CONFIG_COMMON_CLK */
extern spinlock_t imx_ccm_lock;
unsigned long mxc_decode_pll(unsigned int pll, u32 f_ref);
#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARCH_MXC_CLOCK_H__ */

2
arch/arm/plat-mxc/include/mach/mx2_cam.h
View File

@ -23,7 +23,6 @@
#ifndef __MACH_MX2_CAM_H_
#define __MACH_MX2_CAM_H_
#define MX2_CAMERA_SWAP16 (1 << 0)
#define MX2_CAMERA_EXT_VSYNC (1 << 1)
#define MX2_CAMERA_CCIR (1 << 2)
#define MX2_CAMERA_CCIR_INTERLACE (1 << 3)
@ -31,7 +30,6 @@
#define MX2_CAMERA_GATED_CLOCK (1 << 5)
#define MX2_CAMERA_INV_DATA (1 << 6)
#define MX2_CAMERA_PCLK_SAMPLE_RISING (1 << 7)
#define MX2_CAMERA_PACK_DIR_MSB (1 << 8)
/**
* struct mx2_camera_platform_data - optional platform data for mx2_camera

4
arch/arm/plat-mxc/system.c
View File

@ -21,7 +21,6 @@
#include <linux/io.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <mach/hardware.h>
#include <mach/common.h>
@ -29,9 +28,6 @@
#include <asm/proc-fns.h>
#include <asm/mach-types.h>
void __iomem *(*imx_ioremap)(unsigned long, size_t, unsigned int) = NULL;
EXPORT_SYMBOL_GPL(imx_ioremap);
static void __iomem *wdog_base;
/*