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arm64: dts: allwinner: h5: Add trip and cooling maps to CPU thermal zones 

This enables passive cooling by down-regulating CPU voltage and frequency.
The trip points were copied from the H3.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20200717160053.31191-6-wens@kernel.org
This commit is contained in:
Chen-Yu Tsai 2020-07-18 00:00:50 +08:00 committed by Maxime Ripard
parent 5fa21c1354
commit d04f7bc884
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GPG Key ID: E3EF0D6F671851C5
1 changed files with 30 additions and 0 deletions
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30
arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
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@ -3,6 +3,8 @@
#include <arm/sunxi-h3-h5.dtsi>
#include <dt-bindings/thermal/thermal.h>
/ {
cpus {
#address-cells = <1>;
@ -15,6 +17,7 @@ cpu0: cpu@0 {
enable-method = "psci";
clocks = <&ccu CLK_CPUX>;
clock-latency-ns = <244144>; /* 8 32k periods */
#cooling-cells = <2>;
};
cpu1: cpu@1 {
@ -24,6 +27,7 @@ cpu1: cpu@1 {
enable-method = "psci";
clocks = <&ccu CLK_CPUX>;
clock-latency-ns = <244144>; /* 8 32k periods */
#cooling-cells = <2>;
};
cpu2: cpu@2 {
@ -33,6 +37,7 @@ cpu2: cpu@2 {
enable-method = "psci";
clocks = <&ccu CLK_CPUX>;
clock-latency-ns = <244144>; /* 8 32k periods */
#cooling-cells = <2>;
};
cpu3: cpu@3 {
@ -42,6 +47,7 @@ cpu3: cpu@3 {
enable-method = "psci";
clocks = <&ccu CLK_CPUX>;
clock-latency-ns = <244144>; /* 8 32k periods */
#cooling-cells = <2>;
};
};
@ -173,6 +179,30 @@ cpu_thermal: cpu-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&ths 0>;
trips {
cpu_hot_trip: cpu-hot {
temperature = <80000>;
hysteresis = <2000>;
type = "passive";
};
cpu_very_hot_trip: cpu-very-hot {
temperature = <100000>;
hysteresis = <0>;
type = "critical";
};
};
cooling-maps {
cpu-hot-limit {
trip = <&cpu_hot_trip>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
gpu_thermal {